Stefan Roese wrote:
Is this an expected behavior - detection of 256 MiB NAND flash
takes around 20 seconds. The ndfc driver works fine after boot.
No, 20 seconds is definitely too long. Something must be wrong with the
ndfc
driver or the NAND dts entries.
Best regards,
Stefan
Stefan Roese wrote:
Is this an expected behavior - detection of 256 MiB NAND flash
takes around 20 seconds. The ndfc driver works fine after boot.
No, 20 seconds is definitely too long. Something must be wrong with the
ndfc
driver or the NAND dts entries.
Best regards,
Stefan
On Fri, Dec 19, 2008 at 04:13:22PM +1100, Benjamin Herrenschmidt wrote:
This adds supports to the extended DCR addressing via
the indirect mfdcrx/mtdcrx instructions supported by some
4xx cores (440H6 and later)
I enabled the feature for now only on AMCC 460 chips
Signed-off-by: Benjamin
On Fri, Dec 19, 2008 at 04:13:46PM +1100, Benjamin Herrenschmidt wrote:
The handlers for Critical, Machine Check or Debug interrupts
will save and restore MMUCR nowadays, thus we only need to
disable normal interrupts when invalidating TLB entries.
Signed-off-by: Benjamin Herrenschmidt
On Fri, Dec 19, 2008 at 04:13:54PM +1100, Benjamin Herrenschmidt wrote:
After discussing with chip designers, it appears that it's not
necessary to set G everywhere on 440 cores. The various core
errata related to prefetch should be sorted out by firmware by
disabling icache prefetching in CCR0.
On Dec 18, 2008, at 11:13 PM, Benjamin Herrenschmidt wrote:
This series of patches is aimed at supporting SMP on non-hash
based processors. It consists of a rework of the MMU context
management and TLB management, clearly splitting hash32, hash64
and nohash in both cases, adding SMP safe
The correct #address-cells was still used for the actual translation,
so the impact is only a possibility of choosing the wrong range entry
or failing to find any match. Most common cases were not affected.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/boot/devtree.c |2
On Fri, 19 Dec 2008 08:44:57 +0300
Yuri Tikhonov y...@emcraft.com wrote:
The following patch fixes division by zero, which we have in
shmem_truncate_range() and shmem_unuse_inode(), if use big
PAGE_SIZE values (e.g. 256KB on ppc44x).
With 256KB PAGE_SIZE the ENTRIES_PER_PAGEPAGE constant
Stefan Roese wrote:
On Friday 19 December 2008, Felix Radensky wrote:
Thanks a lot to everyone who replied. I've managed to identify the cause
of the delay. The board is equipped with 256 MiB Samsung NAND flash.
Since NAND support is a must for this platform, I've intergated the ndfc
driver
The newest revision of uboot reworks the memory map for this
board to look more like the 85xx boards. Also, some regions
which were far larger than the actual hardware have been scaled
back to match the board, and the imaginary second flash bank has
been removed. Rapidio and PCI are mutually
From: Grant Likely grant.lik...@secretlab.ca
The MPC5200 internal interrupt controller setup function needs to set
the default interrupt controller when it is called. Without this
irq_create_of_mapping() cannot be called without first determining
the pointer to the irq controller (ie. call with
Hi,
Is the thermal diode on a 970FX used on a G5? Can it be read by
software?
kevin
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On Fri, 2008-12-19 at 18:54 -0800, Kevin Diggs wrote:
Hi,
Is the thermal diode on a 970FX used on a G5? Can it be read by
software?
The existing thermal control should do all you need already :-)
Cheers,
Ben.
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On Fri, 19 Dec 2008 23:23:58 +0200
Felix Radensky fe...@embedded-sol.com wrote:
Hi, Sean
Do you have any ideas what can cause such delay ?
Sorry, I haven't been following this thread :(
We also use a 256M NAND, although a Spansion S29GL. While there is a
small delay in u-boot, there is no
Sean MacLennan-2 wrote:
On Fri, 19 Dec 2008 23:23:58 +0200
Felix Radensky fe...@embedded-sol.com wrote:
Hi, Sean
Do you have any ideas what can cause such delay ?
Sorry, I haven't been following this thread :(
We also use a 256M NAND, although a Spansion S29GL. While there is a
On Tue, Nov 25, 2008 at 8:19 AM, Matt Sealey m...@genesi-usa.com wrote:
On Tue, Nov 25, 2008 at 8:45 AM, Lehmann, Hans (Ritter Elektronik)
hans.lehm...@ritter-elektronik.de wrote:
Tim, Grant,
just an info.
Very often the Bestcomm-FEC crashed without any error logs if I initiate a
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