Re: Regarding FPGA based cascaded PIC

2009-11-04 Thread Benjamin Herrenschmidt
On Thu, 2009-11-05 at 08:16 +0530, thirumalai.p wrote: > > I Understood the thing. Thank you very much. So you mean to say that > my map/xlate functions will get invoked only for the devices which is > connected the FPGA PIC. Right, and I fail to see how it would make any sense the other way aro

Re: Regarding FPGA based cascaded PIC

2009-11-04 Thread thirumalai.p
On Thu, 05 Nov 2009 07:51:22 +1100, Benjamin Herrenschmidt wrote: > On Wed, 2009-11-04 at 18:09 +0530, Thirumalai wrote: >> you understood correctly. Here the problem lies.Correct me if i am wrong. >> So >> you are telling that irq_of_parse_and_map() will invoke the map/xlate of >> my >> FPGA pic.

Re: [PATCH] PCI: Fix regression in powerpc MSI-X

2009-11-04 Thread Michael Ellerman
On Wed, 2009-11-04 at 13:03 -0200, Andre Detsch wrote: > Patch f598282f5145036312d90875d0ed5c14b49fd8a7 exposed a problem in > powerpc MSI-X functionality, making network interfaces such as ixgbe > and cxgb3 stop to work when MSI-X is enabled. RX interrupts were not > being generated. Which means

Re: [PATCH 14/27] Add book3s_64 specific opcode emulation

2009-11-04 Thread Segher Boessenkool
+ case OP_31_XOP_EIOIO: + break; Have you always executed an eieio or sync when you get here, or do you just not allow direct access to I/O devices? Other context synchronising insns are not enough, they do not broadcast on the bus. There is no device passt

Re: [PATCH] BUILD_BUG_ON: make it handle more cases

2009-11-04 Thread Stephen Rothwell
Hi Rusty, On Tue, 20 Oct 2009 14:15:33 +1030 Rusty Russell wrote: > > +#ifndef __OPTIMIZE__ > +#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) > +#else > +extern int __build_bug_on_failed; > +#define BUILD_BUG_ON(condition) \ > +

Re: [powerpc] Next tree Nov 2 : kernel BUG at mm/mmap.c:2135!

2009-11-04 Thread David Gibson
On Wed, Nov 04, 2009 at 06:08:44PM +0530, Sachin Sant wrote: > Sachin Sant wrote: > >Today's next tree failed to boot on a POWER 6 box with : > > > >[ cut here ] > >kernel BUG at mm/mmap.c:2135! > >Oops: Exception in kernel mode, sig: 5 [#2] > >SMP NR_CPUS=1024 NUMA pSeries

[PATCH] powerpc/mm: Remove debug context clamping from nohash code

2009-11-04 Thread Benjamin Herrenschmidt
I inadvertently left that debug code enabled, causing the number of contexts to be clamped to 31 which is going to slow things down on 4xx and just plain breaks 8xx Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/mm/mmu_context_nohash.c |4 ++-- 1 files changed, 2 insertions(+), 2 del

[PATCH RFC] gianfar: Make polling safe with IRQs disabled

2009-11-04 Thread Anton Vorontsov
When using KGDBoE, gianfar driver spits 'Interrupt problem' messages, which appears to be a legitimate warning, i.e. we may end up calling netif_receive_skb() or vlan_hwaccel_receive_skb() with IRQs disabled. This patch reworks the RX path so that if netpoll is enabled (the only case when the driv

[PATCH 3/3] gianfar: Fix compiler and sparse warnings

2009-11-04 Thread Anton Vorontsov
commit fba4ed030cfae7efdb6b79a57b0c5a9d72c9de83 ("gianfar: Add Multiple Queue Support") introduced the following warnings: CHECK gianfar.c gianfar.c:333:8: warning: incorrect type in assignment (different address spaces) gianfar.c:333:8:expected unsigned int [usertype] *baddr gianfar.c:33

[PATCH 2/3] fsl_pq_mdio: Fix compiler/sparse warnings (part 2)

2009-11-04 Thread Anton Vorontsov
This patch fixes following warnings: fsl_pq_mdio.c:112:38: warning: cast adds address space to expression () fsl_pq_mdio.c:124:38: warning: cast adds address space to expression () fsl_pq_mdio.c:133:38: warning: cast adds address space to expression () fsl_pq_mdio.c:414:11: warning: cast adds addr

[PATCH 1/3] fsl_pq_mdio: Fix compiler/sparse warnings (part 1)

2009-11-04 Thread Anton Vorontsov
commit 1d2397d742b7a2b39b2f09dd9da3b9d1463f55e9 ("fsl_pq_mdio: Add Suport for etsec2.0 devices") introduced the following warnings: CHECK fsl_pq_mdio.c fsl_pq_mdio.c:287:22: warning: incorrect type in initializer (different base types) fsl_pq_mdio.c:287:22:expected unknown type 11 const *

[RFC PATCH 5/5] powerpc/iseries updates for new OF dynamic code

2009-11-04 Thread Nathan Fontenot
Update the powerpc/iseries vio code to use the new generic OF dynamic code. NOTE: I have no means of testing iseries kernels, this does at least pass the compile test for me. Signed-off-by: Nathan Fontenot --- Index: linux-next/arch/powerpc/platforms/iseries/vio.c =

[RFC PATCH 4/5] Microblaze updates for OF dynamic code

2009-11-04 Thread Nathan Fontenot
This patch removes the common OF dynamic device tree updating from the microblaze prom.c file to now use the generic OF code. NOTE: I have no means of building and testing for the microblaze architecture. I'll sign off on this with the understanding that it has not even passed the compile test y

[RFC PATCH 3/5] powerpc and pseries updates for new OF dynamic code

2009-11-04 Thread Nathan Fontenot
Updates to powerpc generic and powerpc/pseries. This patch removes the dynamic device tree updating code from prom.c and deletes the no longer neccessary pSeries_reconfig.h file, all of the functionality is now in the generic OF code. The remaining changes deal with updating code for name chang

[RFC PATCH 2/5] Merge dynamic OF code to of_dynamic.c

2009-11-04 Thread Nathan Fontenot
Creation of the OF dynamic device tree update code in drivers/of. This merges the common device tree updating routines to add/remove nodes and properties from powerpc and microblaze. All of the new code is conditional based on a new OF_DYNAMIC config option. There are two updates to the code.

[RFC PATCH 1/5] Move devtree_lock and allnodes declaration to of.h

2009-11-04 Thread Nathan Fontenot
Move the declaration of devtree_lock and allnodes from powerpc/microblaze asm/prom.h to linux/of.h Signed-off-by: Nathan Fontenot --- Index: linux-next/include/linux/of.h === --- linux-next.orig/include/linux/of.h 2009-11-02 13:39:

[RFC PATCH 0/5] Merge common dynamic OF device tree code

2009-11-04 Thread Nathan Fontenot
This is a follow on to Grant Likely's patches, attempting to merge the common pieces of dynamic OF device tree updating. These patches move the common code for adding and removing nodes and properties from the device tree to drivers/of/of_dynamic.c and wraps them under the new OF_DYNAMIC config o

Re: Regarding FPGA based cascaded PIC

2009-11-04 Thread Benjamin Herrenschmidt
On Wed, 2009-11-04 at 18:09 +0530, Thirumalai wrote: > you understood correctly. Here the problem lies.Correct me if i am wrong. So > you are telling that irq_of_parse_and_map() will invoke the map/xlate of my > FPGA pic. Right. > > But this is what not happening. Instead of calling my map/xlate

RE: DMA to User-Space

2009-11-04 Thread john . p . price
Jonathan, what kind of memory is fpga_drv.strmdata? memory from the kernel stack, something you allocated? You'll notice you were trying to access location 0. To use dma streaming memory you must call dma_map_single() to get the physical address of fpga_drv.strmdata. That memory must be contigu

Please pull 'next' branch of 4xx tree

2009-11-04 Thread Josh Boyer
Hi Ben, Please pull the next branch of the 4xx tree to get the following commits. I have some other things in the middle of being worked that may or may not make it in time for the next release, so I wanted to get these commits into your tree now rather than wait. josh The following changes sin

Re: Fwd: [PATCH] arch/powerpc: Improve _memcpy

2009-11-04 Thread Albrecht Dreß
See . Any chance to get this one into the tree? Grant? Cheers, Albrecht. Am 03.11.09 20:30 schrieb(en) Chris Friesen: Forwarding to the ppc mailing list. Chris Original Message Subject: [PATCH] arch/p

RE: DMA to User-Space

2009-11-04 Thread Jonathan Haws
> 1. I open /dev/mem and get a file descriptor > 2. I use mmap to reserve some physical addresses for my buffers in > user space. > 3. I give that address to the FPGA for DMA use. > 4. When I get the FPGA interrupt, I invalidate the data cache and > write the data to disk > > Does that sound like

RE: DMA to User-Space

2009-11-04 Thread Jonathan Haws
> Jonathan Haws wrote: > > All, > > > > I have what may be an unconventional question: > > > > Our application consists of data being captured by an FPGA, > processed, and transferred to SDRAM. I simply give the FPGA an > address of where I want it stored in SDRAM and it simply DMAs the > data ove

[PATCH] PCI: Fix regression in powerpc MSI-X

2009-11-04 Thread Andre Detsch
Patch f598282f5145036312d90875d0ed5c14b49fd8a7 exposed a problem in powerpc MSI-X functionality, making network interfaces such as ixgbe and cxgb3 stop to work when MSI-X is enabled. RX interrupts were not being generated. The problem was caused because MSI irq was not being effectively unmasked a

[PATCH 8/8] 8xx: Remove DIRTY pte handling in DTLB Error.

2009-11-04 Thread Joakim Tjernlund
There is no need to do set the DIRTY bit directly in DTLB Error. Trap to do_page_fault() and let the generic MM code do the work. Signed-off-by: Joakim Tjernlund --- arch/powerpc/kernel/head_8xx.S | 96 1 files changed, 0 insertions(+), 96 deletions(-)

[PATCH 7/8] 8xx: start using dcbX instructions in various copy routines

2009-11-04 Thread Joakim Tjernlund
Now that 8xx can fixup dcbX instructions, start using them where possible like every other PowerPc arch do. Signed-off-by: Joakim Tjernlund --- arch/powerpc/kernel/misc_32.S | 18 -- arch/powerpc/lib/copy_32.S| 24 2 files changed, 0 insertions(+)

[PATCH 3/8] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.

2009-11-04 Thread Joakim Tjernlund
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. Test for DAR=0x00f0 in DataTLBError and bail to handle_page_fault(). Signed-off-by: Joakim Tjernlund --- arch/powerpc/kernel/head_8xx.S

[PATCH 6/8] 8xx: Restore _PAGE_WRITETHRU

2009-11-04 Thread Joakim Tjernlund
8xx has not had WRITETHRU due to lack of bits in the pte. After the recent rewrite of the 8xx TLB code, there are two bits left. Use one of them to WRITETHRU. Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE? Signed-off-by: Joakim Tjernlund --- arch/powerpc/include/asm/pte-8xx.h |5

[PATCH 4/8] 8xx: Fixup DAR from buggy dcbX instructions.

2009-11-04 Thread Joakim Tjernlund
This is an assembler version to fixup DAR not being set by dcbX, icbi instructions. There are two versions, one uses selfmodifing code, the other uses a jump table but is much bigger(default). Signed-off-by: Joakim Tjernlund --- arch/powerpc/kernel/head_8xx.S | 147 +

[PATCH 2/8] 8xx: Update TLB asm so it behaves as linux mm expects.

2009-11-04 Thread Joakim Tjernlund
Update the TLB asm to make proper use of _PAGE_DIRY and _PAGE_ACCESSED. Get rid of _PAGE_HWWRITE too. Pros: - I/D TLB Miss never needs to write to the linux pte. - _PAGE_ACCESSED is only set on TLB Error fixing accounting - _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly

[PATCH 1/8] 8xx: invalidate non present TLBs

2009-11-04 Thread Joakim Tjernlund
8xx sometimes need to load a invalid/non-present TLBs in it DTLB asm handler. These must be invalidated separaly as linux mm don't. Signed-off-by: Joakim Tjernlund --- arch/powerpc/mm/fault.c |8 +++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/mm/fault.c

[PATCH 0/8] 8xx: Misc fixes for buggy insn

2009-11-04 Thread Joakim Tjernlund
Here is the latest(last?) round of this series. I hope I got everything right now. Scott and Rex, please test and send ACK/NACK. Jocke Joakim Tjernlund (8): 8xx: invalidate non present TLBs 8xx: Update TLB asm so it behaves as linux mm expects. 8xx: Tag DAR with 0x00f0 to catch buggy inst

[PATCH 5/8] 8xx: Add missing Guarded setting in DTLB Error.

2009-11-04 Thread Joakim Tjernlund
only DTLB Miss did set this bit, DTLB Error needs too otherwise the setting is lost when the page becomes dirty. Signed-off-by: Joakim Tjernlund --- arch/powerpc/kernel/head_8xx.S | 13 ++--- 1 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S

Re: Regarding FPGA based cascaded PIC

2009-11-04 Thread Thirumalai
- Original Message - From: "Benjamin Herrenschmidt" To: "Thirumalai" Cc: Sent: Wednesday, November 04, 2009 11:55 AM Subject: Re: Regarding FPGA based cascaded PIC On Wed, 2009-11-04 at 10:48 +0530, Thirumalai wrote: Hi Ben, I am a having MPC8640D based board on which i a

Re: [powerpc] Next tree Nov 2 : kernel BUG at mm/mmap.c:2135!

2009-11-04 Thread Sachin Sant
Sachin Sant wrote: Today's next tree failed to boot on a POWER 6 box with : [ cut here ] kernel BUG at mm/mmap.c:2135! Oops: Exception in kernel mode, sig: 5 [#2] SMP NR_CPUS=1024 NUMA pSeries Problem exists with today's next as well. Likely cause for this problem seems

Re: [PATCH 14/27] Add book3s_64 specific opcode emulation

2009-11-04 Thread Alexander Graf
On 04.11.2009, at 09:47, Benjamin Herrenschmidt wrote: On Wed, 2009-11-04 at 09:43 +0100, Arnd Bergmann wrote: On Tuesday 03 November 2009, Benjamin Herrenschmidt wrote: (Though glibc can be nasty, afaik it might load up optimized variants of some routines with hard wired cache line sizes b

[PATCH] spi/mpc52xx: replace printk with dev_err

2009-11-04 Thread Wolfram Sang
To easily identify which device has problems. Signed-off-by: Wolfram Sang Cc: Grant Likely --- drivers/spi/mpc52xx_psc_spi.c |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c index e268437..6fb6b3b 100644 -

Re: [PATCH 14/27] Add book3s_64 specific opcode emulation

2009-11-04 Thread Benjamin Herrenschmidt
On Wed, 2009-11-04 at 09:43 +0100, Arnd Bergmann wrote: > On Tuesday 03 November 2009, Benjamin Herrenschmidt wrote: > > (Though glibc can be nasty, afaik it might load up optimized > variants of > > some routines with hard wired cache line sizes based on the CPU > type) > > You can also get appli

Re: [PATCH 14/27] Add book3s_64 specific opcode emulation

2009-11-04 Thread Arnd Bergmann
On Tuesday 03 November 2009, Benjamin Herrenschmidt wrote: > (Though glibc can be nasty, afaik it might load up optimized variants of > some routines with hard wired cache line sizes based on the CPU type) You can also get application with hand-coded cache optimizations that are even harder, if no