From: Harninder Rai harninder@freescale.com
It adds cache-sram support in P1/P2 QorIQ platforms as under:
* A small abstraction over powerpc's remote heap allocator
* Exports mpc85xx_cache_sram_alloc()/free() APIs
* Supports only one contiguous SRAM window
* Drivers
Also modifiy the document of cell-index in SPI controller. Add the
SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
Documentation/powerpc/dts-bindings/fsl/spi.txt | 24
Add eSPI controller support based on the library code spi_fsl_lib.c.
The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:
1. Has different register map and different bit definition
So leave the code operated the
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.
Because the register map of the SPI controller and eSPI controller
is so different, also leave the
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Acked-by: Grant Likely grant.lik...@secretlab.ca
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
- Made changes according to Grant's comments.
drivers/mtd/devices/m25p80.c |5 +
1 files changed, 5 insertions(+), 0
This patchset refactor the file spi_mpc8xxx.c to abstract some common
code as a lib used by the SPI/eSPI controller driver, move the SPI
controller driver code to spi_fsl_spi.c, and add the eSPI controller
support with spi_fsl_espi.c.
v4 main change:
- Update to the latest kernel base(Linux
On Oct 12, 2010, at 5:25 AM, harninder@freescale.com
harninder@freescale.com wrote:
+static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev,
+ const struct of_device_id *match)
+{
+ long rval;
+ unsigned int rem;
+
Thomas Gleixner t...@linutronix.de writes:
On Mon, 11 Oct 2010, Tim Pepper wrote:
I'm not necessarily wanting to open up the age old question of what is
a good HZ, but we were doing some testing on timer tick overheads for
HPC applications and this came up...
Yeah. This comes always up
The new e5500 core is similar to the e500mc core but adds 64-bit
support. We support running it in 32-bit mode as it is identical to the
e500mc.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Updated to remove CONFIG_PPC_E5500 and use E500MC
arch/powerpc/include/asm/reg_booke.h
The P5020DS is in the same family of boards as the P4080 DS and thus
shares the corenet_ds code.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Updated based on removal of CONFIG_PPC_E5500
arch/powerpc/platforms/85xx/Kconfig| 12 ++
arch/powerpc/platforms/85xx/Makefile |
On Tue, 12 Oct 2010, Andi Kleen wrote:
Thomas Gleixner t...@linutronix.de writes:
We have told HPC folks for years that we need a kind of NOHZ mode
for HPC where we can transparently switch off the tick when only one
user space bound thread is active and switch back to normal once this
Currently the design is that we divide the sram portion into 2 equal
parts for AMP
That was the part of initial requirement
Do we want to remove that?
Thanks and Regards
Harry++
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, October 12, 2010
On Tue, Oct 12, 2010 at 10:02 AM, Rai Harninder-B01044
b01...@freescale.com wrote:
Currently the design is that we divide the sram portion into 2 equal
parts for AMP
That was the part of initial requirement
Do we want to remove that?
Why wouldn't you just pass different cache-sram-size/offset
On Tue, 12 Oct 2010 10:50:52 -0500
Kumar Gala ga...@kernel.crashing.org wrote:
The new e5500 core is similar to the e500mc core but adds 64-bit
support. We support running it in 32-bit mode as it is identical to the
e500mc.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
*
Josh,
Please pull this patch. I just found a bone-headed mistake that makes
the whole patch a no-op. I'll need to fix it and put it through a bit
of testing before I can re-submit it.
The other patch in this series should be okay.
Thanks,
Shaggy
On Mon, 2010-09-27 at 16:56 -0500, Dave
On Oct 12, 2010, at 12:33 PM, Scott Wood wrote:
On Tue, 12 Oct 2010 10:50:52 -0500
Kumar Gala ga...@kernel.crashing.org wrote:
The new e5500 core is similar to the e500mc core but adds 64-bit
support. We support running it in 32-bit mode as it is identical to the
e500mc.
On Tue, 12 Oct 2010 14:55:42 -0500
Kumar Gala ga...@kernel.crashing.org wrote:
On Oct 12, 2010, at 12:33 PM, Scott Wood wrote:
On Tue, 12 Oct 2010 10:50:52 -0500
Kumar Gala ga...@kernel.crashing.org wrote:
The new e5500 core is similar to the e500mc core but adds 64-bit
support.
There's mpic stuff in the call trace, so the NULL host was OK.
Look in arch/powerpc/platforms/86xx/pic.c. What is the second-to-last
parameter of mpc86xx_init_irq() in your kernel tree? It's 256 in
current upstream -- this is the number of IRQ sources the MPIC driver
will handle.
One,
On Tue, 12 Oct 2010 15:55:28 -0500
david.hag...@gmail.com wrote:
I wonder about the next lines:
mpic_assign_isu(mpic1, 0, res.start + 0x1);
/* 48 Internal Interrupts */
mpic_assign_isu(mpic1, 1, res.start + 0x10200);
mpic_assign_isu(mpic1, 2, res.start +
On Tue, Oct 12, 2010 at 02:40:13PM -0500, Dave Kleikamp wrote:
Josh,
Please pull this patch. I just found a bone-headed mistake that makes
the whole patch a no-op. I'll need to fix it and put it through a bit
of testing before I can re-submit it.
OK. I should have looked more closely myself.
In message 1286855108.14049.8.ca...@flin.austin.ibm.com you wrote:
icswx is a PowerPC co-processor instruction to send data to a
co-processor. On Book-S processors the LPAR_ID and process ID (PID) of
the owning process are registered in the window context of the
co-processor at initial time.
On Mon, 2010-10-11 at 09:44 -0500, david.hag...@gmail.com wrote:
You should define MSI device nodes on your target dts. And you can refer
to the
file, mpc8572ds.dts.
I see nothing in that file that defines any MSIs. I see code that looks
like it maps ROOT COMPLEX MODE interrupts on
Scott Wood wrote:
On Tue, 12 Oct 2010 15:55:28 -0500
david.hag...@gmail.com wrote:
I wonder about the next lines:
mpic_assign_isu(mpic1, 0, res.start + 0x1);
/* 48 Internal Interrupts */
mpic_assign_isu(mpic1, 1, res.start + 0x10200);
mpic_assign_isu(mpic1, 2,
On Tue, 2010-10-05 at 10:18 -0700, Anirban Chakraborty wrote:
Hi All,
I am trying to test qlcnic driver (for 10Gb QLogic network adapter) on a
Power 6 system
(IBM P 520, System type 8203) with upstream kernel and I do see that the
kernel is
not able to allocate any MSI-X vectors. The
WANG YiFei wrote:
Hi,
I'm a newbie for linux device driver development.
We have a custom ppc405 board which has MCP23S17
(16-Bit I/O Expander with SPI Interface) on it.
I noticed that current kernel has MCP23S08 driver
support, I'd like to know:
1. if passing platform data
I noticed a compilation warning of RTC for powerpc. Found the fix existing
for MIPS not for available for PowerPC.
Can you please add the waring text here.
[1. text/x-patch; 0001-RTC-rtc-cmos.c-Fix-warning-on-PowerPC.patch]...
Please inline the patch rather than using an attachment.
Mikey
On Tue, Oct 12, 2010 at 06:18:31PM +0800, Mingkai Hu wrote:
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.
Because the register map of the
On Tue, Oct 12, 2010 at 06:18:32PM +0800, Mingkai Hu wrote:
Add eSPI controller support based on the library code spi_fsl_lib.c.
The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:
1. Has different register map and
On Tue, Oct 12, 2010 at 06:18:33PM +0800, Mingkai Hu wrote:
Also modifiy the document of cell-index in SPI controller. Add the
SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Applied, thanks.
g.
---
v4:
- Updated to
On Tue, Oct 12, 2010 at 06:18:34PM +0800, Mingkai Hu wrote:
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Acked-by: Grant Likely grant.lik...@secretlab.ca
dwmw2: what are your thoughts on this one?
g.
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
- Made changes
On Wed, 2010-09-15 at 12:33 -0600, Grant Likely wrote:
On Wed, Sep 15, 2010 at 12:05 PM, Nishanth Aravamudan n...@us.ibm.com wrote:
Use the set_dma_ops helper. Instead of modifying vio_dma_mapping_ops,
just create a trivial wrapper for dma_supported.
Signed-off-by: Milton Miller
On Fri, 2010-10-08 at 11:04 -0500, Kumar Gala wrote:
Ben,
This isn't critical, but it does fix having the ppc64e_defconfig
build cleanly.
Doesn't matter, I'm putting it in -next. When is your -next branch btw ?
It's overdue by 3 or 4 rc's already :-)
Cheers,
Ben.
- k
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