On Tuesday 07 June 2011 01:04:40 Chris Metcalf wrote:
For context, the most recent patch for the tile driver in question is here:
https://patchwork.kernel.org/patch/843892/
On 6/6/2011 5:23 PM, Konrad Rzeszutek Wilk wrote:
On Mon, Jun 06, 2011 at 05:01:36PM -0400, Chris Metcalf wrote:
[forgot to CC the list]
-- Forwarded message --
Date: Mon, 6 Jun 2011 16:17:08 -0500 (CDT)
From: Kumar Gala ga...@kernel.crashing.org
To: Benjamin Herrenschmidt b...@kernel.crashing.org
Subject: [git pull] Please pull powerpc.git merge branch
The following changes since commit
Dear All,
I have mpc8313 powerpc based board with silicon revision 2.1. the
processor has two ETH ports (eTsec1 and eTsec2) i.e. eth0 and eth1.
eth0 is 1Gbps port and eth1 is 100Mbps port. On board there is L2
switch from TANTOS2G (psb6972) supports one port 1Gbps,
and from switch there are 4
On Jun 5, 2011, at 9:48 PM, Michael Neuling wrote:
doorbell type is defined as bits 32:36 so should be shifted by 63-36 =
27 rather than 28.
We never noticed this bug as we've only every used type PPC_DBELL = 0.
Signed-off-by: Michael Neuling mi...@neuling.org
---
This patch series ports the cpuidle framework for ppc64 platform and
implements a cpuidle back-end driver for ppc64 (pSeries) platform.
Currently idle states are managed by pseries_{dedicated,shared}_idle_sleep()
routines in arch/powerpc/platforms/pseries/setup.c. There are
generally two idle
From: Len Brown len.br...@intel.com
useful for disabling cpuidle to fall back
to architecture-default idle loop
cpuidle drivers and governors will fail to register.
on x86 they'll say so:
intel_idle: intel_idle yielding to (null)
ACPI: acpi_idle yielding to (null)
Signed-off-by: Len Brown
From: Len Brown len.br...@intel.com
When a Xen Dom0 kernel boots on a hypervisor, it gets access
to the raw-hardware ACPI tables. While it parses the idle tables
for the hypervisor's beneift, it uses HLT for its own idle.
Rather than have xen scribble on pm_idle and access default_idle,
have it
From: Len Brown len.br...@intel.com
pm_idle does not scale as an idle handler registration mechanism.
Don't use it for cpuidle. Instead, call cpuidle directly, and
allow architectures to use pm_idle as an arch-specific default
if they need it. ie.
cpu_idle()
...
This patch provides cpu_idle_wait() routine required
by the cpuidle subsystem. Almost all the code is borrowed
from x86.
Signed-off-by: Trinabh Gupta trin...@linux.vnet.ibm.com
Signed-off-by: Arun R Bharadwaj a...@linux.vnet.ibm.com
---
arch/powerpc/Kconfig |4
This patch implements a cpuidle driver for pSeries based on
routines pseries_dedicated_idle_loop and pseries_shared_idle_loop.
The driver is built only if CONFIG_CPU_IDLE is set. This
cpuidle driver uses global registration of idle states and
not per-cpu.
Signed-off-by: Trinabh Gupta
This patch enables cpuidle for pSeries and cpuidle_idle_call() is
directly called from the idle loop. As a result pseries_idle cpuidle
driver registered with cpuidle subsystem comes into action. This patch
also removes the routines pseries_shared_idle_sleep and
pseries_dedicated_idle_sleep as they
This patch makes pseries_idle_driver to be not registered when
power_save=off kernel boot option is specified. For this
boot_option_idle_override is used similar to how it is used for x86.
Signed-off-by: Trinabh Gupta trin...@linux.vnet.ibm.com
Signed-off-by: Arun R Bharadwaj
On 6/7/2011 3:08 AM, Arnd Bergmann wrote:
On Tuesday 07 June 2011 01:04:40 Chris Metcalf wrote:
There is certainly precedent for drivers that don't fit cleanly into an
existing category to go in drivers/arch, e.g. drivers/s390,
drivers/parisc, etc. There is also drivers/platform/x86, though
On 06/03, Eric Paris wrote:
The audit system previously expected arches calling to audit_syscall_exit to
supply as arguments if the syscall was a success and what the return code was.
Audit also provides a helper AUDITSC_RESULT which was supposed to simplify
things
by converting from
Create an entry for the BG/P chips, include bits to accomodate
the double fp2 fpu and the special MMU considerations like L1
writethrough.
RFC Note: this patch fails scripts/checkpatch.pl because I
matched coding style of the surrounding existing code. Would
you rather have something
On Tue, 2011-06-07 at 19:19 +0200, Oleg Nesterov wrote:
On 06/03, Eric Paris wrote:
The audit system previously expected arches calling to audit_syscall_exit to
supply as arguments if the syscall was a success and what the return code
was.
Audit also provides a helper AUDITSC_RESULT
Arnd Bergmann wrote:
For the spi flash driver that goes through the hypervisor abstraction,
I think drivers/virt/tile would be better than driver/platform/tile,
but we should really have a new abstract flash character driver subsystem
for that.
Why should it matter that the SPI flash driver
On Tuesday 07 June 2011 18:49:02 Chris Metcalf wrote:
You can probably argue that the tile drivers do fit in here as long as
they are specific to the hypervisor and not to some SOC specific hardware.
Can you clarify that? I think you're contrasting something like an ARM
core that was
On Tue, 7 Jun 2011 18:32:37 +0530
Vijay Nikam vijay.t.ni...@gmail.com wrote:
Dear All,
I have mpc8313 powerpc based board with silicon revision 2.1. the
processor has two ETH ports (eTsec1 and eTsec2) i.e. eth0 and eth1.
eth0 is 1Gbps port and eth1 is 100Mbps port. On board there is L2
On Tuesday 07 June 2011 21:20:50 Timur Tabi wrote:
Arnd Bergmann wrote:
For the spi flash driver that goes through the hypervisor abstraction,
I think drivers/virt/tile would be better than driver/platform/tile,
but we should really have a new abstract flash character driver subsystem
for
BG/P nodes need to be configured for writethrough to work in SMP
configurations. This patch adds the right hooks in the MMU code
to make sure BGP_L1_WRITETHROUGH configurations are setup for BG/P.
RFC note: this essentially just changes the ifdefs to use the
BEGIN_MMU_FTR_SECTION macros. A
On Tue, 2011-06-07 at 16:36 -0500, Eric Van Hensbergen wrote:
BG/P nodes need to be configured for writethrough to work in SMP
configurations. This patch adds the right hooks in the MMU code
to make sure BGP_L1_WRITETHROUGH configurations are setup for BG/P.
Ok so getting better, some
On Tue, 2011-06-07 at 13:47 -0500, Eric Van Hensbergen wrote:
Create an entry for the BG/P chips, include bits to accomodate
the double fp2 fpu and the special MMU considerations like L1
writethrough.
RFC Note: this patch fails scripts/checkpatch.pl because I
matched coding style of the
+#define PPC_FEATURE_HAS_FPU_FP2 0x0040
Any chance for a better name ?
That's the official external name, it sucks. I'm happy to
PPC_FEATURE_DOUBLE_HUMMER if you'd prefer, otherwise I'm not feeling
too creative, but am open to artistic suggestions.
-eric
ten-bit interface (TBI) module is part of SoC not board.
Move tbi entries from board related dts files to Si dts.
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon http://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
(branch next)
On Fri, Jun 03, 2011 at 02:51:38PM -0600, Grant Likely wrote:
On Tue, May 31, 2011 at 10:07:01PM -0700, Josh Triplett wrote:
We have a TQM5200 board, which has GPIO lines hooked up to an SM501.
I've managed to come up with the following patch to the tqm5200 device
tree, which manages to
Create an entry for the BG/P chips, include bits to accomodate
the double fp2 fpu and the special MMU considerations like L1
writethrough.
RFC Note: this patch fails scripts/checkpatch.pl because I
matched coding style of the surrounding existing code. Would
you rather have
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