On Tue, 2011-06-28 at 09:50 +0800, b35...@freescale.com wrote:
From: Liu Shuo b35...@freescale.com
The global data fsl_lbc_ctrl_dev-nand don't have to be freed in
fsl_elbc_chip_remove(). The right place to do that is in
fsl_elbc_nand_remove()
if elbc_fcm_ctrl-counter is zero.
On Tue, 2011-06-28 at 09:50 +0800, b35...@freescale.com wrote:
+ /* Hack for supporting the flash chip whose writesize is
+ * larger than 2K bytes.
+ */
Please, use proper kernel multi-line comments. Please, make sure
checkpatch.pl does not generate 13 errors with this patch.
--
On Mon, Jun 27, 2011 at 6:01 PM, Ananth N Mavinakayanahalli
ana...@in.ibm.com wrote:
On Sun, Jun 26, 2011 at 11:47:13PM +0900, Masami Hiramatsu wrote:
(2011/06/24 19:29), Steven Rostedt wrote:
On Fri, 2011-06-24 at 17:21 +0800, Yong Zhang wrote:
Hi,
When I use kprobe to do something, I
On Tue, Jun 28, 2011 at 6:41 PM, Ananth N Mavinakayanahalli
ana...@in.ibm.com wrote:
My access to a 32bit powerpc box is very limited. Also, embedded powerpc
has had issues with gcc-4.6 while gcc-4.5 worked fine.
I think I can do some test if you have any ideas :)
I'm not sure if x86 had
On Wed, 2011-06-22 at 16:25 -0500, Scott Wood wrote:
On MMUs such as FSL where we can guarantee the entire linear mapping is
bolted, we don't need to worry about linear TLB misses. If on top of
that we do a full table walk, we get rid of all recursive TLB faults, and
can dispense with some
Hi Linus !
Here are a handful of minor powerpc bits for 3.0
Note: At the time of this sending, the mirrors still hadn't caught up.
Cheers,
Ben.
The following changes since commit b0af8dfdd67699e25083478c63eedef2e72ebd85:
Linux 3.0-rc5 (2011-06-27 19:12:22 -0700)
are available in the git
On Fri, 24 Jun 2011 12:05:23 -0700
Nishanth Aravamudan n...@us.ibm.com wrote:
From: Milton Miller milt...@bga.com
If an architecture sets ARCH_HAS_DMA_GET_REQUIRED_MASK and has settable
dma_map_ops, the required mask may change by the ops implementation.
For example, a system that always
On 6/29/11, Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
Before I comment on this last one, a quick Q. for Dave: Do you want to
handle this or should I merge it via powerpc.git ? (It depends on
another change to the arch code to expose the SCOM functions that it
uses, and that patch
On Wed, 2011-06-29 at 12:40 +0400, Dmitry Eremin-Solenikov wrote:
On 6/29/11, Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
Before I comment on this last one, a quick Q. for Dave: Do you want to
handle this or should I merge it via powerpc.git ? (It depends on
another change to the
This adds support for running KVM guests in supervisor mode on those
PPC970 processors that have a usable hypervisor mode. Unfortunately,
Apple G5 machines have supervisor mode disabled (MSR[HV] is forced to
1), but the YDL PowerStation does have a usable hypervisor mode.
There are several
This adds the infrastructure for handling PAPR hcalls in the kernel,
either early in the guest exit path while we are still in real mode,
or later once the MMU has been turned back on and we are in the full
kernel context. The advantage of handling hcalls in real mode if
possible is that we avoid
Instead of branching out-of-line with the DO_KVM macro to check if we
are in a KVM guest at the time of an interrupt, this moves the KVM
check inline in the first-level interrupt handlers. This speeds up
the non-KVM case and makes sure that none of the interrupt handlers
are missing the check.
This arranges for the top-level arch/powerpc/kvm/powerpc.c file to
pass down some of the calls it gets to the lower-level subarchitecture
specific code. The lower-level implementations (in booke.c and book3s.c)
are no-ops. The coming book3s_hv.c will need this.
Signed-off-by: Paul Mackerras
Instead of doing the kvm_guest_enter/exit() and local_irq_dis/enable()
calls in powerpc.c, this moves them down into the subarch-specific
book3s_pr.c and booke.c. This eliminates an extra local_irq_enable()
call in book3s_pr.c, and will be needed for when we do SMT4 guest
support in the book3s
This lifts the restriction that book3s_hv guests can only run one
hardware thread per core, and allows them to use up to 4 threads
per core on POWER7. The host still has to run single-threaded.
This capability is advertised to qemu through a new KVM_CAP_PPC_SMT
capability. The return value of
This moves the slb field, which represents the state of the emulated
SLB, from the kvmppc_vcpu_book3s struct to the kvm_vcpu_arch, and the
hpte_hash_[v]pte[_long] fields from kvm_vcpu_arch to kvmppc_vcpu_book3s.
This is in accord with the principle that the kvm_vcpu_arch struct
represents the
Doing so means that we don't have to save the flags anywhere and gets
rid of the last reference to to_book3s(vcpu) in arch/powerpc/kvm/book3s.c.
Doing so is OK because a program interrupt won't be generated at the
same time as any other synchronous interrupt. If a program interrupt
and an
From: David Gibson d...@au1.ibm.com
This improves I/O performance for guests using the PAPR
paravirtualization interface by making the H_PUT_TCE hcall faster, by
implementing it in real mode. H_PUT_TCE is used for updating virtual
IOMMU tables, and is used both for virtual I/O and for real I/O
This adds infrastructure which will be needed to allow book3s_hv KVM to
run on older POWER processors, including PPC970, which don't support
the Virtual Real Mode Area (VRMA) facility, but only the Real Mode
Offset (RMO) facility. These processors require a physically
contiguous, aligned area of
The first patch of the following series is a pure bug-fix for 32-bit
kernels.
The remainder of the following series of patches enable KVM to exploit
the hardware hypervisor mode on 64-bit Power ISA Book3S machines. At
present, POWER7 and PPC970 processors are supported. (Note that the
PPC970
In hypervisor mode, the LPCR controls several aspects of guest
partitions, including virtual partition memory mode, and also controls
whether the hypervisor decrementer interrupts are enabled. This sets
up LPCR at boot time so that guest partitions will use a virtual real
memory area (VRMA)
There are several fields in struct kvmppc_book3s_shadow_vcpu that
temporarily store bits of host state while a guest is running,
rather than anything relating to the particular guest or vcpu.
This splits them out into a new kvmppc_host_state structure and
modifies the definitions in asm-offsets.c
Commit 69acc0d3ba (KVM: PPC: Resolve real-mode handlers through
function exports) resulted in vcpu-arch.trampoline_lowmem and
vcpu-arch.trampoline_enter ending up with kernel virtual addresses
rather than physical addresses. This is OK on 64-bit Book3S machines,
which ignore the top 4 bits of the
This new ioctl allows userspace to specify what paravirtualization
interface (if any) KVM should implement, what architecture version
the guest virtual processors should conform to, and whether the guest
can be permitted to use a real supervisor mode.
At present the only effect of the ioctl is to
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for
On Wed, Jun 29, 2011 at 08:41:03PM +1000, Paul Mackerras wrote:
Documentation/virtual/kvm/api.txt | 35 +++
arch/powerpc/include/asm/kvm.h | 15 +++
arch/powerpc/include/asm/kvm_host.h |1 +
arch/powerpc/kvm/powerpc.c | 28
On 29.06.2011, at 13:53, Josh Boyer wrote:
On Wed, Jun 29, 2011 at 08:41:03PM +1000, Paul Mackerras wrote:
Documentation/virtual/kvm/api.txt | 35
+++
arch/powerpc/include/asm/kvm.h | 15 +++
arch/powerpc/include/asm/kvm_host.h |1 +
On Wed, Jun 29, 2011 at 01:56:16PM +0200, Alexander Graf wrote:
On 29.06.2011, at 13:53, Josh Boyer wrote:
On Wed, Jun 29, 2011 at 08:41:03PM +1000, Paul Mackerras wrote:
Documentation/virtual/kvm/api.txt | 35
+++
arch/powerpc/include/asm/kvm.h |
There is no need to check for the address being a multicast address in
the netdev_for_each_mc_addr loop, so remove it.
Signed-off-by: Tobias Klauser tklau...@distanz.ch
---
drivers/net/ucc_geth.c |5 -
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ucc_geth.c
CPC925/CPC945 use special window to access host bridge functionality of
u3-ht. Provide a way to access this device.
Signed-off-by: Dmitry Eremin-Solenikov dbarysh...@gmail.com
---
arch/powerpc/platforms/maple/pci.c | 55
1 files changed, 55 insertions(+), 0
This fixes the following warning:
WARNING: arch/powerpc/kernel/built-in.o(.text+0x29768): Section mismatch in
reference from the function .register_power_pmu() to the function
.cpuinit.text:.power_pmu_notifier()
The function .register_power_pmu() references
the function __cpuinit
Please merge this patchset, adding a cpufreq driver for Momentum Maple
platform. Changes since V3:
* Add comment regarding power-mode-data
* Adjusted kernel output a bit
* Tied the driver to compatible platforms only (as per
arch/powerpc/platforms/maple/setup.c)
Dmitry Eremin-Solenikov (2):
Enable functions used to access SCOM if PPC_MAPLE is defined: they are
used by cpufreq driver to control hardware.
Signed-off-by: Dmitry Eremin-Solenikov dbarysh...@gmail.com
---
arch/powerpc/kernel/misc_64.S |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git
Add simple cpufreq driver for Maple-based boards (ppc970fx evaluation
kit and others). Driver is based on a cpufreq driver for 64-bit powermac
boxes with all pmac-dependant features removed and simple cleanup
applied.
Signed-off-by: Dmitry Eremin-Solenikov dbarysh...@gmail.com
---
On Wed, Jun 29, 2011 at 09:15:28AM +1000, Benjamin Herrenschmidt wrote:
On Tue, 2011-06-28 at 17:31 -0500, Ayman El-Khashab wrote:
+static int ppc4xx_setup_pcieh_hw(struct platform_device *dev,
+struct resource res, struct
ppc4xx_msi *msi)
+{
+
On Wed, 29 Jun 2011 09:22:04 +0300
Artem Bityutskiy dedeki...@gmail.com wrote:
On Tue, 2011-06-28 at 09:50 +0800, b35...@freescale.com wrote:
+ /* Hack for supporting the flash chip whose writesize is
+* larger than 2K bytes.
+*/
Please, use proper kernel multi-line comments.
On Wed, 29 Jun 2011 09:20:25 +0300
Artem Bityutskiy dedeki...@gmail.com wrote:
On Tue, 2011-06-28 at 09:50 +0800, b35...@freescale.com wrote:
From: Liu Shuo b35...@freescale.com
The global data fsl_lbc_ctrl_dev-nand don't have to be freed in
fsl_elbc_chip_remove(). The right place to do
Hi,
On Tue, Jun 28, 2011 at 10:28 PM, Benjamin Herrenschmidt
If we're going to have a Kconfig.powerpc, should we maybe just have a
powerpc subdirectory instead with the driver in it ?
Where would the powerpc subdirectory be? under drivers/cpufreq? Or
somewhere under arch/powerpc where it
On Wed, Jun 29, 2011 at 11:42:03AM +1000, Benjamin Herrenschmidt wrote:
On Mon, 2011-06-27 at 06:31 -0500, Ayman El-Khashab wrote:
On Mon, Jun 27, 2011 at 08:19:56PM +1000, Benjamin Herrenschmidt wrote:
On Sat, 2011-06-25 at 18:52 -0500, Ayman El-Khashab wrote:
I noticed during a recent
Hi,
Try this one more time ...
On Wed, Jun 29, 2011 at 3:54 AM, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
On Wed, 2011-06-29 at 12:40 +0400, Dmitry Eremin-Solenikov wrote:
If you feel like it :-) The powermac one has quite a bit more plumbing
for voltage control etc... but it
On Wed, 29 Jun 2011 11:06:36 +1000
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
I don't think we ever want to fix userspace... how would you fix the
vDSO gettimeofday implementation for example since the vDSO has no
storage ?
Hmm... I guess you could at least make the libc interface
On Tue, 28 Jun 2011 20:03:10 -0700
ashwath narasimhan ashwath.narasim...@oneconvergence.com wrote:
Hello,
I am new to the powerpc architecture and I am trying to use
perf_event_open() system call for power pc architecture (e500mc) using
2.6.32 kernel distribution. Is this system call
On Wed, 29 Jun 2011 17:50:28 +1000
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
On Wed, 2011-06-22 at 16:25 -0500, Scott Wood wrote:
On MMUs such as FSL where we can guarantee the entire linear mapping is
bolted, we don't need to worry about linear TLB misses. If on top of
that
On Wed, Jun 29, 2011 at 10:09 PM, kevin diggs diggskevi...@gmail.com wrote:
Hi,
On Tue, Jun 28, 2011 at 10:28 PM, Benjamin Herrenschmidt
If we're going to have a Kconfig.powerpc, should we maybe just have a
powerpc subdirectory instead with the driver in it ?
Where would the powerpc
On 06/14/2011 12:04 PM, Scott Wood wrote:
On Tue, 14 Jun 2011 14:17:01 -0400
Steve Bestsfb...@us.ibm.com wrote:
On Tue, 2011-06-14 at 12:30 -0500, Nathan Lynch wrote:
Hi Steve,
On Tue, 2011-06-14 at 12:58 -0400, Steve Best wrote:
+/*
+ * devmem_is_allowed() checks to see if /dev/mem access
On Wed, 2011-06-29 at 14:40 -0500, Scott Wood wrote:
What is the weird page table format referred to by the normal miss
handler?
Not sure :-) Probably the fact that we allocate 64K for PTE pages but
only use 32K of them ?
Cheers,
Ben.
___
Yep e500mc supports performance counters in hardware. Found the mapping for
the kernel call in /arch/powerpc/include/asm/systbl.h
On Tue, Jun 28, 2011 at 8:03 PM, ashwath narasimhan
ashwath.narasim...@oneconvergence.com wrote:
Hello,
I am new to the powerpc architecture and I am trying to
On Wed, 2011-06-29 at 14:19 -0500, Scott Wood wrote:
On Wed, 29 Jun 2011 11:06:36 +1000
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
I don't think we ever want to fix userspace... how would you fix the
vDSO gettimeofday implementation for example since the vDSO has no
storage ?
On 06/17/2011 12:33 AM, Benjamin Herrenschmidt wrote:
On Tue, 2011-05-31 at 14:19 -0500, Meador Inge wrote:
Some MPIC implementations contain one or more blocks of message registers
that are used to send messages between cores via IPIs. A simple API has
been added to access (get/put, read,
On Wed, 2011-06-29 at 22:04 -0500, Meador Inge wrote:
I posted a more detailed response a few days back:
http://patchwork.ozlabs.org/patch/98075/. In
that response, I tried to put forth the rationale
for allocating the registers statically due to
the AMP use case. With that in mind, do you
From: Michael Ellerman mich...@ellerman.id.au
This patch adds support for the new jump label feature.
Unlike x86 and sparc we just merrily patch the code with no locks etc,
as far as I know this is safe, but I'm not really sure what the x86/sparc
code is protecting against so maybe it's not.
I
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