-Original Message-
From: linuxppc-dev-bounces+b38951=freescale@lists.ozlabs.org
[mailto:linuxppc-dev-bounces+b38951=freescale@lists.ozlabs.org] On Behalf
Of Kumar Gala
Sent: Friday, October 28, 2011 9:10 PM
To: Jia Hongtao-B38951
Cc: Gala Kumar-B11780;
These patches against kernel 3.0 for SDK 1.1.
The patches include contents from topic branch 15-pciep.
Also we add PCI related patch from topic branch 05-MPC8572DS here.
We update the pci/pcie initialization code.
___
Linuxppc-dev mailing list
In previous version pci/pcie initialization is in platform code which
Initialize PCI bridge base on EP/RC or host/agent settings.
We unified pci/pcie initialization as common APIs named fsl_pci_setup
which can be called by platform code.
Signed-off-by: Jia Hongtao b38...@freescale.com
If we're an agent/end-point or fsl_add_bridge doesn't succeed due to some
resource failure we should not scan the PCI bus. We change fsl_add_bridge()
to return -ENODEV in the case we're an agent/end-point.
Signed-off-by: Jia Hongtao b38...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
I have built a cross compiler for ppc440 in little endian mode and
using it to build the kernel.
Yes i am running Linux in Little-Endian. This is the first user space
process. I wrote the below program and running it as init from
/sbin/init. I have also set the permissions with chmod +s.
From: Liu Shuo b35...@freescale.com
If we use the Nand flash chip whose number of pages in a block is greater
than 64(for large page), we must treat the low bit of FBAR as being the
high bit of the page address due to the limitation of FCM, it simply uses
the low 6-bits (for large page) of the
From: Liu Shuo b35...@freescale.com
Integrated Flash Controller supports various flashes like NOR, NAND
and other devices using NOR, NAND and GPCM Machine available on it.
IFC supports four chip selects.
Signed-off-by: Dipen Dudhat dipen.dud...@freescale.com
Signed-off-by: Scott Wood
From: Liu Shuo b35...@freescale.com
Integrated Flash Controller(IFC) can be used to hook NAND Flash
chips using NAND Flash Machine available on it.
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Liu Shuo b35...@freescale.com
---
On Mon, 2011-10-31 at 20:49 +1100, Michael Neuling wrote:
I have built a cross compiler for ppc440 in little endian mode and
using it to build the kernel.
Yes i am running Linux in Little-Endian. This is the first user space
process. I wrote the below program and running it as init from
On Oct 29, 2011, at 1:38 AM, Greg KH wrote:
On Fri, Oct 28, 2011 at 11:48:12PM +0200, Hans J. Koch wrote:
On Fri, Oct 28, 2011 at 10:50:29AM -0500, Kumar Gala wrote:
For some devices, the default behavior of pgprot_noncached() is not
appropriate for all of its mappable regions. This provides
On Oct 28, 2011, at 2:40 PM, Jimi Xenidis wrote:
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote:
We had an existing ifdef for 4xx BOOKE processors that got changed to
CONFIG_PPC_ADV_DEBUG_REGS. The define has nothing to do with
CONFIG_PPC_ADV_DEBUG_REGS. The define really should be:
On Oct 28, 2011, at 3:43 PM, Jimi Xenidis wrote:
arch/powerpc/kernel/head_fsl_booke.S has the following code:
/* Data Storage Interrupt */
START_EXCEPTION(DataStorage)
NORMAL_EXCEPTION_PROLOG
mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
On Oct 28, 2011, at 2:37 PM, Jimi Xenidis wrote:
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote:
* set_dabr/do_dabr are no longer used when CNFIG_PPC_ADV_DEBUG_REGS is set
refactor code a bit such that we only build the dabr code for
!CONFIG_PPC_ADV_DEBUG_REGS and removed some
This is not the first user-space instruction. While executing this
process kernel has added two TLB entries with TID(process id) 1. while
trying to map 0x10fc it is raising pte faults .
Santosh Kumar .A
Vision without Action is a daydream... Action without Vision is a nightmare...
On 31
Hi All,
Please find the version 3 of the patchset that implements firmware-assisted
dump mechanism to capture kernel crash dump for Powerpc architecture. The
firmware-assisted dump is a robust mechanism to get reliable kernel crash
dump with assistance from firmware. This approach does not use
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Documentation for firmware-assisted dump. This document is based on the
original documentation written for phyp assisted dump by Linas Vepstas
and Manish Ahuja, with few changes to reflect the current implementation.
Change in v3:
- Modified the
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Reserve the memory during early boot to preserve CPU state data, HPTE region
and RMR region data in case of kernel crash. At the time of crash, powerpc
firmware will store CPU state data, HPTE region data and move RMR region
data to the reserved
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch registers for firmware-assisted dump using rtas token
ibm,configure-kernel-dump. During registration firmware is informed about
the reserved area where it saves the CPU state data, HPTE table and contents
of RMR region at the time of
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Build the crash memory range list by traversing through system memory during
the first kernel before we register for firmware-assisted dump. After the
successful dump registration, initialize the elfcore header and populate
PT_LOAD program headers
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
When registered for firmware assisted dump on powerpc, firmware preserves
the registers for the active CPUs during a system crash. This patch reads
the cpu register data stored in Firmware-assisted dump format (except for
crashing cpu) and
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
With the firmware-assisted dump support we don't require a reboot when we
are in second kernel after crash. The second kernel after crash is a normal
kernel boot and has knowledge about entire system RAM with the page tables
initialized for entire
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch introduces an sysfs interface '/sys/kernel/fadump_release_mem' to
invalidate the last fadump registration, invalidate '/proc/vmcore', release
the reserved memory for general use and re-register for future kernel dump.
Once the dump is
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Introduce a PT_NOTE program header that points to physical address of
vmcoreinfo_note buffer declared in kernel/kexec.c. The vmcoreinfo
note buffer is populated during crash_fadump() at the time of system
crash.
Signed-off-by: Mahesh Salgaonkar
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
If dump is active during system reboot, shutdown or halt then invalidate
the fadump registration as it does not get invalidated automatically.
Signed-off-by: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
---
arch/powerpc/kernel/setup-common.c |
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch introduces a new config option CONFIG_FA_DUMP for firmware
assisted dump feature on Powerpc (ppc64) architecture.
Signed-off-by: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
---
arch/powerpc/Kconfig | 13 +
1 files
On Oct 31, 2011, at 9:18 AM, Kumar Gala wrote:
On Oct 28, 2011, at 2:40 PM, Jimi Xenidis wrote:
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote:
We had an existing ifdef for 4xx BOOKE processors that got changed to
CONFIG_PPC_ADV_DEBUG_REGS. The define has nothing to do with
On Oct 31, 2011, at 9:21 AM, Kumar Gala wrote:
On Oct 28, 2011, at 2:37 PM, Jimi Xenidis wrote:
On Oct 5, 2011, at 9:53 PM, Kumar Gala wrote:
* set_dabr/do_dabr are no longer used when CNFIG_PPC_ADV_DEBUG_REGS is set
refactor code a bit such that we only build the dabr code for
Hello,
I've been tinkering with a series of patches to clean up the PowerPC
MPIC/OpenPIC init recently as part of a new board port I'm working on.
It's reached the point where I'd like some feedback on the general
approach. The code itself hasn't been tested at all yet, and probably
does not
This removes a bunch of extern declarations and CONFIG_SMP ifdefs.
Signed-off-by: Kyle Moffett kyle.d.moff...@boeing.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/platforms/85xx/corenet_ds.c
Instead of using the open-coded reg property lookup and address
translation in mpic_alloc(), directly call of_address_to_resource().
This includes various workarounds for special cases which the naive
of_address_translate() does not.
Afterwards it is possible to remove the copiously copy-pasted
All of the existing callers of mpic_alloc() pass in a non-NULL
device-node pointer, so the checks for a NULL device-node may be
removed.
Signed-off-by: Kyle Moffett kyle.d.moff...@boeing.com
---
arch/powerpc/sysdev/mpic.c | 50 ++-
1 files changed, 21
The MPIC code can already perform an automatic OF address translation
step as part of mpic_alloc(), but several boards need to use that base
address when they perform mpic_assign_isu().
The easiest solution is to save the computed physical address into the
struct mpic for later use by the board
Almost all PowerPC platforms use a standard open-pic device node so
the mpic_alloc() function now accepts NULL for the device-node. This
will cause it to perform a default search with of_find_matching_node().
Signed-off-by: Kyle Moffett kyle.d.moff...@boeing.com
---
It turns out that there are only 2 in-tree platforms which use MPICs
which are not primary: IBM Cell and PowerMac. To reduce the
complexity of the typical board setup code, invert the MPIC_PRIMARY bit
into MPIC_SECONDARY.
Signed-off-by: Kyle Moffett kyle.d.moff...@boeing.com
---
Don't open-code the OpenFirmware dcr-reg property lookup trying to map
DCR resources. This makes the code a bit easier to read.
Signed-off-by: Kyle Moffett kyle.d.moff...@boeing.com
---
arch/powerpc/sysdev/mpic.c |7 ++-
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git
There's not really any reason to have this one-liner in a separate
static inline function, given that all the other similar tests are
already in the alloc_mpic() code.
Signed-off-by: Kyle Moffett kyle.d.moff...@boeing.com
---
arch/powerpc/sysdev/mpic.c |7 +--
1 files changed, 1
The Cell and PowerMac platforms use virtually identical cascaded-IRQ
setup code, so just merge it into the core. This does the obvious thing
when an MPIC device-node specifies an interrupts property.
Signed-off-by: Kyle Moffett kyle.d.moff...@boeing.com
---
arch/powerpc/platforms/cell/setup.c
Store the node pointer in the MPIC during initialization so that all of
the later operational code can just reuse the cached pointer.
Signed-off-by: Kyle Moffett kyle.d.moff...@boeing.com
---
arch/powerpc/include/asm/mpic.h |3 +++
arch/powerpc/sysdev/mpic.c | 32
On Freescale parts with multiple MSI controllers, the controllers are
combined into one pool of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI
Hi Ben,
Please don't take this patch :)
While, it does work around some issues I'm tracking down, it can lead
to worse ones if we are unable to configure the larger DMA window, or if
some functions in a PE don't use 64-bit DMA masks.
Thanks,
Nish
On 26.10.2011 [15:43:23 -0700], Nishanth
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