I have dumped TLB entries while mapping shared memory. On both cores M-Bit
(MAS2[61]) is set in TLB0 entries. On both cores M-Bit is set for all valid
TLB1 entries. TLB1 does contains some invalid entries which has M-Bit cleared.
So I believe at this time the coherency is not the issue. Any
On 01/25/12 01:11, bruce_leon...@selinc.com wrote:
Good afternoon,
I'm using the 3.0.3 kernel running on an MPC8308 and am trying to
interface to a Cypress CY14B256Q2A non-volatile RAM via SPI. I've got the
SPI infrastructure, the Freescale SPI driver (drivers/spi/spi_fsl_spi.c),
and spidev
On 01/23/2012 10:50 PM, Benjamin Herrenschmidt wrote:
On Mon, 2012-01-23 at 13:21 -0600, Scott Wood wrote:
BTW, for non-booke, when is DEC checked when interrupts are hard-enabled
as part of exception return? Likewise with the PS3 HV thing. I only
see the iseries check in the exception path.
On 1/23/2012 10:53 PM, Rob Herring wrote:
On 01/23/2012 03:07 PM, Grant Likely wrote:
Hey everyone,
Here's the second RFC for the irq_domain patches. I could use some
help testing now. I still expect there will be a few bugs. The
series is based on v3.3-rc1, and I've pushed it out to my
On Tue, Jan 24, 2012 at 10:35 PM, Grant Likely
grant.lik...@secretlab.ca wrote:
On Tue, Jan 24, 2012 at 6:50 PM, Rob Herring robherri...@gmail.com wrote:
On 01/24/2012 06:18 PM, Grant Likely wrote:
Rather than having each interrupt controller driver creating its own barely
unique .xlate
On 01/25/2012 08:13 AM, Cousson, Benoit wrote:
On 1/23/2012 10:53 PM, Rob Herring wrote:
On 01/23/2012 03:07 PM, Grant Likely wrote:
Hey everyone,
Here's the second RFC for the irq_domain patches. I could use some
help testing now. I still expect there will be a few bugs. The
series is
Hi Norbert,
So the question is, how do I use spidev (or any other means) to get
the
8308 SPI controller to keep SPICLK active so that the output data from
the
NvRAM gets clocked out to the 8308?
Did you see Documentation/spi/spidev_fdx.c:do_msg ?
it perform a full-duplex (actually
On Thu, Jan 19, 2012 at 11:00 PM, Zhicheng Fan b32...@freescale.com wrote:
Signed-off-by: Fanzc b32...@freeescale.com
Please fix this. There are only two e's in freescale. In addition,
please use your full name.
--
Timur Tabi
Linux kernel developer at Freescale
On Mon, 2012-01-23 at 14:07 -0700, Grant Likely wrote:
Hey everyone,
Here's the second RFC for the irq_domain patches. I could use some
help testing now. I still expect there will be a few bugs. The
series is based on v3.3-rc1, and I've pushed it out to my git server:
Hi Grant,
I
From: Rob Herring rob.herr...@calxeda.com
On ARM, we don't want SPARSE_IRQ to be a user visible option. Make
SPARSE_IRQ visible based on MAY_HAVE_SPARSE_IRQ instead of depending
on HAVE_SPARSE_IRQ.
With this, SPARSE_IRQ is not visible on C6X and ARM.
Signed-off-by: Rob Herring
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