Replace netif_receive_skb with napi_gro_receive.
Signed-off-by: Jiajun Wu b06...@freescale.com
---
drivers/net/ethernet/freescale/gianfar.c | 13 +++--
1 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/freescale/gianfar.c
Benjamin Herrenschmidt b...@kernel.crashing.org writes:
This gets rid of the unused default senses array, and replaces the
incorrect use of IRQ_TYPE_NONE with the new IRQ_TYPE_DEFAULT for
the initial set_trigger() call when mapping an interrupt.
This in turn makes us read the HW state and
On 18.04.2012, at 18:01, Bharat Bhushan wrote:
Time for which the hrtimer is started for decrementer emulation is calculated
using tb_ticks_per_usec. While hrtimer uses the clockevent for DEC
reprogramming (if needed) and which calculate timebase ticks using the
multiplier and shifter
Original-Nachricht
Datum: Thu, 19 Apr 2012 14:41:16 +0200
Von: Michel Dänzer mic...@daenzer.net
An: Gerhard Pircher gerhard_pirc...@gmx.net
CC: linuxppc-dev@lists.ozlabs.org, sch...@linux-m68k.org,
ojordan12...@hotmail.co.uk
Betreff: Re: PowerPC radeon KMS - is it
On Fre, 2012-04-20 at 13:15 +0200, Gerhard Pircher wrote:
Von: Michel Dänzer mic...@daenzer.net
On Don, 2012-04-19 at 13:48 +0200, Gerhard Pircher wrote:
The former case is an explanation, why I see data corruption with my
AGPGART driver (more or less a copy of the uninorth driver)
Original-Nachricht
Datum: Fri, 20 Apr 2012 15:18:16 +0200
Von: Michel Dänzer mic...@daenzer.net
An: Gerhard Pircher gerhard_pirc...@gmx.net
CC: linuxppc-dev@lists.ozlabs.org
Betreff: Re: PowerPC radeon KMS - is it possible?
On Fre, 2012-04-20 at 13:15 +0200, Gerhard
There was refactoring change a while back that moved
the interrupt map down into the virtual pci bridge.
example:
42 /* controller at 0x20 */
43 pci0 {
44 compatible = fsl,p2041-pcie, fsl,qoriq-pcie-v2.2;
45 device_type = pci;
46 #size-cells = 2;
47
On Apr 20, 2012, at 1:37 PM, Yoder Stuart-B08248 wrote:
There was refactoring change a while back that moved
the interrupt map down into the virtual pci bridge.
example:
42 /* controller at 0x20 */
43 pci0 {
44 compatible = fsl,p2041-pcie, fsl,qoriq-pcie-v2.2;
45
On 04/20/2012 01:53 PM, Kumar Gala wrote:
On Apr 20, 2012, at 1:37 PM, Yoder Stuart-B08248 wrote:
There was refactoring change a while back that moved
the interrupt map down into the virtual pci bridge.
example:
42 /* controller at 0x20 */
43 pci0 {
44 compatible =
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Friday, April 20, 2012 1:54 PM
To: Yoder Stuart-B08248
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: pci node question
On Apr 20, 2012, at 1:37 PM, Yoder Stuart-B08248 wrote:
There was
On Apr 20, 2012, at 2:04 PM, Scott Wood wrote:
On 04/20/2012 01:53 PM, Kumar Gala wrote:
On Apr 20, 2012, at 1:37 PM, Yoder Stuart-B08248 wrote:
There was refactoring change a while back that moved
the interrupt map down into the virtual pci bridge.
example:
42 /* controller at
On 04/20/2012 03:37 PM, Kumar Gala wrote:
On Apr 20, 2012, at 2:04 PM, Scott Wood wrote:
On 04/20/2012 01:53 PM, Kumar Gala wrote:
On Apr 20, 2012, at 1:37 PM, Yoder Stuart-B08248 wrote:
There was refactoring change a while back that moved
the interrupt map down into the virtual pci
On Fri, 2012-04-20 at 13:53 -0500, Kumar Gala wrote:
On Apr 20, 2012, at 1:37 PM, Yoder Stuart-B08248 wrote:
There was refactoring change a while back that moved
the interrupt map down into the virtual pci bridge.
example:
42 /* controller at 0x20 */
43 pci0 {
44
On Fri, 2012-04-20 at 14:04 -0500, Scott Wood wrote:
That's not supposed to be how device tree bindings are determined.
Ugh ? This is nothing to do with Linux, I think Kumar is confused :-)
This has to do with PCI bindings.
If you put the interrupt-map in the parent, then crossing the virtual
On Fri, 2012-04-20 at 15:37 -0500, Kumar Gala wrote:
What does this node represent in the first place? Is there really a
PCI-to-PCI bridge? Are all other PCI devices underneath it?
PCIe has this concept of a virtual bridge between the root-comples,
so that is what the node represents.
Between the root complex and whatever's plugged in?
Yes.
so that is what the node represents. Its always been a bit confusing to me
as its not 100% standardized by PCI sig.
It's absolutely standard. The only case where you have siblings to
that RC is when it's some kind of integrated
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