Fixes built-in Bluetooth not working on Apple PowerBooks, regression from
commit 75fb0e324daa48ec458fb5c2960eb07b80cfad9d ('Bluetooth: Fix init sequence
for some CSR based controllers').
Cc: sta...@vger.kernel.org [v3.4]
Signed-off-by: Michel Dänzer mic...@daenzer.net
---
On Mon, 2012-06-25 at 14:28 +0800, Dong Aisheng wrote:
From: Dong Aisheng dong.aish...@linaro.org
prom_update_property() currently fails if the property doesn't
actually exist yet which isn't what we want. Change to add-or-update
instead of update-only, then we can remove a lot duplicated
Hi Michel,
Fixes built-in Bluetooth not working on Apple PowerBooks, regression from
commit 75fb0e324daa48ec458fb5c2960eb07b80cfad9d ('Bluetooth: Fix init sequence
for some CSR based controllers').
Cc: sta...@vger.kernel.org [v3.4]
Signed-off-by: Michel Dänzer mic...@daenzer.net
---
On Son, 2012-06-24 at 23:51 -0700, Marcel Holtmann wrote:
Hi Michel,
Fixes built-in Bluetooth not working on Apple PowerBooks, regression from
commit 75fb0e324daa48ec458fb5c2960eb07b80cfad9d ('Bluetooth: Fix init
sequence
for some CSR based controllers').
Cc:
Hi Michel,
Fixes built-in Bluetooth not working on Apple PowerBooks, regression from
commit 75fb0e324daa48ec458fb5c2960eb07b80cfad9d ('Bluetooth: Fix init
sequence
for some CSR based controllers').
Cc: sta...@vger.kernel.org [v3.4]
Signed-off-by: Michel Dänzer
On Mon, 2012-06-25 at 00:22 -0700, Marcel Holtmann wrote:
Hi Michel,
Fixes built-in Bluetooth not working on Apple PowerBooks, regression
from
commit 75fb0e324daa48ec458fb5c2960eb07b80cfad9d ('Bluetooth: Fix init
sequence
for some CSR based controllers').
Cc:
From: Dong Aisheng dong.aish...@linaro.org
prom_update_property() currently fails if the property doesn't
actually exist yet which isn't what we want. Change to add-or-update
instead of update-only, then we can remove a lot duplicated lines.
Suggested-by: Grant Likely grant.lik...@secretlab.ca
Hi Michel,
On Mon, Jun 25, 2012 at 09:32:50AM +0200, Michel Dänzer wrote:
Also, it would have been nice if that fix was promoted to stable, so I
wouldn't have had to spend a good part of the weekend bisecting...
Thinks like this happen. However after you bisected the issue you could
Fine with me, though FWIW that not only doesn't use
__constant_cpu_to_le16() but actually swaps the non-constant value.
Don't see what point you are trying to make here. Swapping the value
from the actual command structure is always fine with me.
The point is that the result of
On Mon, 2012-06-25 at 10:20 +0100, David Laight wrote:
Fine with me, though FWIW that not only doesn't use
__constant_cpu_to_le16() but actually swaps the non-constant value.
Don't see what point you are trying to make here. Swapping the value
from the actual command structure
On Mon, 2012-06-25 at 11:55 +1000, Anton Blanchard wrote:
We had a request for a fast method of getting CPU and NUMA node IDs
from userspace. Ben suggested we use SPRG3 which is userspace
readable. This is a quick hack to try that out.
I have a glibc patch to implement sched_getcpu using
SLUB duplicates the cache name in kmem_cache_create(). However if the
cache could be merged to others during early booting, the name pointer
is saved in saved_alias list, and the string needs to be kept valid
before slab_sysfs_init() is called.
This patch tries to duplicate the cache name in
This patch tries to kfree the cache name of pgtables cache if SLUB is
used, as SLUB duplicates the cache name, and the original one is leaked.
This patch depends on patch 1 -- (duplicate the cache name in
saved_alias list) in this mail thread. As the pgtables cache might be
merged to other
On 06/25/2012 05:53 PM, Li Zhong wrote:
SLUB duplicates the cache name in kmem_cache_create(). However if the
cache could be merged to others during early booting, the name pointer
is saved in saved_alias list, and the string needs to be kept valid
before slab_sysfs_init() is called.
This
On 06/25/2012 01:53 PM, Li Zhong wrote:
SLUB duplicates the cache name in kmem_cache_create(). However if the
cache could be merged to others during early booting, the name pointer
is saved in saved_alias list, and the string needs to be kept valid
before slab_sysfs_init() is called.
This patch
Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
for 64-bit hosts.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c
When delivering guest IRQs, update MSR computaion mode according to guest
interrupt computation mode found in EPCR.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git
Extend MAS2 EPN mask for 64-bit hosts, to retain most significant bits.
Change get tlb eaddr to use this mask.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/mmu-book3e.h |2 +-
arch/powerpc/kvm/e500.h |2 +-
2 files changed, 2
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is the version currently
supported by KVM, use
Add EPCR support in booke mtspr/mfspr emulation. EPCR register is defined
only for 64-bit and HV categories, so it shoud be available only on 64-bit
virtual processors. Undefine the support for 32-bit builds.
Define a reusable setter function for vcpu's EPCR.
Signed-off-by: Mihai Caraman
Include header file for get_tb() declaration.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index db05692..a427031 100644
---
Add emulation helper for getting instruction ea and refactor tlb instruction
emulation to use it.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500.h |6 +++---
arch/powerpc/kvm/e500_emulate.c | 21 ++---
arch/powerpc/kvm/e500_tlb.c
64-bit GCC 4.5.1 warns about an uninitialized variable which was guarded
by a flag. Initialize the variable to make it happy.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500_tlb.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git
64-bit host runs with lazy interrupt disabling, so local_irq_disable() does
not disable interrupts right away and does not protect against preemption
required by __kvmppc_vcpu_run(). Define a macro for 64-bit to use
hard_irq_disable().
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit booke
see head_fsl_booke.S file. Extend interrupt handlers' parameter list with
interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
handler to use the proper GSRRx save/restore registers.
Only the bolted
GET_VCPU define will not be implemented for 64-bit for performance reasons
so get rid of it also on 32-bit.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/bookehv_interrupts.S |7 ++-
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git
Refactor exception prolog to allow save/restore register parameters. Add
addition none definition for exception prolog usage.
This is needed for exceptions like Guest Doorbell that use GSRRx regsiters
which do not map on exception type.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
This patchset adds 64-bit Book3E PowerPC support to KVM. It is intended
as a request for comment for scratch register changes and for the support
limited to bolted TLB miss exception handlers.
This work was validated on Freescale's e5500 cores using P5020DS boards.
This patchset is based on Alex
Mask high 32 bits of effective address in emulation layer, for guests running
in 32-bit mode.
MAS2's high-order 32 bits represents the upper 32 bits of the effective address
of the page. Mask it too for tlbwe instruction emulation.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
Add bookehv interrupt handling support for 64-bit hosts. Change common stack
layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit execution
flow to the existing kvm_handler_common asm macro. Update input register
values documentation.
Only the bolted version of TLB miss exception
64-bit host needs to remain in 64-bit mode when an exception take place.
Set interrupt computaion mode in EPCR register.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500mc.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git
Machine check exception handler was using a wrong prolog. Hypervisors, like
KVM, which are called early from the exception handler rely on the interrupt
source.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kernel/exceptions-64e.S |2 +-
1 files changed, 1
tlbilxva emulation was using an u32 variable for guest effective address.
Replace it with gva_t type to handle 64-bit guests.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500mc.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git
On 06/25/2012 03:26 PM, Mihai Caraman wrote:
Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
for 64-bit hosts.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
On 06/25/2012 04:24 PM, Caraman Mihai Claudiu-B02008 wrote:
-Original Message-
From: Avi Kivity [mailto:a...@redhat.com]
Sent: Monday, June 25, 2012 4:00 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org;
-Original Message-
From: Avi Kivity [mailto:a...@redhat.com]
Sent: Monday, June 25, 2012 4:00 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org; qemu-...@nongnu.org
Subject: Re: [RFC PATCH 03/17] KVM: PPC64: booke:
The patch introduces additional wrapper function to call the original
implementation so that the DMA can be configured for all existing PEs.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
Reviewed-by: Ram Pai linux...@us.ibm.com
Reviewed-by: Richard Yang weiy...@linux.vnet.ibm.com
---
We don't need them anymore. The patch removes those functions.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
Reviewed-by: Ram Pai linux...@us.ibm.com
Reviewed-by: Richard Yang weiy...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci-ioda.c | 441 -
1
There're 2 arrays introduced to trace which PE has occupied the
corresponding resource (I/O or MMIO) segment. However, we didn't
allocate enough memory for them and that possiblly leads to PE
descriptor corruption.
The patch fixes that by allocating enough memory for those 2 arrays.
The resource (I/O and MMIO) will be assigned on basis of PE from
top to bottom so that we can implement the trick here: the resource
that has been assigned to parent PE could be taken by child PE if
necessary.
The current implementation already has PE list per PHB basis, but
the list doesn't meet
There're 2 types of PCI bus sensitive PEs: (A) The PE includes
single PCI bus. (B) The PE includes the PCI bus and all the subordinate
PCI buses, and the patch tries to assign I/O and MMIO resources
based on created PEs. Fortunately, we figured out unified scheme
to do resource assignment for all
The rework is done based on Ben's initial ideas on how PE and resource
assignment is done on top of PCI core instead of doing resource assignment
by powernv platform. With the series of patches, the following aspects will
be covered:
- Only create PE based on PCI bus. Basically, there
Currently, the PCI probe flags PCI_PROBE_ONLY | PCI_REASSIGN_ALL_RSRC
used on powernv platform. That means the platform has to do the PCI
resource assignment by itself.
The patch changes the PCI probe flag to PCI_REASSIGN_ALL_RSRC so
that the PCI core will do the resource assignment. Also, the
Basically, there're 2 types of PCI bus sensitive PEs: (A) The PE
includes single PCI bus. (B) The PE includes the PCI bus and all
the subordinate PCI buses. At present, we'd like to put PCI bus
originated by PCI-e link to form PE that contains single PCI bus,
and the PCIe-to-PCI bridge will form
While the device driver or PCI core tries to enable PCI device, the
platform dependent callback ppc_md.pcibios_enable_device_hook will
be called to check if there has one associated PE for the PCI device.
If we don't have the associated PE for the PCI device, it's not allowed
to enable the PCI
On Sun, Jun 24, 2012 at 8:10 PM, Gavin Shan sha...@linux.vnet.ibm.com wrote:
With current implementation, there is one function to retrieve
the corresponding host bridge (struct pci_host_bridge) according
to the given PCI device (struct pci_dev) and that function has
been declared as static.
From: Joe Liccese joe.licc...@freescale.com
The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
facilitate interoperability between a data path device and a look-aside
co-processor, the Interlaken Look-Aside protocol is defined for short
transaction-related transfers.
First 5 patches convert us to %r0-31.
Next 12 convert make using R0-31 required in macros.
Last 2 convert instructions where ra = r0 we use 0 rather than the
register value (as suggested by Andreas).
Version 4 add:
Fixes for bpf_jit code
Version 3 adds:
Fixes for chroma (moved some defines
We are going to use these later and convert r0 to %r0 etc.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h | 33 +
1 file changed, 33 insertions(+)
Index: b/arch/powerpc/include/asm/ppc-opcode.h
The assembler doesn't take %r0 register arguments in braces, so remove them.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc_asm.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
Index: b/arch/powerpc/include/asm/ppc_asm.h
Since we are taking a registers, this should never have been an sldi.
Talking to paulus offline, this is the correct fix.
Was introduced by:
commit 19ccb76a1938ab364a412253daec64613acbf3df
Author: Paul Mackerras pau...@samba.org
Date: Sat Jul 23 17:42:46 2011 +1000
Talking to paulus, this
Now all the fixes are in place, let's rock-n-roll!
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc_asm.h | 72 -
1 file changed, 39 insertions(+), 33 deletions(-)
Index: b/arch/powerpc/include/asm/ppc_asm.h
move lbz/stbciz to ppc-opcode.h.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h |7 +++
arch/powerpc/kernel/misc_64.S |5 -
2 files changed, 7 insertions(+), 5 deletions(-)
Index: b/arch/powerpc/include/asm/ppc-opcode.h
Merge the defines of STACKFRAMESIZE, STK_REG, STK_PARAM from different
places.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc_asm.h |5 +
arch/powerpc/lib/checksum_64.S |3
arch/powerpc/lib/copypage_power7.S |
Merge the defines of VCPU_GPR from different places.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc_asm.h |7 +++
arch/powerpc/kvm/book3s_hv_rmhandlers.S |3 ---
arch/powerpc/kvm/book3s_interrupts.S|8
mtocrf define is just a wrapper around the real instructions so we can
just use real register names here (ie. lower case).
Also remove braces in macro so this is possible.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/asm-compat.h |2 +-
LOAD_REG_ADDR define is just a wrapper around real instructions so we
can just use real register names here (ie. lower case).
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/platforms/powernv/opal-wrappers.S |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index:
These macros are using integers where they could be using logical
names since they take registers.
We are going to enforce this soon, so fix these up now.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/kernel/exceptions-64e.S |8
arch/powerpc/kernel/misc_64.S
We need to do this so we can enforce the name of a and b in called
macros PPC_RA/B later.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Index: b/arch/powerpc/include/asm/ppc-opcode.h
These are currently the same as __PPC_RA/B/S/T but we'll wrap them
soon.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h |4
1 file changed, 4 insertions(+)
Index: b/arch/powerpc/include/asm/ppc-opcode.h
Now have ___PPC_RA/B/S/T we can use it in some places. These are
places where we can't use the existing defines which will soon enforce
R0-R31 usage.
The macros being changed here are being used in inline asm, which
can't convert to enforce the R0-R31 usage.
bpf_jit uses a mix of both
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h | 33 +
1 file changed, 33 insertions(+)
Index: b/arch/powerpc/include/asm/ppc-opcode.h
===
---
Enforce the use of R0-R31 in macros where possible now we have all the
fixes in.
R0-R31 macros are removed here so that can't be used anymore. They
should not be defined anywhere.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h | 41
R0 is special since it'll be 0.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h | 34 ++
1 file changed, 34 insertions(+)
Index: b/arch/powerpc/include/asm/ppc-opcode.h
Some macros use RA where when RA=R0 the values is 0, so make this
the enforced mnemonic in the macro.
Idea suggested by Andreas Schwab.
Signed-off-by: Michael Neuling mi...@neuling.org
---
---
Index: b/arch/powerpc/include/asm/ppc-opcode.h
On 06/25/2012 01:28 AM, Dong Aisheng wrote:
From: Dong Aisheng dong.aish...@linaro.org
prom_update_property() currently fails if the property doesn't
actually exist yet which isn't what we want. Change to add-or-update
instead of update-only, then we can remove a lot duplicated lines.
With current implementation, there is one function to retrieve
the corresponding host bridge (struct pci_host_bridge) according
to the given PCI device (struct pci_dev) and that function has
been declared as static. Further, we don't have the public
function to retrieve host bridge from PCI
Hello Ben and Kumar,
Do you have any concerns or comments on these series of patches?
Would you please have a review?
Thanks.
-Jia Hongtao.
-Original Message-
From: Linuxppc-dev [mailto:linuxppc-dev-
bounces+b38951=freescale@lists.ozlabs.org] On Behalf Of Jia Hongtao-
B38951
On Tue, 2012-06-26 at 02:33 +, Jia Hongtao-B38951 wrote:
Hello Ben and Kumar,
Do you have any concerns or comments on these series of patches?
Would you please have a review?
My main concern is that currently the PCI code has some assumptions
about ordering of things that will get
On Mon, 2012-06-25 at 18:54 +0800, Wanlong Gao wrote:
On 06/25/2012 05:53 PM, Li Zhong wrote:
SLUB duplicates the cache name in kmem_cache_create(). However if the
cache could be merged to others during early booting, the name pointer
is saved in saved_alias list, and the string needs to be
On Tue, 2012-06-26 at 08:30 +0800, Gavin Shan wrote:
+EXPORT_SYMBOL(pci_bus_host_bridge);
Yinghai, thanks for your time on this :-)
why do you need to export it?
The reason is that we have introduced extra fields to struct
pci_host_bridge
in [PATCH 2/2] and platform want to access
My main concern is that currently the PCI code has some assumptions
about ordering of things that will get violated.
For example, the pci final fixups are an fs_initcall iirc, or something
like that. There's other similar oddities that might become problematic.
In addition, there might be
On Mon, 2012-06-25 at 15:10 +0400, Glauber Costa wrote:
On 06/25/2012 01:53 PM, Li Zhong wrote:
SLUB duplicates the cache name in kmem_cache_create(). However if the
cache could be merged to others during early booting, the name pointer
is saved in saved_alias list, and the string needs to
+EXPORT_SYMBOL(pci_bus_host_bridge);
Yinghai, thanks for your time on this :-)
why do you need to export it?
The reason is that we have introduced extra fields to struct
pci_host_bridge
in [PATCH 2/2] and platform want to access those extra fields.
But the platform code is
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