Andrew Morton writes:
> On Thu, 06 Jun 2013 09:31:06 +1000 Benjamin Herrenschmidt
> wrote:
>
>> On Wed, 2013-06-05 at 20:58 +0530, Aneesh Kumar K.V wrote:
>> >
>> > This is the second patchset needed to support THP on ppc64. Some of the
>> > changes
>> > included in this series are tricky in
On 06/06/2013 10:26 AM, Michael Neuling wrote:
> Anshuman Khandual wrote:
>
>> Completely ignore BHRB privilege state filter request as we are
>> already configuring that with privilege state filtering attribute
>> for the accompanying PMU event. This would help achieve cleaner
>> user space inte
Andy Lutomirski wrote:
> I broke them in this commit:
>
> commit 1be374a0518a288147c6a7398792583200a67261
> Author: Andy Lutomirski
> Date: Wed May 22 14:07:44 2013 -0700
>
> net: Block MSG_CMSG_COMPAT in send(m)msg and recv(m)msg
>
> This patch adds __sys_sendmsg and __
On Wed, 2013-06-05 at 22:25 -0700, Guenter Roeck wrote:
>
>
> Can you point me to some of the breaking code ? I guess it must be in some of
> the pci_dma_dev_setup callbacks, but those I looked at only check devicetree
> data or simply set function pointers, both of which should not be affected b
On Thu, Jun 06, 2013 at 11:00:04AM +1000, Benjamin Herrenschmidt wrote:
> On Sat, 2013-06-01 at 06:58 -0700, Guenter Roeck wrote:
> > the comment was actuially directed towards Yuanquan.
> >
> > No problem, take your time. I did my best to test it, but I agree that this
> > is a
> > critical area
From: Eric Dumazet
Date: Wed, 05 Jun 2013 21:35:25 -0700
> On Thu, 2013-06-06 at 12:56 +1000, Michael Neuling wrote:
>> On Thu, May 23, 2013 at 7:07 AM, Andy Lutomirski wrote:
>> > MSG_CMSG_COMPAT is (AFAIK) not intended to be part of the API --
>> > it's a hack that steals a bit to indicate to
Anshuman Khandual wrote:
> Completely ignore BHRB privilege state filter request as we are
> already configuring that with privilege state filtering attribute
> for the accompanying PMU event. This would help achieve cleaner
> user space interaction for BHRB.
>
> This patch fixes a situation lik
On Thu, 2013-06-06 at 12:56 +1000, Michael Neuling wrote:
> On Thu, May 23, 2013 at 7:07 AM, Andy Lutomirski wrote:
> > MSG_CMSG_COMPAT is (AFAIK) not intended to be part of the API --
> > it's a hack that steals a bit to indicate to other networking code
> > that a compat entry was used. So don'
benh,
FWIW this is fixing a regression from:
4474ef0 powerpc: Rework set_dabr so it can take a DABRX value as well
Mikey
Michael Neuling wrote:
> Some CPUs have a DABR but not DABRX. Configuration are:
> - No 32bit CPUs have DABRX but some have DABR.
> - POWER4+ and below have the DABR but
In commit 59affcd I added context switching of more PMU SPRs, because
they are potentially exposed to userspace on Power8. However despite me
being a smart arse in the commit message it's actually not correct. In
particular it interacts badly with a global perf record.
We will have to do something
In commit bc09c21 "Fix finding overflowed PMC in interrupt" we added
a printk() to the PMU exception handler. Unfortunately that is not safe.
The problem is that the PMU exception may run even when interrupts are
soft disabled, aka NMI context. We do this so that we can profile parts
of the kernel
Hi Anton,
On Thu, 6 Jun 2013 13:01:05 +1000 Anton Blanchard wrote:
>
> > This is causing a regression on 64bit powerpc with 32bit usermode.
> > When I hit userspace, udev is broken and I suspect all networking is
> > broken as well.
> >
> > Can we please revert 1be374a0518a288147c6a7398792583200
Hi,
> This is causing a regression on 64bit powerpc with 32bit usermode.
> When I hit userspace, udev is broken and I suspect all networking is
> broken as well.
>
> Can we please revert 1be374a0518a288147c6a7398792583200a67261
> upstream?
>
> Found via bisect.
Doesn't this patch break compat_s
On Thu, May 23, 2013 at 7:07 AM, Andy Lutomirski wrote:
> MSG_CMSG_COMPAT is (AFAIK) not intended to be part of the API --
> it's a hack that steals a bit to indicate to other networking code
> that a compat entry was used. So don't allow it from a non-compat
> syscall.
Dave & Linus
This is cau
From: Tang Yuantian
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v3:
- fix typo
v2:
- add t4240, b4420, b4860 support
- remove pll/4 clock from p2041, p3041 and p5020
On Sat, 2013-06-01 at 06:58 -0700, Guenter Roeck wrote:
> the comment was actuially directed towards Yuanquan.
>
> No problem, take your time. I did my best to test it, but I agree that this
> is a
> critical area of the code, and it would be desirable to get additional
> scrutiny
> and test fee
RTAS token "ibm,get-config-addr-info" or ibm,get-config-addr-info2"
are used to retrieve the PE address according to PCI address, which
made up of domain/bus/slot/function. If we don't have those 2 tokens,
the domain/bus/slot/function would be used as the address for EEH
RTAS operations. Some older
Quoting Robert Knight :
Sometime after kernel 3.3.4, Fedora 17 running on an IBM OpenPower
720 stopped being able to read the SCSI disks with an error
concerning a return code -1. In the updates since, it has not
resumed working.
Can you tell me which kernel you saw this issue(I assumed
On Thu, 06 Jun 2013 09:31:06 +1000 Benjamin Herrenschmidt
wrote:
> On Wed, 2013-06-05 at 20:58 +0530, Aneesh Kumar K.V wrote:
> >
> > This is the second patchset needed to support THP on ppc64. Some of the
> > changes
> > included in this series are tricky in that it changes the powerpc linux
On Wed, 2013-06-05 at 20:58 +0530, Aneesh Kumar K.V wrote:
>
> This is the second patchset needed to support THP on ppc64. Some of the
> changes
> included in this series are tricky in that it changes the powerpc linux page
> table
> walk subtly. We also overload few of the pte flags for ptes at
On Tue, 15 Jan 2013 15:38:54 +0800, Mike Qiu wrote:
> Multiple MSI only requires the IRQ in msi_desc entry to be set as
> the value of irq_base.
>
> This patch implements the above mentioned technique.
>
> Signed-off-by: Mike Qiu
Hi Mike,
question below...
> ---
> +int irq_set_multiple_msi_d
On Wed, 2013-06-05 at 16:41 +0100, David Laight wrote:
> > ptep = pte_offset_kernel(&pmd, addr);
> > do {
> > - pte_t pte = *ptep;
> > + pte_t pte = ACCESS_ONCE(*ptep);
>
> Why not just define ptep as a 'pointer to volatile'?
ACCESS_ONCE is the proper way to do it in L
On Wed, 2013-06-05 at 14:10 +0100, David Laight wrote:
> > If a BAR has the value of 0, we would assume that it is unset yet and
> > then mark the resource as unset and would reassign it later.
>
> IIRC the PCI spec allows a BAR address of zero.
> Certainly some sparc systems have assigned 0 to a
On 6/5/2013 6:01 PM, wenxi...@linux.vnet.ibm.com wrote:
Quoting Robert Knight :
Sometime after kernel 3.3.4, Fedora 17 running on an IBM OpenPower
720 stopped being able to read the SCSI disks with an error
concerning a return code -1. In the updates since, it has not
resumed working.
Can
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, June 04, 2013 1:11 PM
> To: Pan Lijun-B44306
> Cc: linuxppc-...@ozlabs.org; Pan Lijun-B44306
> Subject: Re: [PATCH 2/3] powerpc/perf: add 2 additional performance
> monitor counters for e6500 core
>
> On 05/29/2013 05:12:41
On 6/3/2013 11:52 PM, Gavin Shan wrote:
On Tue, Jun 04, 2013 at 01:16:52PM +1000, Tony Breeds wrote:
On Mon, Jun 03, 2013 at 09:40:52PM -0400, Robert Knight wrote:
On 6/3/2013 8:01 PM, Tony Breeds wrote:
On Mon, Jun 03, 2013 at 05:20:12PM -0400, Robert Knight wrote:
Device tree struct 0x000
On 06/05/2013 04:14:21 AM, Caraman Mihai Claudiu-B02008 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, June 05, 2013 1:54 AM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Caraman Mihai C
From: Catalin Udma
This change is required after the e6500 perf support has been added.
There are 6 counters in e6500 core instead of 4 in e500 core and
the MAX_HWEVENTS counter should be changed accordingly from 4 to 6.
Added also runtime check for counters overflow.
Signed-off-by: Catalin Udma
From: 'Priyanka Jain
e6500 core performance monitors has the following features:
- 6 performance monitor counters
- 512 events supported
- no threshold events
e6500 PMU has more specific events (Data L1 cache misses, Instruction L1
cache misses, etc ) than e500 PMU (which only had Data L1 cache
There are 6 counters in e6500 core instead of 4 in e500 core.
Signed-off-by: Lijun Pan
---
arch/powerpc/include/asm/reg_fsl_emb.h | 12
arch/powerpc/kernel/cputable.c |2 +-
arch/powerpc/oprofile/op_model_fsl_emb.c | 30 ++
arch/powerp
Signed-off-by: Lijun Pan
---
arch/powerpc/include/asm/reg_fsl_emb.h |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h
b/arch/powerpc/include/asm/reg_fsl_emb.h
index 77bb71c..1cf8ab0 100644
--- a/arch/powerpc/include/asm/reg_fsl_
Signed-off-by: Lijun Pan
---
arch/powerpc/include/asm/reg_fsl_emb.h |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h
b/arch/powerpc/include/asm/reg_fsl_emb.h
index 77bb71c..1cf8ab0 100644
--- a/arch/powerpc/include/asm/reg_fsl_
There are 6 counters in e6500 core instead of 4 in e500 core.
Signed-off-by: Lijun Pan
---
arch/powerpc/include/asm/reg_fsl_emb.h | 12
arch/powerpc/kernel/cputable.c |2 +-
arch/powerpc/oprofile/op_model_fsl_emb.c | 30 ++
arch/powerp
From: Catalin Udma
This change is required after the e6500 perf support has been added.
There are 6 counters in e6500 core instead of 4 in e500 core and
the MAX_HWEVENTS counter should be changed accordingly from 4 to 6.
Added also runtime check for counters overflow.
Signed-off-by: Catalin Udma
e6500 core performance monitors has the following features:
- 6 performance monitor counters
- 512 events supported
- no threshold events
e6500 PMU has more specific events (Data L1 cache misses, Instruction L1
cache misses, etc ) than e500 PMU (which only had Data L1 cache reloads,
etc). Where av
On 06/05/2013 02:29:47 AM, Caraman Mihai Claudiu-B02008 wrote:
> > case BOOKE_INTERRUPT_SPE_FP_ROUND:
> > +#ifdef CONFIG_SPE
> > kvmppc_booke_queue_irqprio(vcpu,
> > BOOKE_IRQPRIO_SPE_FP_ROUND);
> > r = RESUME_GUEST;
> > break;
>
> Why not use kvmpp
Hi Ben,
There is no change in this patchset and it applies cleanly on top of
v4 of Nvram-to-pstorepatches.
The patchset takes care of compressing oops messages while writing to NVRAM,
so that more oops data can be captured in the given space.
big_oops_buf (2.22 * oops_data_sz) is allocated for
This patch set exploits the pstore subsystem to read details of
of-config partition in NVRAM to a separate file in /dev/pstore.
For instance, of-config partition details will be stored in a
file named [of-nvram-5].
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim Keniston
---
arch/powerpc/p
This patch exploits pstore subsystem to read details of common partition
in NVRAM to a separate file in /dev/pstore. For instance, common partition
details will be stored in a file named [common-nvram-6].
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim Keniston
---
arch/powerpc/platforms/p
Introduce os_partition member in nvram_os_partition structure to identify
if the partition is an os partition or not. This will be useful to handle
non-os partitions of-config and common.
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim Keniston
---
arch/powerpc/platforms/pseries/nvram.c |
This patch set exploits the pstore subsystem to read details of rtas partition
in NVRAM to a separate file in /dev/pstore. For instance, rtas details will be
stored in a file named [rtas-nvram-4].
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim Keniston
---
arch/powerpc/platforms/pseries/n
IBM's p series machines provide persistent storage for LPARs through NVRAM.
NVRAM's lnx,oops-log partition is used to log oops messages.
Currently the kernel provides the contents of p-series NVRAM only as a
simple stream of bytes via /dev/nvram, which must be interpreted in user
space by the nvram
Introduce generic read function to read nvram partitions other than rtas.
nvram_read_error_log will be retained which is used to read rtas partition
from rtasd. nvram_read_partition is the generic read function to read from
any nvram partition.
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim
Removal of syslog prefix in the uncompressed oops text will
help in capturing more oops data.
Signed-off-by: Aruna Balakrishnaiah
Reviewed-by: Jim Keniston
---
arch/powerpc/platforms/pseries/nvram.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/ps
Introduce version and timestamp information in the oops header.
oops_log_info (oops header) holds version (to distinguish between old
and new format oops header), length of the oops text
(compressed or uncompressed) and timestamp.
The version field will sit in the same place as the length in old
h
Currently the kernel provides the contents of p-series NVRAM only as a
simple stream of bytes via /dev/nvram, which must be interpreted in user
space by the nvram command in the powerpc-utils package. This patch set
exploits the pstore subsystem to expose each partition in NVRAM as a
separate file
On 06/03/2013 09:36 AM, Stephen Warren wrote:
> From: Stephen Warren
>
> Previously, the #line parsing regex ended with ({WS}+[0-9]+)?. The {WS}
> could match line-break characters. If the #line directive did not contain
> the optional flags field at the end, this could cause any integer data on
On 06/05/2013 02:10:07 AM, Caraman Mihai Claudiu-B02008 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, June 05, 2013 12:39 AM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Alexander Graf
There are 6 counters in e6500 core instead of 4 in e500 core.
Signed-off-by: Lijun Pan
---
arch/powerpc/include/asm/reg_fsl_emb.h | 12
arch/powerpc/kernel/cputable.c |2 +-
arch/powerpc/oprofile/op_model_fsl_emb.c | 30 ++
arch/powerp
From: Catalin Udma
This change is required after the e6500 perf support has been added.
There are 6 counters in e6500 core instead of 4 in e500 core and
the MAX_HWEVENTS counter should be changed accordingly from 4 to 6.
Added also runtime check for counters overflow.
Signed-off-by: Catalin Udma
e6500 core performance monitors has the following features:
- 6 performance monitor counters
- 512 events supported
- no threshold events
e6500 PMU has more specific events (Data L1 cache misses, Instruction L1
cache misses, etc ) than e500 PMU (which only had Data L1 cache reloads,
etc). Where av
Signed-off-by: Lijun Pan
---
arch/powerpc/include/asm/reg_fsl_emb.h |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/reg_fsl_emb.h
b/arch/powerpc/include/asm/reg_fsl_emb.h
index 77bb71c..1cf8ab0 100644
--- a/arch/powerpc/include/asm/reg_fsl_
From: "Aneesh Kumar K.V"
Hugepage invalidate involves invalidating multiple hpte entries.
Optimize the operation using H_BULK_REMOVE on lpar platforms.
On native, reduce the number of tlb flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/machdep.h| 3 +
arch/powerpc/mm/
From: "Aneesh Kumar K.V"
If a hash bucket gets full, we "evict" a more/less random entry from it.
When we do that we don't invalidate the TLB (hpte_remove) because we assume
the old translation is still technically "valid". This implies that when
we are invalidating or updating pte, even if HPTE
> ptep = pte_offset_kernel(&pmd, addr);
> do {
> - pte_t pte = *ptep;
> + pte_t pte = ACCESS_ONCE(*ptep);
Why not just define ptep as a 'pointer to volatile'?
David
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Linuxppc-dev mailing list
Linuxppc-de
From: "Aneesh Kumar K.V"
We find all the overlapping vma and mark them such that we don't allocate
hugepage in that range. Also we split existing huge page so that the
normal page hash can be invalidated and new page faulted in with new
protection bits.
Signed-off-by: Aneesh Kumar K.V
---
arch
Hi,
This is the second patchset needed to support THP on ppc64. Some of the changes
included in this series are tricky in that it changes the powerpc linux page
table
walk subtly. We also overload few of the pte flags for ptes at PMD level (huge
page PTEs).
The related mm/ changes are already me
From: "Aneesh Kumar K.V"
We enable only if the we support 16MB page size.
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h | 3 +--
arch/powerpc/mm/pgtable_64.c | 29 +
2 files changed, 30 insertion
From: "Aneesh Kumar K.V"
THP code does PTE page allocation along with large page request and deposit them
for later use. This is to ensure that we won't have any failures when we split
hugepages to regular pages.
On powerpc we want to use the deposited PTE page for storing hash pte slot and
seco
From: "Aneesh Kumar K.V"
Replace find_linux_pte with find_linux_pte_or_hugepte and explicitly
document why we don't need to handle transparent hugepages at callsites.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h | 24
arch/powerpc/kernel
From: "Aneesh Kumar K.V"
The deposted PTE page in the second half of the PMD table is used to
track the state on hash PTEs. After updating the HPTE, we mark the
coresponding slot in the deposted PTE page valid.
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include
From: "Aneesh Kumar K.V"
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/gup.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/gup.c b/arch/powerpc/mm/gup.c
index 4b921af..3d36fd7 100644
--- a/arch/powerpc/mm/gu
From: "Aneesh Kumar K.V"
We need to use smb_rmb when looking at hpte slot array. Otherwise we could
reorder the hpte_slot array load bfore even we marked the pmd trans huge.
Related smb_wmb()s is done in pgtable_trans_huge_deposit when we deposit
a pgtable.
Signed-off-by: Aneesh Kumar K.V
---
From: "Aneesh Kumar K.V"
We now have pmd entries covering 16MB range and the PMD table double its
original size.
We use the second half of the PMD table to deposit the pgtable (PTE page).
The depoisted PTE page is further used to track the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hugetlbpage.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 2865077
From: "Aneesh Kumar K.V"
With THP we set pmd to none, before we do pte_clear. Hence we can't
walk page table to get the pte lock ptr and verify whether it is locked.
THP do take pte lock before calling pte_clear. So we don't change the locking
rules here. It is that we can't use page table walkin
From: "Aneesh Kumar K.V"
GCC is very likely to read the pagetables just once and cache them in
the local stack or in a register, but it is can also decide to re-read
the pagetables. The problem is that the pagetable in those places can
change from under gcc.
With THP/hugetlbfs the pmd (and pgd f
From: "Aneesh Kumar K.V"
We need to have irqs disabled to handle all the possible parallel update for
linux page table without holding locks.
Events that we are intersted in while walking page tables are
1) Page fault
2) umap
3) THP split
4) THP collapse
A) local_irq_disabled:
-
From: "Aneesh Kumar K.V"
We will use this in the later patch for handling THP pages
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/hugetlb.h | 8 +-
arch/powerpc/include/asm/pgtable-ppc64.h | 13 --
arch/powerpc/include/asm/pgtable.h |
> If a BAR has the value of 0, we would assume that it is unset yet and
> then mark the resource as unset and would reassign it later.
IIRC the PCI spec allows a BAR address of zero.
Certainly some sparc systems have assigned 0 to a BAR.
So assuming a BAR of 0 means it is unset may not be
true for
On Wednesday, June 05, 2013 04:06:29 PM Viresh Kumar wrote:
> On 5 June 2013 15:00, wrote:
> > From: Tang Yuantian
> >
> > Add cpufreq driver for Freescale e500mc, e5500 and e6500 SoCs
> > which are capable of changing the CPU frequency dynamically
> >
> > Signed-off-by: Tang Yuantian
> > Signe
If a BAR has the value of 0, we would assume that it is unset yet and
then mark the resource as unset and would reassign it later. But after
commit 6c5705fe (powerpc/PCI: get rid of device resource fixups)
the pcibios_fixup_resources is invoked after the bus address was
translated to linux resource
On 5 June 2013 15:00, wrote:
> From: Tang Yuantian
>
> Add cpufreq driver for Freescale e500mc, e5500 and e6500 SoCs
> which are capable of changing the CPU frequency dynamically
>
> Signed-off-by: Tang Yuantian
> Signed-off-by: Li Yang
> ---
> v5:
> - enhance the CPU hotplug case
>
From: Tang Yuantian
Add cpufreq driver for Freescale e500mc, e5500 and e6500 SoCs
which are capable of changing the CPU frequency dynamically
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v5:
- enhance the CPU hotplug case
- mask the disallowed CPU frequencies
On Wednesday 05 June 2013 03:13 PM, Benjamin Herrenschmidt wrote:
On Wed, 2013-06-05 at 14:30 +0530, Aruna Balakrishnaiah wrote:
Hi Ben,
On Saturday 01 June 2013 10:55 AM, Benjamin Herrenschmidt wrote:
Another question...
Should the core pstore fail to unlink partitions that don't have
an ->e
On Wed, 2013-06-05 at 14:30 +0530, Aruna Balakrishnaiah wrote:
> Hi Ben,
>
> On Saturday 01 June 2013 10:55 AM, Benjamin Herrenschmidt wrote:
> > Another question...
> >
> > Should the core pstore fail to unlink partitions that don't have
> > an ->erase callback ? IE. Why would you let anyone eras
> > + * Simulate AltiVec unavailable fault to load guest state
> > + * from thread to AltiVec unit.
> > + * It requires to be called with preemption disabled.
> > + */
> > +static inline void kvmppc_load_guest_altivec(struct kvm_vcpu *vcpu)
> > +{
> > +#ifdef CONFIG_ALTIVEC
> > + if (cpu_has_feat
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, June 05, 2013 1:54 AM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Caraman Mihai Claudiu-B02008
> Subject: Re: [RFC PATCH 6/6] KVM: PPC: Book3E: En
On 6/4/2013 6:16 PM, Brian King wrote:
Wendy - do you have access to
one of these systems so we could take a look at this?
I can provide access if there's not another available.
Regards,
Robert
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Hi Ben,
On Saturday 01 June 2013 10:55 AM, Benjamin Herrenschmidt wrote:
Another question...
Should the core pstore fail to unlink partitions that don't have
an ->erase callback ? IE. Why would you let anyone erase the OFW
common partition for example ? That means that userspace tools
can no lo
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, June 05, 2013 1:28 AM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Caraman Mihai Claudiu-B02008
> Subject: Re: [RFC PATCH 3/6] KVM: PPC: Book3E: Re
The patch creates debugfs entries (powerpc/PCI/err_injct) for
injecting EEH errors for testing purpose.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/eeh-ioda.c | 33 -
1 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/p
The patch intends to register OPAL event notifier and process the
PCI errors from firmware. If we have pending PCI errors, the kthread
will be invoke to handle that in turn.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/pci-err.c | 15 +++
1 files changed, 15 inserti
The patch creates one debugfs directory ("powerpc/PCI") for
each PHB so that we can hook EEH error injection debugfs entry
there in proceeding patch.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/pci-ioda.c | 22 ++
arch/powerpc/platforms/powernv/pci.h
While we're restarting or powering off the system, we needn't
the OPAL notifier any more. So just to disable that.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/setup.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/setup
The patch intends to implement the notifier for variable OPAL events.
It's notable that the notifier can be disabled dynamically. Also, the
notifier could be fired upon incoming OPAL interrupts, or enabling
the OPAL notifier.
Signed-off-by: Gavin Shan
---
arch/powerpc/include/asm/opal.h |
The patch adds EEH backends for PowerNV platform. It's notable that
part of those EEH backends call to the I/O chip dependent backends.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/Makefile |2 +-
arch/powerpc/platforms/powernv/eeh-powernv.c | 387 ++
On PowerNV platform, the EEH event is produced either by detect
on accessing config or I/O registers, or by interrupts dedicated
for EEH report. The patch adds support to process the interrupts
dedicated for EEH report.
Firstly, the kernel thread will be waken up to process incoming
interrupt. The
The patch initializes EEH for PowerNV platform. Because the OPAL
APIs requires HUB ID, we need trace that through struct pnv_phb.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/pci-ioda.c | 16 +---
arch/powerpc/platforms/powernv/pci-p5ioc2.c |6 --
2 files
It's meaningless to handle frozen PE if we already had fenced PHB.
The patch intends to check the PHB state before checking PE. If the
PHB has been put into fenced state, we need take care of that firstly.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/pseries/eeh.c | 61
The patch enables EEH check and let EEH core to process the EEH
errors for PowerNV platform while accessing config space. Originally,
the implementation already had mechanism to check EEH errors and
tried to recover from them. However, we never let EEH core to handle
the EEH errors.
Signed-off-by:
The patch adds the I/O chip backend to do PE reset. For now, we
focus on PCI bus dependent PE. If PHB PE has been put into error
state, the PHB will take complete reset. Besides, the root bridge
will take fundamental or hot reset accordingly if the indicated
PE locates at the toppest of PCI hierarc
The patch adds backends to retrieve error log and configure p2p
bridges for the indicated PE.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/eeh-ioda.c | 57 -
1 files changed, 55 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/power
The patch adds I/O chip backend to retrieve the state for the
indicated PE. While the PE state is temperarily unavailable,
we return the default wait time (1000ms).
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/eeh-ioda.c | 102 -
1 files changed, 101
The patch adds the backend to enable or disable EEH functionality
for the specified PE. The backend is also used to enable MMIO or
DMA path for the problematic PE. It's notable that all PEs on
PowerNV platform support EEH functionality by default, and we
disallow to disable EEH for the specific PE.
For EEH on PowerNV platform, the overall architecture is a bit
different from that on pSeries platform. In order to support multiple
I/O chips in future, we split EEH to 3 layers for PowerNV platform:
EEH core, platform layer, I/O layer. It would give EEH implementation
on PowerNV much more flexibi
The post initialization (struct eeh_ops::post_init) is called after
the EEH probe is done. On the other hand, the EEH core post initialization
is designed to call platform and then I/O chip backend on PowerNV
platform.
The patch adds the backend for I/O chip to notify the platform
the specific PHB
The patch synchronizes OPAL APIs between kernel and firmware. Also,
we starts to replace opal_pci_get_phb_diag_data() with the similar
opal_pci_get_phb_diag_data2() and the former OPAL API would return
OPAL_UNSUPPORTED from now on.
Signed-off-by: Gavin Shan
---
arch/powerpc/include/asm/opal.h
The patch adds new EEH operation post_init. It's used to notify
the platform that EEH core has completed the EEH probe. By that,
PowerNV platform starts to use the services supplied by EEH
functionality.
Signed-off-by: Gavin Shan
---
arch/powerpc/include/asm/eeh.h |1 +
arch/powerpc/pl
The EEH event is usually produced because of 0xFF's returned from
PCI config or I/O registers. PowerNV platform also can produce EEH
event through interrupts. The patch differentiates the EEH events
produced for different cases in order to process them differently
in future.
Signed-off-by: Gavin S
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