'pe_no' hasn't been defined, it should be an typo error,
it should be 'frozen_pe_no'.
Also '__func__' has missed in IODA_EEH_DBG(),
For safety reasons, use pr_info() directly, instead
of use IODA_EEH_DBG()
Signed-off-by: Mike Qiu qiud...@linux.vnet.ibm.com
---
On Tue, Aug 06, 2013 at 08:35:10PM +1000, Benjamin Herrenschmidt wrote:
On Tue, 2013-08-06 at 18:23 +0800, Kevin Hao wrote:
In function flush_icache_range(), we use cpu_has_feature() to test
the feature bit of CPU_FTR_COHERENT_ICACHE. But this seems not optimal
for two reasons:
a) For
On Tue, Aug 06, 2013 at 08:36:38PM +1000, Benjamin Herrenschmidt wrote:
On Tue, 2013-08-06 at 18:23 +0800, Kevin Hao wrote:
We don't need to flush the dcache and invalidate the icache on the
CPU which has CPU_FTR_COHERENT_ICACHE set.
Actually we probably need an isync...
Will add.
Transactional memory will restore the TAR, PPR and DSCR on transaction failure.
Add these to the thread_struct for use in the future
Signed-off-by: Michael Neuling mi...@neuling.org
Cc: sta...@vger.kernel.org
---
arch/powerpc/include/asm/processor.h | 4
arch/powerpc/kernel/asm-offsets.c
Add save_tar() function to save the Target Address Register (TAR). This will
be used in a future patch to save the TAR earlier than it currently is.
Signed-off-by: Michael Neuling mi...@neuling.org
Cc: sta...@vger.kernel.org
---
arch/powerpc/include/asm/switch_to.h | 5 +
Currently we don't save and restore the checkpointed TAR, PPR and DSCR.
This adds the required save and restore to the treclaim and trechkpt code.
Signed-off-by: Michael Neuling mi...@neuling.org
Cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/tm.S | 20
1 file changed,
This moves us to use the save_tar() function to save the Target Address
Register (TAR) a lot earlier in __switch_to.
We need to save the TAR earlier as we may overwrite it in the transactional
memory reclaim/recheckpoint path.
Signed-off-by: Michael Neuling mi...@neuling.org
Cc:
'pe_no' hasn't been defined, it should be an typo error,
it should be 'frozen_pe_no'.
Also '__func__' has missed in IODA_EEH_DBG(),
For safety reasons, use pr_devel() directly, instead
of use IODA_EEH_DBG()
Signed-off-by: Mike Qiu qiud...@linux.vnet.ibm.com
---
On 08/06/2013 10:43 PM, Gerhard Sittig wrote:
the .get_clock() callback is run from probe() and might allocate
resources, introduce a .put_clock() callback that is run from remove()
to undo any allocation activities
prepare and enable the clocks in open(), disable and unprepare the
clocks
On 08/06/2013 10:43 PM, Gerhard Sittig wrote:
the .get_clock() callback is run from probe() and might allocate
resources, introduce a .put_clock() callback that is run from remove()
to undo any allocation activities
AFAICS With this patch put_clock() is still a no-op, is there a patch
which
On 08/07/2013 09:30 AM, Marc Kleine-Budde wrote:
On 08/06/2013 10:43 PM, Gerhard Sittig wrote:
the .get_clock() callback is run from probe() and might allocate
resources, introduce a .put_clock() callback that is run from remove()
to undo any allocation activities
AFAICS With this patch
[ no change in content, but order shuffling for better application ]
On Tue, Aug 06, 2013 at 23:31 +0200, Gerhard Sittig wrote:
[ this is an overview on how to split the series if necessary ]
On Tue, Aug 06, 2013 at 22:43 +0200, Gerhard Sittig wrote:
this series
- fixes several
On Wed, Aug 07, 2013 at 04:11:56PM +1000, Michael Neuling wrote:
Add save_tar() function to save the Target Address Register (TAR). This will
be used in a future patch to save the TAR earlier than it currently is.
Signed-off-by: Michael Neuling mi...@neuling.org
Cc: sta...@vger.kernel.org
Hi,
Please find the patch set that performs the machine check handling inside linux
host. The design is to be able to handle re-entrancy so that we do not clobber
the machine check information during nested machine check interrupt.
The patch 2 implements the logic to save the raw MCE info onto
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch adds the early machine check function pointer in cputable for
CPU specific early machine check handling. The early machine handle routine
will be called in real mode to handle SLB and TLB errors. This patch just
sets up a mechanism
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
If we get a machine check exception due to SLB or TLB errors, then flush
SLBs/TLBs and reload SLBs to recover. We do this in real mode before turning
on MMU. Otherwise we would run into nested machine checks.
If we get a machine check when we are
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch splits the common exception prolog logic into two parts to
facilitate reuse of existing code in the next patch. The second part will
be reused in the machine check exception routine in the next patch.
Please note that this patch does
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Move machine check entry point into Linux. So far we were dependent on
firmware to decode MCE error details and handover the high level info to OS.
This patch introduces early machine check routine that saves the MCE
information (srr1, srr0, dar
Now that we have weak versions for each of the PCI MSI architecture
functions, we can actually build the MSI support for all platforms,
regardless of whether they provide or not architecture-specific
versions of those functions. For this reason, the ARCH_SUPPORTS_MSI
hidden kconfig boolean becomes
Until now, the MSI architecture-specific functions could be overloaded
using a fairly complex set of #define and compile-time
conditionals. In order to prepare for the introduction of the msi_chip
infrastructure, it is desirable to switch all those functions to use
the 'weak' mechanism. This
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch introduces flush_tlb operation in cpu_spec structure. This will
help us to invoke appropriate CPU-side flush tlb routine. This patch
adds the foundation to invoke CPU specific flush routine for respective
architectures. Currently this
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch handles the memory errors on power8. If we get a machine check
exception due to SLB or TLB errors, then flush SLBs/TLBs and reload SLBs to
recover.
I do not have access to power8 box, hence this patch haven't been tested
yet.
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Add basic error handling in machine check exception handler.
- If MSR_RI isn't set, we can not recover.
- Check if disposition set to OpalMCE_DISPOSITION_RECOVERED.
- Check if address at fault is inside kernel address space, if not then send
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Now that we handle machine check in linux, the MCE decoding should also
take place in linux host. This info is crucial to log before we go down
in case we can not handle the machine check errors. This patch decodes
and populates a machine check
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Now that we are ready to handle machine check directly in linux, do not
register with firmware to handle machine check exception.
Signed-off-by: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/opal.c |8
-Original Message-
From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org]
Sent: Saturday, July 13, 2013 7:07 AM
To: Wood Scott-B07421
Cc: Wang Dongsheng-B40534; Wood Scott-B07421; johan...@sipsolutions.net;
an...@enomsg.org; ga...@kernel.crashing.org; linuxppc-
+#ifdef CONFIG_PPC_BOOK3S_64
+_GLOBAL(_save_tar)
+ /*
+* Back up the TAR across context switches. Note that the TAR is not
+* available for use in the kernel. (To provide this, the TAR should
+* be backed up/restored on exception entry/exit instead, and be in
+*
Patch attempts to improve the performace of __arch_hweight functions by
making them inline instead of current out of line implementation.
Testcase is to disable/enable SMT on a large (192 thread) POWER7 lpar.
Program used for SMT disable/enable is ppc64_cpu with --smt=[off/on]
option. Here are
2013/8/3 Gerhard Sittig g...@denx.de:
On Wed, Jul 31, 2013 at 11:20 +0400, Alexander Popov wrote:
Please make sure to either cite
properly or to properly mark changes as such. Don't spread false
information, please. You are free to change what I submitted,
but you should not pretend that I
2013/8/3 Gerhard Sittig g...@denx.de:
On Wed, Jul 31, 2013 at 11:21 +0400, Alexander Popov wrote:
You don't provide a lot of information to those you want to
receive feedback from. You should keep a history and list the
changes between versions. And you may want to somehow link this
v3 to
On Tue, Aug 06, 2013 at 06:55:00PM -0500, Scott Wood wrote:
On Tue, 2013-08-06 at 18:10 -0500, Scott Wood wrote:
On Thu, 2013-08-01 at 19:49 +0200, Lutz Jaenicke wrote:
The TBIPA register is part of gianfar's full register set. When starting
from the MII registers, the start address of
This change improves and cleans up the tile console.
- We enable HVC_IRQ support on tilegx, with the addition of a new
Tilera hypervisor API for tilegx to allow a console IPI. If IPI
support is not available we fall back to the previous polling mode.
- We simplify the earlyprintk code to
On Aug 6, 2013, at 3:43 PM, Gerhard Sittig wrote:
this series
- fixes several drivers that are used in the MPC512x platform (UART,
SPI, ethernet, PCI, USB, CAN, NAND flash, video capture) in how they
handle clocks (appropriately acquire and setup them, hold references
during use, release
Oh - one more thing - and my apologies for not spotting this before:
dst = allocate_buf_for_compression(big_buf_sz);
No - you may not call kmalloc() in oops/panic context. Please pre-allocate
everything you need in some initialization code to make sure that we don't
fail in the
On Wed, 2013-08-07 at 15:09 +0530, Mahesh J Salgaonkar wrote:
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index a1aba53..0b5b04a 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -35,7 +35,7 @@ obj-y :=
On Wed, 2013-08-07 at 16:22 +0200, Lutz Jaenicke wrote:
On Tue, Aug 06, 2013 at 06:55:00PM -0500, Scott Wood wrote:
On Tue, 2013-08-06 at 18:10 -0500, Scott Wood wrote:
On Thu, 2013-08-01 at 19:49 +0200, Lutz Jaenicke wrote:
The TBIPA register is part of gianfar's full register set. When
On Tue, Aug 6, 2013 at 10:35 PM, Tony Luck tony.l...@gmail.com wrote:
ERST is at the whim of the BIOS writer (the ACPI standard doesn't provide any
suggestions on record sizes). My systems support ~6K record size.
Off by a little - 7896 bytes on my current machine.
efivars has, IIRC, a 1k
This patch fixes a bug that is triggered when cts(cbc(aes)) is used with
nx-crypto driver on input larger than 32 bytes.
The chaining value from co-processor was not being saved. This value is
needed because it is used as the IV by cts(cbc(aes)).
Signed-off-by: Fionnuala Gunter
On Wed, 2013-07-31 at 21:32 -0500, Liu Po-B43644 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, July 31, 2013 11:47 PM
To: Liu Po-B43644
Cc: Wood Scott-B07421; linuxppc-...@ozlabs.org; ga...@kernel.crashing.org;
Fleming Andy-AFLEMING; Hu Mingkai-B21284
On Thu, Apr 11, 2013 at 09:56:30PM +0800, Zhenhua Luo wrote:
When using recent udev, the /dev node mount requires CONFIG_DEVTMPFS_MOUNT
is enabled in Kernel. The patch enables the option in defconfig of Freescale
QorIQ targets.
Changed defconfig list:
On Fri, Jun 21, 2013 at 06:59:12PM +0800, Minghuan Lian wrote:
Add compatible fsl,mpic-msi-v4.3 for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. When using
MSIR1, the interrupt number
On Fri, Jun 21, 2013 at 06:59:14PM +0800, Minghuan Lian wrote:
The original MPIC MSI bank contains 8 registers, MPIC v4.3 MSI bank
contains 16 registers, and this patch adds NR_MSI_REG_MAX and
NR_MSI_IRQS_MAX to describe the maximum capability of MSI bank.
MPIC v4.3 provides MSIIR1 to index
On Tue, May 14, 2013 at 04:05:56PM +0800, Dongsheng Wang wrote:
This problem belongs to the core synchronization issues.
The cpu1 already updated spin_table values, but bootcore cannot get
this value in time.
After bootcpu hibiernation restore the pages. we are now running
with the kernel
Transactional memory will restore the TAR, PPR and DSCR on transaction failure.
Add these to the thread_struct for use in the future
Signed-off-by: Michael Neuling mi...@neuling.org
Cc: sta...@vger.kernel.org
---
arch/powerpc/include/asm/processor.h | 4
arch/powerpc/kernel/asm-offsets.c
Add save_tar() function to save the Target Address Register (TAR). This will
be used in a future patch to save the TAR earlier than it currently is.
Signed-off-by: Michael Neuling mi...@neuling.org
Cc: sta...@vger.kernel.org
---
arch/powerpc/include/asm/switch_to.h | 9 +
This moves us to use the save_tar() function to save the Target Address
Register (TAR) a lot earlier in __switch_to.
We need to save the TAR earlier as we may overwrite it in the transactional
memory reclaim/recheckpoint path.
Signed-off-by: Michael Neuling mi...@neuling.org
Cc:
Currently we don't save and restore the checkpointed TAR, PPR and DSCR.
This adds the required save and restore to the treclaim and trechkpt code.
Signed-off-by: Michael Neuling mi...@neuling.org
Cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/tm.S | 20
1 file changed,
From: Wang Dongsheng dongsheng.w...@freescale.com
Update the 64-bit hibernation code to support Book E CPUs.
Some registers and instructions are not defined for Book3e
(SDR reg, tlbia instruction).
SDR: Storage Description Register. Book3S and Book3E have different
address translation mode, we
On 08/08/2013 12:11 AM, Scott Wood wrote:
On Wed, 2013-08-07 at 15:09 +0530, Mahesh J Salgaonkar wrote:
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index a1aba53..0b5b04a 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -35,7 +35,7
Hi Tony,
On Thursday 08 August 2013 03:52 AM, Tony Luck wrote:
On Tue, Aug 6, 2013 at 10:35 PM, Tony Luck tony.l...@gmail.com wrote:
ERST is at the whim of the BIOS writer (the ACPI standard doesn't provide any
suggestions on record sizes). My systems support ~6K record size.
Off by a little
On 08/07/2013 03:08 PM, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch splits the common exception prolog logic into two parts to
facilitate reuse of existing code in the next patch. The second part will
be reused in the machine check exception
On Thu, 2013-08-08 at 09:40 +0530, Anshuman Khandual wrote:
On 08/07/2013 03:08 PM, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
This patch splits the common exception prolog logic into two parts to
facilitate reuse of existing code in the next patch. The
On Wednesday 07 August 2013 11:00 PM, Tony Luck wrote:
Oh - one more thing - and my apologies for not spotting this before:
dst = allocate_buf_for_compression(big_buf_sz);
No - you may not call kmalloc() in oops/panic context. Please pre-allocate
everything you need in some
On 08/07/2013 03:08 PM, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Move machine check entry point into Linux. So far we were dependent on
firmware to decode MCE error details and handover the high level info to OS.
This patch introduces early machine check
On Wed, Aug 7, 2013 at 9:29 PM, Aruna Balakrishnaiah
ar...@linux.vnet.ibm.com wrote:
When we preallocate, we can use the same big_buf for compression as well as
decompression.
Also workspace will be one for both. By allocating max of inflate workspace
size and deflate
workspace size. We can
On Wed, Aug 07, 2013 at 03:09:13PM +0530, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Now that we handle machine check in linux, the MCE decoding should also
take place in linux host. This info is crucial to log before we go down
in case we can not handle the
On Wed, Aug 07, 2013 at 03:08:15PM +0530, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Move machine check entry point into Linux. So far we were dependent on
firmware to decode MCE error details and handover the high level info to OS.
This patch introduces
On Wed, Aug 07, 2013 at 03:08:55PM +0530, Mahesh J Salgaonkar wrote:
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
If we get a machine check exception due to SLB or TLB errors, then flush
SLBs/TLBs and reload SLBs to recover. We do this in real mode before turning
on MMU. Otherwise we
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