-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, September 26, 2013 12:23 PM
To: Wang Dongsheng-B40534; Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v4 4/4] powerpc/85xx: add sysfs for pw20 state and
altivec idle
-Original
This is an optimization for the PowerPC in 64-bit
little-endian. Bit counting is used in find_zero(), instead
of the multiply and shift.
It is modelled after Alan Modra's PowerPC LE strlen patch
http://sourceware.org/ml/libc-alpha/2013-08/msg00097.html.
Signed-off-by: Philippe Bergheaud
Add the plumbing to implement arch_get_random_long/int(). It didn't seem
worth adding an extra ppc_md hook for int, so we reuse the one for long.
Add an implementation for powernv based on the hwrng found in power7+
systems. We whiten the output of the hwrng, and the result passes all
the
Add a driver for the hwrng found in power7+ systems, based on the
existing code for the arch_get_random_long() hook.
We only register a single instance of the driver, not one per device,
because we use the existing per_cpu array of devices in the arch code.
This means we always read from the
Some powernv systems include a hwrng. Guests can access it via the
H_RANDOM hcall.
We add a real mode implementation of H_RANDOM when a hwrng is found.
Userspace can detect the presence of the hwrng by quering the
KVM_CAP_PPC_HWRNG capability.
Signed-off-by: Michael Ellerman
On Wed, Sep 25, 2013 at 05:00:16PM -0400, Tejun Heo wrote:
Hello,
On Wed, Sep 25, 2013 at 10:58:05PM +0200, Alexander Gordeev wrote:
Unfortunately, pSeries is a shows-topper here :( It seems we have to
introduce pci_get_msi{,x}_limit() interfaces to honour the quota
thing. I just hope
Hi,
sorry for the lat response, as I've been traveling in the last weeks.
At Thu, 19 Sep 2013 22:53:02 +0100,
Russell King wrote:
This code sequence is unsafe in modules:
static u64 mask = DMA_BIT_MASK(something);
...
if (!dev-dma_mask)
dev-dma_mask = mask;
as if
Previously PSERIES_MSI depended on PPC_PSERIES via EEH. However in
commit 317f06d powerpc/eeh: Move common part to kernel directory we
made CONFIG_EEH selectable on POWERNV. That leaves us with PSERIES_MSI
being live even when PSERIES=n. Fix it by making PSERIES_MSI depend
directly on PPC_PSERIES.
On Thu, Sep 26, 2013 at 09:51:23AM +0200, Takashi Iwai wrote:
Hi,
sorry for the lat response, as I've been traveling in the last weeks.
At Thu, 19 Sep 2013 22:53:02 +0100,
Russell King wrote:
This code sequence is unsafe in modules:
static u64 mask = DMA_BIT_MASK(something);
On Thu, 2013-09-26 at 16:31 +1000, Michael Ellerman wrote:
+ pr_info_once(registering arch random hook\n);
Either pr_debug or make it nicer looking :-)
Cheers,
Ben.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
On Thu, 2013-09-26 at 16:31 +1000, Michael Ellerman wrote:
+ pr_info(registered powernv hwrng.\n);
First letter of a line should get a capital :-) Also since
it's per-device, at least indicate the OF path or the chip number or
something ...
Cheers,
Ben.
At Thu, 26 Sep 2013 08:54:25 +0100,
Russell King - ARM Linux wrote:
On Thu, Sep 26, 2013 at 09:51:23AM +0200, Takashi Iwai wrote:
Hi,
sorry for the lat response, as I've been traveling in the last weeks.
At Thu, 19 Sep 2013 22:53:02 +0100,
Russell King wrote:
This code
The performance monitor interrupt is asynchronous, so we should check
if the current processor is in napping status in the handler of this
interrupt.
Signed-off-by: Kevin Hao haoke...@gmail.com
---
arch/powerpc/kernel/exceptions-64e.S | 1 +
1 file changed, 1 insertion(+)
diff --git
At Thu, 26 Sep 2013 10:25:13 +0200,
Takashi Iwai wrote:
At Thu, 26 Sep 2013 08:54:25 +0100,
Russell King - ARM Linux wrote:
On Thu, Sep 26, 2013 at 09:51:23AM +0200, Takashi Iwai wrote:
Hi,
sorry for the lat response, as I've been traveling in the last weeks.
At Thu, 19
We already got the value of current_thread_info and ti_flags and store
them into r9 and r4 respectively before jumping to resume_kernel. So
there is no reason to reload them again.
Signed-off-by: Kevin Hao haoke...@gmail.com
---
arch/powerpc/kernel/entry_64.S | 4 +---
1 file changed, 1
Il 26/09/2013 08:31, Michael Ellerman ha scritto:
Some powernv systems include a hwrng. Guests can access it via the
H_RANDOM hcall.
We add a real mode implementation of H_RANDOM when a hwrng is found.
Userspace can detect the presence of the hwrng by quering the
KVM_CAP_PPC_HWRNG
Subject: Re: [PATCH v2 2/6] PCI/MSI: Factor out pci_get_msi_cap() interface
On Wed, Sep 25, 2013 at 05:00:16PM -0400, Tejun Heo wrote:
Hello,
On Wed, Sep 25, 2013 at 10:58:05PM +0200, Alexander Gordeev wrote:
Unfortunately, pSeries is a shows-topper here :( It seems we have to
Hi,
after upgrading from 3.11 to 3.12-rc2, the therm_adt746x module could not
be loaded any more:
therm_adt746x: `-2' invalid for parameter `limit_adjust'
I've alwasy passed limit_adjust=-3 (negative 3) to the module via
modprobe.conf, to lower the max temperature. Up until 3.11, loading
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, September 26, 2013 7:10 AM
To: Xie Xiaobo-R63061
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Johnston Michael-
R49610
Subject: Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support
On Wed, 2013-09-25 at
From: Hongbo Zhang hongbo.zh...@freescale.com
Hi DMA and DT maintainers, please have a look at these V11 patches.
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch set
adds support this DMA engine.
V10-V11 changes:
- add contains two entries for reg description in patch
From: Hongbo Zhang hongbo.zh...@freescale.com
This patch updates the discription of each type of DMA controller and its
channels, it is preparation for adding another new DMA controller binding, it
also fixes some defects of indent for text alignment at the same time.
Signed-off-by: Hongbo Zhang
From: Hongbo Zhang hongbo.zh...@freescale.com
This patch adds support to 8-channel DMA engine, thus the driver works for both
the new 8-channel and the legacy 4-channel DMA engines.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
drivers/dma/Kconfig |9 +
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
the device tree nodes for them.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/dma.txt| 70 +
Define a QE init function in common file, and avoid
the same codes being duplicated in board files.
Signed-off-by: Xie Xiaobo x@freescale.com
---
V5 - V4: add the board files modification, remove the qe_pic_init.
V4 - V3: Nochange
arch/powerpc/platforms/85xx/common.c | 33
TWR-P1025 Overview
-
512Mbyte DDR3 (on board DDR)
64MB Nor Flash
eTSEC1: Connected to RGMII PHY AR8035
eTSEC3: Connected to RGMII PHY AR8035
Two USB2.0 Type A
One microSD Card slot
One mini-PCIe slot
One mini-USB TypeB dual UART
Signed-off-by: Michael Johnston
Hi Christian,
On Thu, 26 Sep 2013 02:16:16 -0700 (PDT), Christian Kujau wrote:
Hi,
after upgrading from 3.11 to 3.12-rc2, the therm_adt746x module could not
be loaded any more:
therm_adt746x: `-2' invalid for parameter `limit_adjust'
I've alwasy passed limit_adjust=-3 (negative 3)
On Mon, Sep 23, 2013 at 11:36:21AM +0800, Chen Gang wrote:
NO_IRQ may be defined as '(unsigned int) -1' in some architectures
(arm, sh ...), and either may not be defined in some architectures
which can enable SND_SOC_FSL_SSI (e.g. allmodconfig for arc).
Applied, thanks.
signature.asc
On 09/26/2013 06:29 PM, Mark Brown wrote:
On Mon, Sep 23, 2013 at 11:36:21AM +0800, Chen Gang wrote:
NO_IRQ may be defined as '(unsigned int) -1' in some architectures
(arm, sh ...), and either may not be defined in some architectures
which can enable SND_SOC_FSL_SSI (e.g. allmodconfig for
On Thu, Sep 26, 2013 at 09:58:53AM +0100, David Laight wrote:
Would it be possible to do some kind of 2-stage allocation.
In the first pass the driver would pass a minimum and desired
number of MSI-X interrupts, but not actually be given any.
Repeated calls to msi_enable_msi/msix() is what we
We made this change to pseries in 2011 and I think it makes
sense to do the same on powernv.
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/arch/powerpc/platforms/powernv/setup.c
===
---
On Thu, Sep 26, 2013 at 09:58:53AM +0100, David Laight wrote:
Would it be possible to do some kind of 2-stage allocation.
In the first pass the driver would pass a minimum and desired
number of MSI-X interrupts, but not actually be given any.
Repeated calls to msi_enable_msi/msix() is
On Thu, Sep 26, 2013 at 12:34:36PM +0100, David Laight wrote:
I was thinking that the first call would be done during driver probe
(assuming such a time exists) so that the subsystem could determine
how many interrupts all the drivers would like, so it can then
hand out a smaller number to
Hi,
On Friday 20 September 2013 04:41 AM, Russell King wrote:
The correct way for a driver to specify the coherent DMA mask is
not to directly access the field in the struct device, but to use
dma_set_coherent_mask(). Only arch and bus code should access this
member directly.
Convert all
On 13-09-18 05:48 AM, Alexander Gordeev wrote:
The last pattern makes most of sense to me and could be updated with a more
clear sequence - a call to (bit modified) pci_msix_table_size() followed
by a call to pci_enable_msix(). I think this pattern can effectively
supersede the currently
On Thu, Sep 26, 2013 at 08:32:53AM -0400, Mark Lord wrote:
On 13-09-18 05:48 AM, Alexander Gordeev wrote:
The last pattern makes most of sense to me and could be updated with a more
clear sequence - a call to (bit modified) pci_msix_table_size() followed
by a call to pci_enable_msix(). I
Hello,
On Thu, Sep 26, 2013 at 09:46:46AM +0200, Alexander Gordeev wrote:
Can you please go into a bit of detail on that? Why does it matter?
Because otherwise we will re-introduce a problem described by Michael:
We have a small number of MSIs available, limited by hardware
firmware, if
On Thu, Sep 26, 2013 at 09:11:47AM -0400, Tejun Heo wrote:
Because otherwise we will re-introduce a problem described by Michael:
We have a small number of MSIs available, limited by hardware
firmware, if we don't impose a quota then the first device that probes
will get most/all of the
Hello,
On Thu, Sep 26, 2013 at 10:39 AM, Alexander Gordeev agord...@redhat.com wrote:
I can imagine a scenario where the first device probes in, requests its
Well, we can imagine a lot of thing but usually have to draw the line somewhere.
optimal number, acquires that number and exhausts MSIs
On Thu, Sep 26, 2013 at 05:52:16PM +1000, Michael Ellerman wrote:
Previously PSERIES_MSI depended on PPC_PSERIES via EEH. However in
commit 317f06d powerpc/eeh: Move common part to kernel directory we
made CONFIG_EEH selectable on POWERNV. That leaves us with PSERIES_MSI
being live even when
On Thu, Sep 26, 2013 at 05:52:17PM +1000, Michael Ellerman wrote:
We currently have a user visible CONFIG_POWERNV_MSI option, but it
doesn't actually disable MSI for powernv. The MSI code is always built,
what it does disable is the inclusion of the MSI bitmap code, which
leads to a build error.
From: Rob Herring rob.herr...@calxeda.com
of_translate_dma_address is implemented in common code, so move the
declaration there too.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: Grant Likely
From: Rob Herring rob.herr...@calxeda.com
When removing prom.h include by of.h, several OF headers will no longer
be implicitly included. Add explicit includes of of_*.h as needed.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul
On Thu, 26 Sep 2013 at 11:39, Jean Delvare wrote:
I think it is a bug in:
commit 6072ddc8520b86adfac6939ca32fb6e6c4de017a
Author: Jingoo Han jg1@samsung.com
Date: Thu Sep 12 15:14:07 2013 -0700
kernel: replace strict_strto*() with kstrto*()
The change was a good idea but the
2013/9/19 Russell King - ARM Linux li...@arm.linux.org.uk:
This email is only being sent to the mailing lists in question, not to
anyone personally. The list of individuals is far to great to do that.
I'm hoping no mailing lists reject the patches based on the number of
recipients.
Huh, I
On Wed, 2013-09-25 at 22:02 -0500, Liu Shengzhou-B36685 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, September 26, 2013 9:24 AM
To: Liu Shengzhou-B36685
Cc: linuxppc-dev@lists.ozlabs.org; ga...@kernel.crashing.org
Subject: Re: [PATCH] powerpc/fsl/defconfig:
On Mon, Sep 02, 2013 at 09:55:40AM +1000, Benjamin Herrenschmidt wrote:
On Sun, 2013-09-01 at 17:24 +0100, Ben Hutchings wrote:
The original version of this was done by Bastian Blank, who wrote:
The problem is the following:
- Architecture specific code sets preferred console to
On Thu, 2013-09-26 at 04:27 -0500, Xie Xiaobo-R63061 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Thursday, September 26, 2013 7:10 AM
To: Xie Xiaobo-R63061
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Johnston Michael-
R49610
Subject: Re: [PATCH V4 3/3]
On Thu, 2013-09-26 at 01:18 -0500, Wang Dongsheng-B40534 wrote:
-Original Message-
From: Bhushan Bharat-R65777
Sent: Thursday, September 26, 2013 12:23 PM
To: Wang Dongsheng-B40534; Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
Subject: RE: [PATCH v4 4/4] powerpc/85xx:
On Thu, 2013-09-26 at 14:22 -0700, Greg Kroah-Hartman wrote:
So, I shouldn't apply this patch? We should do something to fix this,
if Debian has to drag this patch on for 5 years, that's an indication
that this might be one solution we should use, right?
Ah sorry, dropped the ball on that
On Wed, 2013-09-25 at 22:53 -0500, Bhushan Bharat-R65777 wrote:
-Original Message-
From: Alex Williamson [mailto:alex.william...@redhat.com]
Sent: Wednesday, September 25, 2013 10:10 PM
To: Bhushan Bharat-R65777
Cc: j...@8bytes.org; b...@kernel.crashing.org;
Otherwise, we get a debug traceback due to the use of
smp_processor_id() (or get_paca()) inside hard_smp_processor_id().
mpic_host_map() is just looking for a default CPU, so it doesn't matter
if we migrate after getting the CPU ID.
Signed-off-by: Scott Wood scottw...@freescale.com
---
P1010rdb-pa and p1010rdb-pb have different mtd of nand.
So update dts to adapt to both p1010rdb-pa and p1010rdb-pb.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/powerpc/boot/dts/p1010rdb-pa.dts | 40 +++
arch/powerpc/boot/dts/p1010rdb-pb.dts | 34
Hi Russell,
Thank you for the patch.
On Thursday 19 September 2013 22:56:02 Russell King wrote:
The code sequence:
isp-raw_dmamask = DMA_BIT_MASK(32);
isp-dev-dma_mask = isp-raw_dmamask;
isp-dev-coherent_dma_mask = DMA_BIT_MASK(32);
bypasses the architectures check on the
-Original Message-
From: Wood Scott-B07421
Sent: Friday, September 27, 2013 5:12 AM
To: Liu Shengzhou-B36685
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
ga...@kernel.crashing.org
Subject: Re: [PATCH] powerpc/fsl/defconfig: enable CONFIG_AT803X_PHY
On Wed, 2013-09-25
-Original Message-
From: Wood Scott-B07421
Sent: Friday, September 27, 2013 5:37 AM
To: Wang Dongsheng-B40534
Cc: Bhushan Bharat-R65777; Wood Scott-B07421; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH v4 4/4] powerpc/85xx: add sysfs for pw20 state and
altivec idle
On
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