On Mon, Sep 30, 2013 at 03:11:42PM +0200, Bartlomiej Zolnierkiewicz wrote:
__initdata tag should be placed between the variable name and equal
sign for the variable to be placed in the intended .init.data section.
I see lots of other occurences of that in arch/powerpc. Why not send a
single
On Sun, Sep 29, 2013 at 02:41:18PM +0200, Vladimir Murzin wrote:
While cross-building for PPC64 I've got bunch of
WARNING: arch/powerpc/kernel/built-in.o(.text.unlikely+0x2d2): Section
mismatch in reference from the function .free_lppacas() to the variable
.init.data:lppaca_size The function
Hi Maddy,
On Fri, Sep 27, 2013 at 05:03:54PM +0530, Madhavan Srinivasan wrote:
powerpc/kernel/sysfs.c exports purr with write permission.
PURR
This is only valid for kernel in hypervisor mode.
But writing to the file in PowerVM lpar causes crash.
In the kernel history/source we refer to it
On Tuesday 01 October 2013 10:20 AM, Michael Ellerman wrote:
On Mon, Sep 30, 2013 at 04:47:29PM +0530, Madhavan Srinivasan wrote:
Currently pmc setup macros are used for non pmc sprs. This patch
add new set of macros and cleans up the code to use the new setup macro
for non pmc sprs.
Hi
From: Paul E. McKenney paul...@linux.vnet.ibm.com
The csum_partial_copy_generic() uses register r7 to adjust the remaining
bytes to process. Unfortunately, r7 also holds a parameter, namely the
address of the flag to set in case of access exceptions while reading
the source buffer. Lacking a
From: Paul E. McKenney paul...@linux.vnet.ibm.com
The csum_partial_copy_generic() function saves the PowerPC non-volatile
r14, r15, and r16 registers for the main checksum-and-copy loop.
Unfortunately, it fails to restore them upon error exit from this loop,
which results in silent corruption of
On Tue, 1 Oct 2013 14:12:29 Michael Ellerman wrote:
On Tue, Oct 01, 2013 at 01:54:10PM +1000, Alistair Popple wrote:
This patch initialises the iommu page size used for vio, cell, powernv
and pseries platforms to 4K. It has been boot tested on a pseries
machine with vio.
This patch
On Thu, Sep 26, 2013 at 04:39:02PM +0200, Alexander Gordeev wrote:
On Thu, Sep 26, 2013 at 09:11:47AM -0400, Tejun Heo wrote:
Because otherwise we will re-introduce a problem described by Michael:
We have a small number of MSIs available, limited by hardware
firmware, if we don't impose
This reverts commit 6391f697d4892a6f233501beea553e13f7745a23. The
compiler warning it wants to fix does not appear with my gcc 4.6.2. IMO
we don't need superfluous (and here even misleading) code to make old
compilers happy. Fixing the printout was bogus, too. We want to know
WHICH critical irq
On Fri, Sep 20, 2013 at 07:26:03AM -0500, Tejun Heo wrote:
Hello,
On Wed, Sep 18, 2013 at 06:50:45PM +0200, Alexander Gordeev wrote:
Actually, I do not see much contradiction with what I proposed. The
key words here determine the number of MSIs the controller wants.
In general case it
On Wed, Sep 18, 2013 at 09:22:31AM -0500, Tejun Heo wrote:
Hello,
On Wed, Sep 18, 2013 at 11:48:00AM +0200, Alexander Gordeev wrote:
On Wed, Sep 18, 2013 at 12:30:23AM +1000, Michael Ellerman wrote:
How about no?
We have a small number of MSIs available, limited by hardware
On Tue, 2013-10-01 at 16:31 +1000, Michael Ellerman wrote:
1)Changed the test for to hypervisor mode instead of platform
I think Ben's wrong about that.
Almost all existing code uses FW_FEATURE_LPAR to differentiate
hypervisor vs guest mode, so I think we should do the same here.
I
On Wed, Sep 18, 2013 at 11:48:00AM +0200, Alexander Gordeev wrote:
On Wed, Sep 18, 2013 at 12:30:23AM +1000, Michael Ellerman wrote:
How about no?
We have a small number of MSIs available, limited by hardware
firmware, if we don't impose a quota then the first device that probes
will
On 10/01/2013 09:26 AM, Wolfram Sang wrote:
This reverts commit 6391f697d4892a6f233501beea553e13f7745a23. The
compiler warning it wants to fix does not appear with my gcc 4.6.2. IMO
we don't need superfluous (and here even misleading) code to make old
compilers happy. Fixing the printout was
On Tuesday 01 October 2013 12:01 PM, Michael Ellerman wrote:
Hi Maddy,
On Fri, Sep 27, 2013 at 05:03:54PM +0530, Madhavan Srinivasan wrote:
powerpc/kernel/sysfs.c exports purr with write permission.
PURR
This is only valid for kernel in hypervisor mode.
But writing to the file in
On Thu, Sep 26, 2013 at 06:01:27PM +1000, Benjamin Herrenschmidt wrote:
On Thu, 2013-09-26 at 16:31 +1000, Michael Ellerman wrote:
+ pr_info(registered powernv hwrng.\n);
First letter of a line should get a capital :-) Also since
it's per-device, at least indicate the OF path or the
On Thu, Sep 26, 2013 at 11:06:59AM +0200, Paolo Bonzini wrote:
Il 26/09/2013 08:31, Michael Ellerman ha scritto:
Some powernv systems include a hwrng. Guests can access it via the
H_RANDOM hcall.
Is there any reason to do this in the kernel?
It's less code, and it's faster :)
It does
On Fri, Sep 27, 2013 at 07:45:45PM +0530, Anshuman Khandual wrote:
On 09/26/2013 12:01 PM, Michael Ellerman wrote:
+int powernv_hwrng_present(void)
+{
+ return __raw_get_cpu_var(powernv_rng) != NULL;
+}
+
static unsigned long rng_whiten(struct powernv_rng *rng, unsigned long val)
On Thu, Sep 26, 2013 at 09:17:19PM +1000, Anton Blanchard wrote:
We made this change to pseries in 2011 and I think it makes
sense to do the same on powernv.
I'd vote we set it to 10s for all 64-bit machines in
arch/powerpc/kernel/setup_64.c.
cheers
On Tue, Oct 01, 2013 at 06:34:26PM +1000, Michael Ellerman wrote:
On Thu, Sep 26, 2013 at 11:06:59AM +0200, Paolo Bonzini wrote:
Il 26/09/2013 08:31, Michael Ellerman ha scritto:
Some powernv systems include a hwrng. Guests can access it via the
H_RANDOM hcall.
Is there any reason to
On Tue, Oct 01, 2013 at 05:50:30PM +1000, Benjamin Herrenschmidt wrote:
On Tue, 2013-10-01 at 16:31 +1000, Michael Ellerman wrote:
1)Changed the test for to hypervisor mode instead of platform
I think Ben's wrong about that.
Almost all existing code uses FW_FEATURE_LPAR to
Hi,
On Tue, Oct 01, 2013 at 09:54:51AM +0200, Sebastian Andrzej Siewior wrote:
On 10/01/2013 09:26 AM, Wolfram Sang wrote:
This reverts commit 6391f697d4892a6f233501beea553e13f7745a23. The
compiler warning it wants to fix does not appear with my gcc 4.6.2. IMO
we don't need superfluous
On Tue, Oct 01, 2013 at 11:39:08AM +0300, Gleb Natapov wrote:
On Tue, Oct 01, 2013 at 06:34:26PM +1000, Michael Ellerman wrote:
On Thu, Sep 26, 2013 at 11:06:59AM +0200, Paolo Bonzini wrote:
Il 26/09/2013 08:31, Michael Ellerman ha scritto:
Some powernv systems include a hwrng. Guests
Currently PMC (Performance Monitor Counter) setup macros are used
for other sprs. Since not all sprs are PMC related, this patch
modifies the exisiting macro and uses it to setup both PMC and
non PMC sprs accordingly.
V2 changes:
1) Modified SYSFS_PMCSETUP to a generic macro with additional
On Tue, 2013-10-01 at 11:39 +0300, Gleb Natapov wrote:
On Tue, Oct 01, 2013 at 06:34:26PM +1000, Michael Ellerman wrote:
On Thu, Sep 26, 2013 at 11:06:59AM +0200, Paolo Bonzini wrote:
Il 26/09/2013 08:31, Michael Ellerman ha scritto:
Some powernv systems include a hwrng. Guests can
Il 01/10/2013 10:34, Michael Ellerman ha scritto:
If you really want to have the hypercall, implementing it in QEMU means
that you can support it on all systems, in fact even when running
without KVM.
Sure, I can add a fallback to /dev/hwrng for full emulation.
The QEMU command line
On Tue, Oct 01, 2013 at 07:23:20PM +1000, Paul Mackerras wrote:
On Tue, Oct 01, 2013 at 11:39:08AM +0300, Gleb Natapov wrote:
On Tue, Oct 01, 2013 at 06:34:26PM +1000, Michael Ellerman wrote:
On Thu, Sep 26, 2013 at 11:06:59AM +0200, Paolo Bonzini wrote:
Il 26/09/2013 08:31, Michael
On 10/01/2013 11:23 AM, Paul Mackerras wrote:
On Tue, Oct 01, 2013 at 11:39:08AM +0300, Gleb Natapov wrote:
On Tue, Oct 01, 2013 at 06:34:26PM +1000, Michael Ellerman wrote:
On Thu, Sep 26, 2013 at 11:06:59AM +0200, Paolo Bonzini wrote:
Il 26/09/2013 08:31, Michael Ellerman ha scritto:
Some
On Tue, Oct 01, 2013 at 05:51:33PM +1000, Michael Ellerman wrote:
The disadvantage is that any restriction imposed on us above the quota
can only be reported as an error from pci_enable_msix().
The quota code, called from pci_get_msix_limit(), can only do so much to
interogate firmware about
Il 01/10/2013 11:38, Benjamin Herrenschmidt ha scritto:
So for the sake of that dogma you are going to make us do something that
is about 100 times slower ? (and possibly involves more lines of code)
If it's 100 times slower there is something else that's wrong. It's
most likely not 100 times
Alexander Graf ag...@suse.de writes:
On 09/30/2013 03:09 PM, Aneesh Kumar K.V wrote:
Alexander Grafag...@suse.de writes:
On 27.09.2013, at 12:52, Aneesh Kumar K.V wrote:
Aneesh Kumar K.Vaneesh.ku...@linux.vnet.ibm.com writes:
Hi All,
This patch series support enabling HV and PR KVM
On 10/01/2013 01:26 PM, Aneesh Kumar K.V wrote:
Alexander Grafag...@suse.de writes:
On 09/30/2013 03:09 PM, Aneesh Kumar K.V wrote:
Alexander Grafag...@suse.de writes:
On 27.09.2013, at 12:52, Aneesh Kumar K.V wrote:
Aneesh Kumar K.Vaneesh.ku...@linux.vnet.ibm.com writes:
Hi All,
Il 01/10/2013 13:36, Alexander Graf ha scritto:
Yes, so we should verify in the machine models that we're runnable with
the currently selected type at least, to give the user a sensible error
message.
Something like the below
I like that one a lot. Andreas, Paolo, what do you think?
Yes,
On 10/01/2013 01:36 PM, Alexander Graf wrote:
On 10/01/2013 01:26 PM, Aneesh Kumar K.V wrote:
Alexander Grafag...@suse.de writes:
On 09/30/2013 03:09 PM, Aneesh Kumar K.V wrote:
Alexander Grafag...@suse.de writes:
On 27.09.2013, at 12:52, Aneesh Kumar K.V wrote:
Aneesh Kumar
Hello,
On Tue, Oct 01, 2013 at 05:35:48PM +1000, Michael Ellerman wrote:
Roughly third of the drivers just do not care and bail out once
pci_enable_msix() has not succeeded. Not sure how many of these are
mandated by the hardware.
Yeah, I mean, this type of interface is a trap.
On Tue, Oct 01, 2013 at 02:52:28PM +1000, Michael Neuling wrote:
Well we don't have to, I think Mikey wasn't totally clear about that
making all registers volatile business :-) This is just something we
need to handle in assembly if we are going to reclaim the suspended
transaction.
On Tue, Oct 01, 2013 at 05:16:54AM -0700, Paul E. McKenney wrote:
On Tue, Oct 01, 2013 at 02:52:28PM +1000, Michael Neuling wrote:
Well we don't have to, I think Mikey wasn't totally clear about that
making all registers volatile business :-) This is just something we
need to handle in
On 10/01/2013 11:11 AM, Wolfram Sang wrote:
Hi,
Hi Wolfram,
Well, if you insist, I'd prefer the following patch.
From: Wolfram Sang w...@the-dreams.de Subject: [PATCH] ppc:
mpc52xx: silence false positive from old GCC
So people can compile with -Werror (RT patchset).
Why do you mention
So people can compile with -Werror (RT patchset).
Why do you mention the RT patch set here? Doesn't the vanila tree gets
compiled with -Werror as well?
Not for me.
irq_chip *irqchip = NULL; /* pet old compilers */
That would probably work, too. I would drop that comment but then
powerpc/kernel/sysfs.c exports PURR with write permission.
This may be valid for kernel in phyp mode. But writing to
the file in guest mode causes crash.
# echo 0 purr
cpu 0x0: Vector: 700 (Program Check) at [c0d072b0]
pc: c001770c: .write_purr+0x1c/0x40
lr:
On Mon, 2013-09-30 at 03:31 -0500, Hu Mingkai-B21284 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, September 25, 2013 3:37 AM
To: Hu Mingkai-B21284
Cc: Wood Scott-B07421; linuxppc-...@ozlabs.org
Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the
On Tue, 2013-10-01 at 08:56 +0530, Prabhakar Kushwaha wrote:
On 10/01/2013 01:17 AM, Scott Wood wrote:
On Mon, 2013-09-30 at 12:24 +0530, Prabhakar Kushwaha wrote:
- Removed l2switch. It will be added later
Why?
I am not aware of bindings required for l2switch as we are not working
Under heavy (DLPAR?) stress, we tripped this panic() in
arch/powerpc/kernel/iommu.c::iommu_init_table():
page = alloc_pages_node(nid, GFP_ATOMIC, get_order(sz));
if (!page)
panic(iommu_init_table: Can't allocate %ld bytes\n,
sz);
Before the panic() we
On Tue, 2013-10-01 at 13:19 +0200, Paolo Bonzini wrote:
Il 01/10/2013 11:38, Benjamin Herrenschmidt ha scritto:
So for the sake of that dogma you are going to make us do something that
is about 100 times slower ? (and possibly involves more lines of code)
If it's 100 times slower there is
Subject: [PATCH 0/9][v5] powerpc/perf: Export memory hierarchy level in
Power7/8.
Power7 and Power8 processors save the memory hierarchy level (eg: L2, L3)
from which a load or store instruction was satisfied. Export this hierarchy
information to the user via the perf_mem_data_src object.
Export generic perf events for Power8 in sysfs.
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Reviewed-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c | 23 +++
1 file changed, 23 insertions(+)
diff --git
The logic used in branch_opcode() to extract the opcode for an instruction
applies to non branch instructions also. So rename to instr_opcode().
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Reviewed-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
We use helpers like GENERIC_EVENT_ATTR() to list the generic events in
sysfs. To avoid name collisions, GENERIC_EVENT_ATTR() requires the perf
event macros to start with PME.
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Reviewed-by: Anshuman Khandual khand...@linux.vnet.ibm.com
Add a few lines to the perf-mem man page to indicate:
- its dependence on the mem-loads and mem-stores events
- how to use the feature on Power architecture.
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
---
tools/perf/Documentation/perf-mem.txt | 11
On Power8, the LDST field in SIER identifies the memory hierarchy level
(eg: L1, L2 etc), from which a data-cache miss for a marked instruction
was satisfied.
Use the 'perf_mem_data_src' object to export this hierarchy level to user
space. Fortunately, the memory hierarchy levels in Power8 map
perf_mem_data_src is an union that is initialized via the -val field
and accessed via the bitmap fields. For this to work on big endian
platforms, we also need a big-endian represenation of perf_mem_data_src.
Cc: Stephane Eranian eran...@google.com
Cc: Michael Ellerman mich...@ellerman.id.au
On Power7, the DCACHE_SRC field in MMCRA register identifies the memory
hierarchy level (eg: L2, L3 etc) from which a data-cache miss for a
marked instruction was satisfied.
Use the 'perf_mem_data_src' object to export this hierarchy level to user
space. Some memory hierarchy levels in Power7
The perf event PM_MRK_GRP_CMPL is useful in analyzing memory hierarchy
of applications.
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Reviewed-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/perf/power8-pmu.c |5 +
1 file changed, 5 insertions(+)
diff
Implement is_instr_load_store() to detect whether a given instruction
is one of the fixed-point or floating-point load/store instructions.
This function will be used in a follow-on patch to save memory hierarchy
information of the load/store.
Signed-off-by: Sukadev Bhattiprolu
Convert the memset/memcpy uses of 6 to ETH_ALEN
where appropriate.
Also convert some struct definitions and u8 array
declarations of [6] to ETH_ALEN.
Signed-off-by: Joe Perches j...@perches.com
---
drivers/net/ethernet/8390/ax88796.c| 2 +-
drivers/net/ethernet/amd/atarilance.c
On Tue, Oct 01, 2013 at 07:55:03AM -0400, Tejun Heo wrote:
Hello,
On Tue, Oct 01, 2013 at 05:35:48PM +1000, Michael Ellerman wrote:
Roughly third of the drivers just do not care and bail out once
pci_enable_msix() has not succeeded. Not sure how many of these are
mandated by the
On Tue, Oct 01, 2013 at 12:35:27PM +0200, Alexander Gordeev wrote:
On Tue, Oct 01, 2013 at 05:51:33PM +1000, Michael Ellerman wrote:
The disadvantage is that any restriction imposed on us above the quota
can only be reported as an error from pci_enable_msix().
The quota code, called from
On 13-09-26 09:03 AM, Alexander Gordeev wrote:
On Thu, Sep 26, 2013 at 08:32:53AM -0400, Mark Lord wrote:
On 13-09-18 05:48 AM, Alexander Gordeev wrote:
The last pattern makes most of sense to me and could be updated with a more
clear sequence - a call to (bit modified) pci_msix_table_size()
On Wed, Oct 02, 2013 at 12:33:38PM +1000, Michael Ellerman wrote:
It is an interface which forces the driver writers to write
complicated fallback code which won't usually be excercised.
It does not force anyone to do anything. That's just bull.
Yeah, sure, we don't have shitty code in
On Tue, Oct 01, 2013 at 01:19:06PM +0200, Paolo Bonzini wrote:
Anyhow, I would like to know more about this hwrng and hypercall.
Does the hwrng return random numbers (like rdrand) or real entropy (like
rdseed that Intel will add in Broadwell)? What about the hypercall?
Well, firstly, your
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