On 11/08/2013 10:45 AM, Dan Williams wrote:
On Mon, Nov 4, 2013 at 6:31 PM, Hongbo Zhang hongbo.zh...@freescale.com wrote:
Hi Vinod Koul and Dan Williams,
Ping?
Not much to review from the dmaengine side, just one question below.
It would be helpful if you can send these to the new dmaengine
From: Hongbo Zhang hongbo.zh...@freescale.com
This patch updates the discription of each type of DMA controller and its
channels, it is preparation for adding another new DMA controller binding, it
also fixes some defects of indent for text alignment at the same time.
Signed-off-by: Hongbo Zhang
From: Hongbo Zhang hongbo.zh...@freescale.com
Hi Dan Williams and Vinod Koul,
This time only resend all patches to the new dmaengine patchwork at
dmaengine(at)vger.kernel.org as Dan Williams suggested.
Patch 1/3 and 2/3 have been Acked-by: Mark Rutland mark.rutl...@arm.com
after several
From: Tang Yuantian yuantian.t...@freescale.com
Adds the clock bindings for Freescale PowerPC CoreNet platforms
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
v6:
- splited the previous patch into 2 parts, one is for binding(this
From: Hongbo Zhang hongbo.zh...@freescale.com
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
the device tree nodes for them.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
Acked-by: Mark Rutland mark.rutl...@arm.com
---
From: Hongbo Zhang hongbo.zh...@freescale.com
This patch adds support to 8-channel DMA engine, thus the driver works for both
the new 8-channel and the legacy 4-channel DMA engines.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
---
drivers/dma/Kconfig |9 +
On 11/9/2013 1:17 AM, Lijun Pan wrote:
diff --git a/arch/powerpc/configs/mpc85xx_defconfig
b/arch/powerpc/configs/mpc85xx_defconfig
index d2e0fab..72fff6e 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -1,4 +1,5 @@
CONFIG_PPC_85xx=y
On Mon, Nov 11, 2013 at 09:41:46AM +, yuantian.t...@freescale.com wrote:
From: Tang Yuantian yuantian.t...@freescale.com
Adds the clock bindings for Freescale PowerPC CoreNet platforms
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We don't use PACATOC for PR. Avoid updating HOST_R2 with PR
KVM mode when both HV and PR are enabled in the kernel. Without this we
get the below crash
(qemu)
Unable to handle kernel paging request for data at address 0x8310
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
NOTE: I am not sure why we were originally computing dsisr and dar. So may be
we need a variant of this patch. But with this and the
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch make sure we inherit the LE bit correctly in different case
so that we can run Little Endian distro in PR mode
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
This patch depends on the below two changes
1)
Ping. I haven't seen any comments on any of these patches.
--
Joseph S. Myers
jos...@codesourcery.com
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mpc85xx_smp_defconfig and mpc85xx_defconfig already have CONFIG_P1023RDS=y.
Merge CONFIG_P1023RDB=y and other relevant configurations into
mpc85xx_smp_defconfig and mpc85_defconfig.
Signed-off-by: Lijun Pan lijun@freescale.com
---
arch/powerpc/configs/85xx/p1023_defconfig | 188
[ dropping devicetree@vger from CC ]
On Fri, Nov 01, 2013 at 11:04 +0100, Anatolij Gustschin wrote:
On Fri, 1 Nov 2013 11:19:30 +0400
Alexander Popov a13xp0p0...@gmail.com wrote:
Concentrate the specific code for MPC8308 in the 'if' branch
and handle MPC512x in the 'else' branch.
On Fri, Nov 01, 2013 at 11:19 +0400, Alexander Popov wrote:
Introduce support for slave s/g transfer preparation and the associated
device control callback in the MPC512x DMA controller driver, which adds
support for data transfers between memory and peripheral I/O to the
previously
On Mon, 11 Nov 2013, pegasus wrote:
And this is due to the pipelining feature that is inherent in all
processors.
No, it has nothing to do with pipelining at all. It is just the
convention that IBM defined as to how the branch taken exception works
in BookE Power ISA. The pipeline
From: Andy Fleming
You need an extra parameter to read or write Clause 45 PHYs, so
we need a different API with the extra parameter.
Signed-off-by: Andy Fleming
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
include/linux/phy.h | 33 +
1 file changed,
From: Andy Fleming
Very incomplete, but will allow for binding an ethernet controller
to it.
Also, Add XGMII interface type
Signed-off-by: Andy Fleming
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
drivers/net/phy/phy_device.c | 101 ++-
From: Andy Fleming
phy_attach_direct() may now attach to a generic 10G driver. It can
also be used exactly as phy_connect_direct(), which will be useful
when using of_mdio, as phy_connect (and therefore of_phy_connect)
start the PHY state machine, which is currently irrelevant for 10G
PHYs.
From: Andy Fleming
10G PHYs don't currently support running the state machine, which
is implicitly setup via of_phy_connect(). Therefore, it is necessary
to implement an OF version of phy_attach(), which does everything
except start the state machine.
Signed-off-by: Andy Fleming
Signed-off-by:
These lines were inoperative for four years, which puts some doubt into
their importance, and it's possible the fixed version will regress, but
at the very least they should be removed instead.
Signed-off-by: Adam Borowski kilob...@angband.pl
---
arch/powerpc/boot/dts/xcalibur1501.dts | 4 ++--
On Sat, 2013-11-09 at 14:43 +0800, Kevin Hao wrote:
On Fri, Nov 08, 2013 at 03:16:12PM -0600, Scott Wood wrote:
OK... Why are you splitting out smp_85xx_basic_setup()?
In the current implementation of smp_85xx_setup_cpu(), we only invoke
the function mpic_setup_this_cpu() when the
On Mon, Nov 11, 2013 at 1:12 AM, Hongbo Zhang
hongbo.zh...@freescale.com wrote:
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 49e8fbd..16a9a48 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -1261,7 +1261,9 @@ static int fsl_dma_chan_probe(struct
Hi Linus !
Now that you've proven that even a typhoon can't get you, let's start
throwing code at you again !
The bulk of this is LE updates. One should now be able to build an
LE kernel and even run some things in it.
I'm still sitting on a handful of patches to enable the new ABI that
I
+++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
@@ -0,0 +1,123 @@
+* Clock Block on Freescale CoreNet Platforms
+
+Freescale CoreNet chips take primary clocking input from the external
+SYSCLK signal. The SYSCLK input (frequency) is multiplied using
+multiple phase
On Sun, Nov 10, 2013 at 11:35:43PM -0600, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
Commit b5b4bb3f6a11f9 (of: only include prom.h on sparc) removed implicit
includes of of_*.h headers by powerpc's prom.h. Some PPC4xx components
were missed in initial clean-up patch, so
On Mon, Oct 28, 2013 at 05:58:42AM +, Xiubo Li-B47053 wrote:
Hi Dan, Vinod,
+static int fsl_sai_probe(struct platform_device *pdev) {
[...]
+
+ sai-dma_params_rx.addr = res-start + SAI_RDR;
+ sai-dma_params_rx.maxburst = 6;
+ index = of_property_match_string(np,
On PHB3, we will fail to fetch IODA tables without PCI_COMMAND_MASTER
on PCI bridges. According to one experiment I had, the MSIx interrupts
didn't raise from the adapter without the bit applied to all upstream
PCI bridges including root port of the adapter. The patch forces to
have that bit
We possibly has fenced PHB except frozen PE. So the output log
doesn't cover all cases and the patch fixes it.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/kernel/eeh_event.c |9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git
On 11/12/2013 08:09 AM, Dan Williams wrote:
On Mon, Nov 11, 2013 at 1:12 AM, Hongbo Zhang
hongbo.zh...@freescale.com wrote:
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 49e8fbd..16a9a48 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -1261,7 +1261,9 @@ static
+static int fsl_sai_probe(struct platform_device *pdev) {
[...]
+
+ sai-dma_params_rx.addr = res-start + SAI_RDR;
+ sai-dma_params_rx.maxburst = 6;
+ index = of_property_match_string(np, dma-names, rx);
+ ret = of_parse_phandle_with_args(np, dmas,
I re-read the link you posted earlier and this time it made more sense to me.
The kind of questions which are coming into my mind were being discussed.
So, off I went and downloaded the latest version of
arch/powerpc/kernel/traps.c hoping to see those very changes in them.
However it didn't match
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