From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
arch/powerpc/platforms/wsp/wsp.c: In function ‘wsp_probe_devices’:
arch/powerpc/platforms/wsp/wsp.c:76:3: error: implicit declaration of function
‘of_address_to_resource’ [-Werror=implicit-function-declaration]
Signed-off-by: Aneesh Kumar
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Even though we have same value for linux PTE bits and hash PTE pits
use the hash pte bits wen updating hash pte
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/platforms/cell/beat_htab.c | 4 ++--
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We want to make sure we don't use these function when updating a pte
or pmd entry that have a valid hpte entry, because these functions
don't invalidate them. So limit the check to _PAGE_PRESENT bit.
Numafault core changes use these functions
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
change_prot_numa should work even if _PAGE_NUMA != _PAGE_PROTNONE.
On archs like ppc64 that don't use _PAGE_PROTNONE and also have
a separate page table outside linux pagetable, we just need to
make sure that when calling change_prot_numa we
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Set memory coherence always on hash64 config. If
a platform cannot have memory coherence always set they
can infer that from _PAGE_NO_CACHE and _PAGE_WRITETHRU
like in lpar. So we dont' really need a separate bit
for tracking
Hi,
This patch series add support for numa faults on ppc64 architecture. We steal
the
_PAGE_COHERENCE bit and use that for indicating _PAGE_NUMA. We clear the
_PAGE_PRESENT bit
and also invalidate the hpte entry on setting _PAGE_NUMA. The next fault on that
page will be considered a numa fault.
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We steal the _PAGE_COHERENCE bit and use that for indicating NUMA ptes.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pgtable.h | 66 +-
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
Opal now has a new messaging infrastructure to push the messages to
linux in a generic format for different type of messages using only one
event bit. The format of the opal message is as below:
struct opal_msg {
uint32_t msg_type;
On 11/16/2013 04:32 PM, Russell King - ARM Linux wrote:
On Fri, Nov 15, 2013 at 05:16:55PM +0100, Cedric Le Goater wrote:
The new helper routine dma_set_mask_and_coherent() breaks the
initialization of the pseries vio devices which do not have an
initial dev-dma_mask. I think we need to use
Commit 4886c399da70d5f8a4016c2213850dce6cac88c5 (DMA-API: ppc: vio.c:
replace dma_set_mask()+dma_set_coherent_mask() with new helper)
introduced the usage of the new helper routine dma_set_mask_and_coherent().
This breaks the initialization of the pseries vio devices which do not
setup an
Move SG list and entry structure to header file so that
it can be used in other places as well.
Signed-off-by: Vasant Hegde hegdevas...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/opal.h | 22 +++
arch/powerpc/platforms/powernv/opal-flash.c | 31
This patch adds Platform dump retrieval interface.
Flow:
- We register to OPAL notification event.
- OPAL sends new dump available notification.
- We retrieve the dump and send it to debugfs.
- User copies the dump data and end ACKs via debugfs.
- We send ACK to OPAL.
debugfs files:
Update dump README file content.
Signed-off-by: Vasant Hegde hegdevas...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/opal-dump.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/opal-dump.c
On 10/23/2013 05:31 PM, Tiejun Chen wrote:
Scott,
Tested on fsl-p5040 DS.
Scott,
Any comments to this version?
Tiejun
v6:
* rebase
* change the C code to initialize the exception stack addresses in the PACA
instead.
* Clear the PACA_IRQ_HARD_DIS force to exit directly from this debug
On Fri, Nov 01, 2013 at 07:19:33AM +, Alexander Popov wrote:
From: Gerhard Sittig g...@denx.de
register the controller for device tree based lookup of DMA channels
(non-fatal for backwards compatibility with older device trees), provide
the '#dma-cells' property in the shared
On Monday 18 November 2013, Mark Rutland wrote:
+++ b/Documentation/devicetree/bindings/dma/mpc512x-dma.txt
@@ -0,0 +1,55 @@
+* Freescale MPC512x DMA Controller
+
+The DMA controller in the Freescale MPC512x SoC can move blocks of
+memory contents between memory and peripherals or
Ping^2. I still haven't seen any comments on any of these patches.
--
Joseph S. Myers
jos...@codesourcery.com
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On Mon, Nov 18, 2013 at 02:31:54PM +, Arnd Bergmann wrote:
On Monday 18 November 2013, Mark Rutland wrote:
+++ b/Documentation/devicetree/bindings/dma/mpc512x-dma.txt
@@ -0,0 +1,55 @@
+* Freescale MPC512x DMA Controller
+
+The DMA controller in the Freescale MPC512x SoC can
On Mon, 2013-11-18 at 14:54 +, Joseph S. Myers wrote:
Ping^2. I still haven't seen any comments on any of these patches.
Sorry for the delay -- I plan to take a look at them, but they came in
too late for the last pull request, especially since I'm not that
familiar with SPE and thus
On Mon, 2013-11-18 at 17:21 +1100, Alistair Popple wrote:
The kernel doesn't build correctly using the ELFv2 ABI. This patch
ensures that the ELFv1 ABI is used when building a kernel with an
ELFv2 enabled compiler.
Signed-off-by: Alistair Popple alist...@popple.id.au
---
On Thu, 2013-11-14 at 21:16 -0600, Sethi Varun-B16395 wrote:
Haiying/Scott,
Forgot to mention this, the PAMU driver has to handle stash destination
settings both for power and dsp cores (on B4 platform). For the dsp
cores we would expect the physical core id (not controlled by Linux).
To make
On 17.11.2013, at 20:09, Liu Ping Fan qemul...@gmail.com wrote:
In some scene, e.g openstack CI, PR guest can trigger sc 1 frequently,
this patch optimizes the path by directly delivering BOOK3S_INTERRUPT_SYSCALL
to HV guest, so powernv can return to HV guest without heavy exit, i.e,
no need
On 16.11.2013, at 01:55, Paul Mackerras pau...@samba.org wrote:
On Fri, Nov 15, 2013 at 04:35:00PM +0800, Liu Ping Fan wrote:
Since kvmppc_hv_find_lock_hpte() is called from both virtmode and
realmode, so it can trigger the deadlock.
Suppose the following scene:
Two physical cpuM, cpuN,
On 18.11.2013, at 16:32, Alexander Graf ag...@suse.de wrote:
On 16.11.2013, at 01:55, Paul Mackerras pau...@samba.org wrote:
On Fri, Nov 15, 2013 at 04:35:00PM +0800, Liu Ping Fan wrote:
Since kvmppc_hv_find_lock_hpte() is called from both virtmode and
realmode, so it can trigger the
On Mon, 18 Nov 2013 13:29:25 Scott Wood wrote:
On Mon, 2013-11-18 at 17:21 +1100, Alistair Popple wrote:
[snip]
How hard would it be to get the kernel to work with the new ABI?
We are preparing patches at the moment to allow the kernel to support a
userspace compiled with the new ABI,
For the DSP case again we have to set up the stash attribute. Are you saying
that this should be a separate attribute?
-Varun
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, November 19, 2013 1:07 AM
To: Sethi Varun-B16395
Cc: Wang Haiying-R54964; j...@8bytes.org;
On Mon, 2013-11-18 at 20:42 -0600, Varun Sethi wrote:
For the DSP case again we have to set up the stash attribute. Are you saying
that this should be a separate attribute?
Not necessarily a separate attribute, but there should be some way to
distinguish whether you're providing a Linux cpu
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, November 19, 2013 8:34 AM
To: Sethi Varun-B16395
Cc: Wang Haiying-R54964; j...@8bytes.org; iommu@lists.linux-
foundation.org; linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] iommu/fsl_pamu: use physical cpu index to find
On Mon, Nov 18, 2013 at 05:21:34PM +1100, Alistair Popple wrote:
The kernel doesn't build correctly using the ELFv2 ABI. This patch
ensures that the ELFv1 ABI is used when building a kernel with an
ELFv2 enabled compiler.
Let me check I've got this straight.
The ELFv2 ABI is still being
On Fri, Nov 15, 2013 at 03:36:04PM +0800, Li Zhong wrote:
This is seen when CONFIG_SMP is not enabled:
arch/powerpc/platforms/powernv/rng.c: In function 'rng_init_per_cpu':
arch/powerpc/platforms/powernv/rng.c:74: error: implicit declaration of
function 'cpu_to_chip_id'
Hi Li,
We try
On Tue, 19 Nov 2013 14:25:53 Michael Ellerman wrote:
On Mon, Nov 18, 2013 at 05:21:34PM +1100, Alistair Popple wrote:
The kernel doesn't build correctly using the ELFv2 ABI. This patch
ensures that the ELFv1 ABI is used when building a kernel with an
ELFv2 enabled compiler.
Let me check
From: Bharat Bhushan bharat.bhus...@freescale.com
PAMU (FSL IOMMU) has a concept of primary window and subwindows.
Primary window corresponds to the complete guest iova address space
(including MSI space), with respect to IOMMU_API this is termed as
geometry. IOVA Base of subwindow is determined
So by now we have defined all the interfaces for getting the msi region,
this patch expose the interface to linux subsystem. These will be used by
vfio subsystem for setting up iommu for MSI interrupt of direct assignment
devices.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
In Aperture type of IOMMU (like FSL PAMU), VFIO-iommu system need to know
the MSI region to map its window in h/w. This patch just defines the
required weak functions only and will be used by followup patches.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v1-v2
- Added
This patch adds the interface to get the msi region information from arch
specific code. The machine spicific code is not yet defined.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v1-v2
- None
arch/powerpc/include/asm/machdep.h |8
arch/powerpc/kernel/msi.c
The FSL MSI will provide the interface to get:
- Number of MSI regions (which is number of MSI banks for powerpc)
- Get the region address range: Physical page which have the
address/addresses used for generating MSI interrupt
and size of the page.
These are required to create IOMMU
This patch defines an interface by which a msi page
can be mapped to a specific iova page.
This is a requirement in aperture type of IOMMUs (like Freescale PAMU),
where we map msi iova page just after guest memory iova address.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2
-
This patch extend the interface to arch specific code for setting
msi iova address for a msi page. Machine specific code is not yet
implemented.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v2
- new patch
arch/powerpc/include/asm/machdep.h |2 ++
arch/powerpc/kernel/msi.c
Now we Keep track of devices which have msi page mapping to specific
iova page for all msi bank. When composing MSI address and data then
this list will be traversed. If device found in the list then use
configured iova page otherwise iova page will be taken as before.
Signed-off-by: Bharat
Some function defined in vfio_iommu_type1.c are generic (not specific
or type1 iommu) and we want to use these for FSL IOMMU (PAMU) and
going forward in iommu-none driver.
So I have created a new file naming vfio_iommu_common.c and moved some
of generic functions into this file.
I Agree (with
This patch adds vfio iommu support for Freescale IOMMU (PAMU -
Peripheral Access Management Unit).
The Freescale PAMU is an aperture-based IOMMU with the following
characteristics. Each device has an entry in a table in memory
describing the iova-phys mapping. The mapping has:
-an overall
Since kvmppc_hv_find_lock_hpte() is called from both virtmode and
realmode, so it can trigger the deadlock.
Suppose the following scene:
Two physical cpuM, cpuN, two VM instances A, B, each VM has a group of
vcpus.
If on cpuM, vcpu_A_1 holds bitlock X (HPTE_V_HVLOCK), then is switched
out, and
In some scene, e.g openstack CI, PR guest can trigger sc 1 frequently,
this patch optimizes the path by directly delivering BOOK3S_INTERRUPT_SYSCALL
to HV guest, so powernv can return to HV guest without heavy exit, i.e,
no need to swap TLB, HTAB,.. etc
Signed-off-by: Liu Ping Fan
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