For allocating resource under bus path, we do not have dev to pass along,
and we only have bus to use instead.
-v2: drop pcibios_bus_addr_to_resource().
-v3: drop __* change requested by Bjorn.
Signed-off-by: Yinghai Lu ying...@kernel.org
Cc: linux-al...@vger.kernel.org
Cc:
-Original Message-
From: Alex Williamson [mailto:alex.william...@redhat.com]
Sent: Tuesday, December 10, 2013 11:23 AM
To: Bhushan Bharat-R65777
Cc: Wood Scott-B07421; linux-...@vger.kernel.org; ag...@suse.de; Yoder Stuart-
B08248; io...@lists.linux-foundation.org;
the 'soc' node in the MPC5125 tower board .dts has an '#interrupt-cells'
property although this node is not an interrupt controller
remove this erroneously placed property because starting with v3.13-rc1
lookup and resolution of 'interrupts' specs for peripherals gets misled
(tries to use the
[ Cc: to Matteo as well ]
On Tue, Dec 03, 2013 at 15:04 +0100, Anatolij Gustschin wrote:
On Tue, 3 Dec 2013 11:56:52 +0100
Gerhard Sittig g...@denx.de wrote:
the 'soc' node in the common .dtsi for MPC5121 has an '#interrupt-cells'
property although this node is not an interrupt
Scott,
This issue is due to the non-continuous MPIC register, I think there is
two ways to fix it.
The first one is as what we are discussing, in fact the Bman/Qman DT
author had introduced this way, and I had to follow it, it is a trick,
adding 208 is a bit ugly I think, and even difficult
On Tue, Dec 10, 2013 at 11:05 +0100, Gerhard Sittig wrote:
FYI: I only noticed yesterday that MPC5125 suffers from the same
issue, have sent 1386669068-2477-1-git-send-email-...@denx.de
to fix that as well. Both patches may get squashed when going
upstream. Don't have a dump at hand for
On Tue, 2013-12-10 at 18:33 +0800, Hongbo Zhang wrote:
Scott,
This issue is due to the non-continuous MPIC register, I think there is
two ways to fix it.
The first one is as what we are discussing, in fact the Bman/Qman DT
author had introduced this way, and I had to follow it, it is a
On Tue, 2013-12-10 at 12:29 +0100, Christophe Leroy wrote:
Today, the only way to load kernels whose size is greater than 8Mbytes is to
activate CONFIG_PIN_TLB. Otherwise, the physical memory initially mapped is
limited to 8Mbytes. This patch adds the capability to select the size of
initial
[ trimmed Cc: list to PowerPC and CCF ]
On Sat, Nov 30, 2013 at 23:51 +0100, Gerhard Sittig wrote:
this series introduces support for the common clock framework (CCF,
COMMON_CLK Kconfig option) in the PowerPC based MPC512x platform,
which brings device tree based clock lookup as well
For
On Mon, Dec 9, 2013 at 8:59 PM, Benjamin Herrenschmidt b...@au1.ibm.com wrote:
On Mon, 2013-12-09 at 17:01 -0700, Bjorn Helgaas wrote:
[+cc arch lists]
On Thu, Dec 05, 2013 at 07:52:53PM +0800, Yijing Wang wrote:
Use dev_is_pci() instead of directly compare
pci_bus_type to check whether it
My e-mail address is scottw...@freescale.com, not
IMCEAEX-_O=MMS_OU=EXTERNAL+20+28FYDIBOHF25SPDLT
+29_CN=RECIPIENTS_CN=f0faac8d7e74473a9ee1c45b068d8...@namprd03.prod.outlook.com
On Tue, 2013-12-10 at 05:37 +, bharat.bhus...@freescale.com wrote:
-Original Message-
From: Wood
On Wed, Dec 11, 2013 at 07:52:51AM +1100, Benjamin Herrenschmidt wrote:
On Tue, 2013-12-10 at 15:40 +0100, Alexander Graf wrote:
On 10.12.2013, at 15:21, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We already
the SDHC clock is derived from CSB with a fractional divider which can
address quarters; the implementation multiplies CSB by 4 and divides
it by the (integer) divider value
a bug in the clock domain synchronisation requires that only even
divider values get setup; we achieve this by
-
On 10.12.2013, at 17:08, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
Alexander Graf ag...@suse.de writes:
On 10.12.2013, at 15:21, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We already checked
On 10.12.2013, at 15:21, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We already checked need_resched. So we can call schedule directly
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
The real fix for the
On Tue, 2013-12-10 at 23:48 +0100, Peter Zijlstra wrote:
Yeah, I went on holidays and the patch just sat there. I'll prod Ingo
into merging it.
Thanks !
Cheers,
Ben.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
Le 10/12/2013 23:24, Scott Wood a écrit :
On Tue, 2013-12-10 at 12:29 +0100, Christophe Leroy wrote:
Today, the only way to load kernels whose size is greater than 8Mbytes is to
activate CONFIG_PIN_TLB. Otherwise, the physical memory initially mapped is
limited to 8Mbytes. This patch adds the
From: Joseph Myers jos...@codesourcery.com
The e500 SPE floating-point emulation code clears existing exceptions
(__FPU_FPSCR = ~FP_EX_MASK;) before ORing in the exceptions from the
emulated operation. However, these exception bits are the sticky,
cumulative exception bits, and should only be
On Tue, 2013-12-10 at 15:40 +0100, Alexander Graf wrote:
On 10.12.2013, at 15:21, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We already checked need_resched. So we can call schedule directly
Signed-off-by: Aneesh
add clock related specs to the MPC5125 tower board DTS
- add clock providers (crystal/oscillator, clock control module)
- add consumers (the CAN, SDHC, I2C, DIU, FEC, USB, PSC peripherals)
Signed-off-by: Gerhard Sittig g...@denx.de
---
arch/powerpc/boot/dts/mpc5125twr.dts | 53
Hi Mark,
Is there some reason you've excluded OpenRISC here? Did you just miss
it, or does the implementation diverage too much to be usable with
your generic version?
Regards,
Jonas
On 25 November 2013 17:13, Mark Salter msal...@redhat.com wrote:
Many architectures provide an asm/fixmap.h
On Wed, 2013-12-11 at 00:05 +0100, leroy christophe wrote:
Le 10/12/2013 23:24, Scott Wood a écrit :
On Tue, 2013-12-10 at 12:29 +0100, Christophe Leroy wrote:
Today, the only way to load kernels whose size is greater than 8Mbytes is
to
activate CONFIG_PIN_TLB. Otherwise, the physical
Le 11/12/2013 00:18, Scott Wood a écrit :
On Wed, 2013-12-11 at 00:05 +0100, leroy christophe wrote:
Le 10/12/2013 23:24, Scott Wood a écrit :
On Tue, 2013-12-10 at 12:29 +0100, Christophe Leroy wrote:
Today, the only way to load kernels whose size is greater than 8Mbytes is to
activate
improve the common clock support code for MPC512x
- expand the CCM register set declaration with MPC5125 related registers
(which reside in the previously reserved area)
- tell the MPC5121, MPC5123, and MPC5125 SoC variants apart, and derive
the availability of components and their clocks
this series improves the previously introduced common clock support for
MPC512x such that SoC variants 5123 and 5125 get addressed appropriately
(MPC5125 turned out to be rather different from MPC5121 than I perceived
before -- there is much more than just two FECs and no MBX)
thus this series
adjust (expand on or move) a few comments,
add markers for easier navigation around helpers
Signed-off-by: Gerhard Sittig g...@denx.de
---
arch/powerpc/platforms/512x/clock-commonclk.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We already checked need_resched. So we can call schedule directly
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
NOTE: This patch also work around a regression upstream w.r.t PR KVM
BUG: soft lockup - CPU#0 stuck for
Today, the only way to load kernels whose size is greater than 8Mbytes is to
activate CONFIG_PIN_TLB. Otherwise, the physical memory initially mapped is
limited to 8Mbytes. This patch adds the capability to select the size of initial
memory between 8/16/24 Mbytes and this is regardless of whether
Alexander Graf ag...@suse.de writes:
On 10.12.2013, at 15:21, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
We already checked need_resched. So we can call schedule directly
Signed-off-by: Aneesh Kumar K.V
On Thu, Oct 31, 2013 at 01:38:58PM -0500, Tom wrote:
From: Tom Musta tommu...@gmail.com
This patch addresses unaligned single precision floating point loads
and stores in the single-step code. The old implementation
improperly treated an 8 byte structure as an array of two 4 byte
words,
On Wed, Dec 11, 2013 at 02:54:40PM +1100, Paul Mackerras wrote:
On Thu, Oct 31, 2013 at 01:38:58PM -0500, Tom wrote:
From: Tom Musta tommu...@gmail.com
This patch addresses unaligned single precision floating point loads
and stores in the single-step code. The old implementation
On Tue, 2013-12-10 at 08:39 +0100, Philippe Bergheaud wrote:
All the important PThread locking occurs in GLIBC libpthread.so
For scaling to large core counts we need to stay out of the kernel and
scheduler as much as possible which implies increasing the spin time in user
mode. For POWER
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