As Freescale IFC controller has been moved to driver to driver/memory.
So enable memory driver in powerpc config
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
Branch next
Changes for v2: Sending as it
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/memory
and fix the header file includes.
Also remove module_platform_driver() and instead call
platform_driver_register() from subsys_initcall() to make sure
From: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
This patch fix the below crash
NIP [c004cee4] .__hash_page_thp+0x2a4/0x440
LR [c00439ac] .hash_page+0x18c/0x5e0
...
Call Trace:
[c00736103c40] [1b00] 0x1b00(unreliable)
[437908.479693]
From: Li Zhong zh...@linux.vnet.ibm.com
It seems that forward declaration couldn't work well with typedef, use
struct spinlock directly to avoiding following build errors:
In file included from include/linux/spinlock.h:81,
from include/linux/seqlock.h:35,
from
Alexander Graf ag...@suse.de writes:
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
We definitely don't need to emulate mtspr, because both the registers
are hypervisor resource.
This patch description doesn't cover what the patch actually does. It
changes the implementation from always
On 31.01.2014, at 11:38, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
Alexander Graf ag...@suse.de writes:
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
We definitely don't need to emulate mtspr, because both the registers
are hypervisor resource.
This patch description
Paul Mackerras pau...@samba.org writes:
On Tue, Jan 28, 2014 at 10:14:07PM +0530, Aneesh Kumar K.V wrote:
virtual time base register is a per vm register and need to saved
and restored on vm exit and entry. Writing to VTB is not allowed
in the privileged mode.
...
+#ifdef
Alexander Graf ag...@suse.de writes:
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
Writing to IC is not allowed in the privileged mode.
This is not a patch description.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/kvm_host.h | 1 +
On 31.01.2014, at 12:25, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
Alexander Graf ag...@suse.de writes:
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
Writing to IC is not allowed in the privileged mode.
This is not a patch description.
Signed-off-by: Aneesh Kumar
Paul Mackerras pau...@samba.org writes:
On Tue, Jan 28, 2014 at 10:14:12PM +0530, Aneesh Kumar K.V wrote:
We allow priv-mode update of this. The guest value is saved in fscr,
and the value actually used is saved in shadow_fscr. shadow_fscr
only contains values that are allowed by the host. On
Alexander Graf ag...@suse.de writes:
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
At this point we allow all the supported facilities except EBB. So
forward the interrupt to guest as illegal instruction.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
On 31.01.2014, at 12:40, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
Alexander Graf ag...@suse.de writes:
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
At this point we allow all the supported facilities except EBB. So
forward the interrupt to guest as illegal instruction.
On 01/17/2014 11:56 AM, Kleber Sacilotto de Souza wrote:
These two patches fix problems on the PCI-E link speed detection.
The first one fixes a regression and adds some improvements on the
code, and the second one adds definitions for Gen3 speeds.
Kleber Sacilotto de Souza (2):
On Fri, 2014-01-31 at 10:20 -0200, Kleber Sacilotto de Souza wrote:
On 01/17/2014 11:56 AM, Kleber Sacilotto de Souza wrote:
These two patches fix problems on the PCI-E link speed detection.
The first one fixes a regression and adds some improvements on the
code, and the second one adds
On Thu, Jan 30, 2014 at 12:20:21PM +, Moese, Michael wrote:
Hello PPC-developers,
I'm currently trying to benchmark access speeds to our PCIe-connected IP-cores
located inside our FPGA. On x86-based systems I was able to achieve bursts for
both read and write access. On PPC32, using an
On Jan 29, 2014, at 8:38 PM, Michael Ellerman m...@ellerman.id.au wrote:
This patch adds some documentation on the different cpu families
supported by arch/powerpc.
Signed-off-by: Michael Ellerman m...@ellerman.id.au
---
Documentation/powerpc/cpu_families.txt | 76
On Fri, Jan 31, 2014 at 08:46:11AM +0800, Gavin Shan wrote:
On Thu, Jan 30, 2014 at 11:00:48AM -0200, Thadeu Lima de Souza Cascardo wrote:
Commit f5c57710dd62dd06f176934a8b4b8accbf00f9f8 (powerpc/eeh: Use
partial hotplug for EEH unaware drivers) introduces eeh_rmv_device,
which may grab a
On Mon, Jan 27, 2014 at 09:07:34PM -0600, Brandon Stewart wrote:
I corrected several coding errors.
Signed-off-by: Brandon Stewart stewar...@gmail.com
---
drivers/macintosh/adb.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/macintosh/adb.c
On 01/22/2014 04:11 PM, Cody P Schafer wrote:
On 01/21/2014 05:32 PM, Michael Ellerman wrote:
On Thu, 2014-01-16 at 15:53 -0800, Cody P Schafer wrote:
These patches add basic pmus for 2 powerpc hypervisor interfaces to obtain
performance counters: gpci (get performance counter info) and 24x7.
On Fri, Jan 31, 2014 at 11:47:44AM +0100, Alexander Graf wrote:
On 31.01.2014, at 11:38, Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
wrote:
Alexander Graf ag...@suse.de writes:
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
We definitely don't need to emulate mtspr, because
On Thu, 2014-01-30 at 12:20 +, Moese, Michael wrote:
Hello PPC-developers,
I'm currently trying to benchmark access speeds to our PCIe-connected IP-cores
located inside our FPGA. On x86-based systems I was able to achieve bursts for
both read and write access. On PPC32, using an e500v2, I
Hi Michael,
I'm currently trying to benchmark access speeds to our PCIe-connected IP-cores
located inside our FPGA. On x86-based systems I was able to achieve bursts for
both read and write access. On PPC32, using an e500v2, I had no success at all
so far.
Whenever I want to benchmark
This patchset fixes a couple of issues encountered in the suspend/resume code
base. First when using the kernel device tree update code update-nodes is
unnecessarily called more than once. Second the cpu cache lists are not
updated after a suspend/resume which under certain conditions may cause a
From: Haren Myneni hb...@us.ibm.com
The current code makes rtas calls for update-nodes, activate-firmware and then
update-nodes again. The FW provides the same data for both update-nodes calls.
As a result a proc entry exists error is reported for the second update while
adding device nodes.
From: Haren Myneni hb...@us.ibm.com
pHyp can change cache nodes for suspend/resume operation. The current code
updates the device tree after all non boot CPUs are enabled. Hence, we do not
modify the cache list based on the latest cache nodes. Also we do not remove
cache entries for the primary
Traditionally it has been drmgr's responsibilty to update the device tree
through the /proc/ppc64/ofdt interface after a suspend/resume operation.
This patchset however has modified suspend/resume ops to preform that update
entirely in the kernel during the resume. Therefore, a mechanism is
On Fri, 2014-01-31 at 07:32 -0600, Kumar Gala wrote:
On Jan 29, 2014, at 8:38 PM, Michael Ellerman m...@ellerman.id.au wrote:
+Freescale BookE
+---
+
+ - Software loaded TLB.
+ - e6500 adds HW loaded indirect TLB entries.
+ - Mix of 32 64 bit
+
+ e200 --- e500 ---
On Thu, 2014-01-30 at 14:32 +1100, Stephen Rothwell wrote:
Hi Michael,
Nice.
On Thu, 30 Jan 2014 13:38:00 +1100 Michael Ellerman m...@ellerman.id.au
wrote:
+++ b/Documentation/powerpc/cpu_families.txt
@@ -0,0 +1,76 @@
+CPU Families
+
+
+This doco tries to
This patch adds some documentation on the different cpu families
supported by arch/powerpc.
Signed-off-by: Michael Ellerman m...@ellerman.id.au
---
v2: Reworked formatting to avoid wrapping.
Fixed up Freescale details.
Documentation/powerpc/cpu_families.txt | 227
On Thu, 2014-16-01 at 23:53:47 UTC, Cody P Schafer wrote:
Add PMU_RANGE_ATTR() and PMU_RANGE_RESV() (for reserved areas) which
generate functions to extract the relevent bits from
event-attr.config{,1,2} for use by sw-like pmus where the
'config{,1,2}' values don't map directly to hardware
Peter, Ingo, can we get your ACK on this please?
cheers
On Thu, 2014-16-01 at 23:53:48 UTC, Cody P Schafer wrote:
Export the swevent hrtimer helpers currently only used in events/core.c
to allow the addition of architecture specific sw-like pmus.
Signed-off-by: Cody P Schafer
On Thu, 2014-16-01 at 23:53:49 UTC, Cody P Schafer wrote:
Signed-off-by: Cody P Schafer c...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/hvcall.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/hvcall.h
On Thu, 2014-16-01 at 23:53:50 UTC, Cody P Schafer wrote:
H_GetPerformanceCounterInfo (refered to as hv_gpci or just gpci from
here on) is an interface to retrieve specific performance counters and
other data from the hypervisor. All outputs have a fixed format (and
are represented as structs
On Thu, 2014-16-01 at 23:53:52 UTC, Cody P Schafer wrote:
This provides a basic link between perf and hv_gpci. Notably, it does
not yet support transactions and does not list any events (they can
still be manually composed).
What are the plans for listing?
The manual compose is nice but
On Thu, 2014-16-01 at 23:53:51 UTC, Cody P Schafer wrote:
24x7 (also called hv_24x7 or H_24X7) is an interface to obtain
performance counters from the hypervisor. These counters do not have a
fixed format/possition and are instead documented in a 24x7 Catalog,
which is provided by the
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