On Sun, 2014-09-21 at 10:55 -0700, Joe Perches wrote:
printk calls should return void
Joe Perches (2):
powerpc: pci-ioda: Remove unnecessary return value from printk
powerpc: pci-ioda: Use a single function to emit logging messages
Patches look good to me.
Ben/Gavin, what do these
On 09/19/2014 11:19 PM, Scott Wood wrote:
On Fri, 2014-09-19 at 15:16 -0500, Scott Wood wrote:
On Thu, 2014-09-18 at 18:26 +1000, Michael Neuling wrote:
From: Ian Munsie imun...@au1.ibm.com
Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation
requests
to the nearest power
Hi Stephen,
On 19/09/14 23:24, Stephen Boyd wrote:
On 09/03/14 10:00, Sudeep Holla wrote:
From: Sudeep Holla sudeep.ho...@arm.com
This patch adds initial support for providing processor cache information
to userspace through sysfs interface. This is based on already existing
On 09/19/2014 11:16 PM, Scott Wood wrote:
On Thu, 2014-09-18 at 18:26 +1000, Michael Neuling wrote:
From: Ian Munsie imun...@au1.ibm.com
Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation requests
to the nearest power of 2. eg. ask for 5 IRQs and you'll get 8. This
Hi Michael,
Minor comment inline.
On 09/18/2014 11:26 AM, Michael Neuling wrote:
From: Ian Munsie imun...@au1.ibm.com
Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation requests
to the nearest power of 2. eg. ask for 5 IRQs and you'll get 8. This wastes
a
lot of IRQs
On Mon, Sep 22, 2014 at 11:05 AM, Geert Uytterhoeven
ge...@linux-m68k.org wrote:
JFYI, when comparing v3.17-rc5[1] to v3.17-rc4[3], the summaries are:
- build errors: +13/-3
+ /scratch/kisskb/src/arch/powerpc/kernel/iommu.c: error:
'fail_iommu_bus_notifier' defined but not used
On Wed, Sep 17, 2014 at 11:51:53AM -0700, Sukadev Bhattiprolu wrote:
SNIP
This means that when provided as an event, a value for
phys_processor_idx must also be supplied. For example:
perf stat -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
Changelog[v3]
On Mon, Sep 15, 2014 at 12:24:27AM +0100, One Thousand Gnomes wrote:
So a problem that no one has ever complained about on _any_ arch is suddenly
a problem on a subset of Alpha cpus, but a problem I know exists on Alpha
isn't important because no one's filed a bug about it?
Yes - because
Hi,
On Wed, Jun 25, 2014 at 08:49:03AM -0700, Sukadev Bhattiprolu wrote:
powerpc/perf: Adjust callchain based on DWARF debug info
When saving the callchain on Power, the kernel conservatively saves excess
entries in the callchain. A few of these entries are needed in some cases
but not
Highlights include DMA32 zone support (SATA, USB, etc now works on 64-bit
FSL kernels), MSI changes, 8xx optimizations and cleanup, t104x board
support, and PrPMC PCI enumeration.
The following changes since commit 78eb9094ca08a40b8f9d3e113a2b88e0b7dbad1d:
powerpc/t2080rdb: Add T2080RDB board
diff --git a/arch/powerpc/sysdev/msi_bitmap.c
b/arch/powerpc/sysdev/msi_bitmap.c
index 2ff6302..e001559 100644
--- a/arch/powerpc/sysdev/msi_bitmap.c
+++ b/arch/powerpc/sysdev/msi_bitmap.c
@@ -24,28 +24,36 @@ int msi_bitmap_alloc_hwirqs(struct msi_bitmap *bmp, int
num)
*
On Mon, 2014-09-22 at 11:26 +0300, Laurentiu Tudor wrote:
On 09/19/2014 11:19 PM, Scott Wood wrote:
On Fri, 2014-09-19 at 15:16 -0500, Scott Wood wrote:
On Thu, 2014-09-18 at 18:26 +1000, Michael Neuling wrote:
From: Ian Munsie imun...@au1.ibm.com
Currently msi_bitmap_alloc_hwirqs()
On Mon, Sep 22, 2014 at 04:56:17PM +1000, Michael Ellerman wrote:
On Sun, 2014-09-21 at 10:55 -0700, Joe Perches wrote:
printk calls should return void
Joe Perches (2):
powerpc: pci-ioda: Remove unnecessary return value from printk
powerpc: pci-ioda: Use a single function to emit logging
When enabling EEH functionality on passed through devices (PE)
with VFIO, the devices in the PE would be removed permanently
from guest side. In that case, the PE remains frozen state.
When returning PE to host, or restarting the guest again, we
had mechanism unfreezing the PE by clearing PESTA/B
PE would be owned by userland, which probably request PE reset
done in host side. During the reset, we should drop the PCI
config accesses to the PE with help of flag EEH_PE_RESET.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/kernel/eeh.c | 2 ++
1 file changed, 2
The names of PCI reset scopes aren't sychronized with firmware.
The patch fixes it.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/opal.h | 9 ++---
arch/powerpc/platforms/powernv/eeh-ioda.c | 12 ++--
On 09/17/2014 12:15 PM, Nathan Fontenot wrote:
On 09/17/2014 02:07 AM, Michael Ellerman wrote:
On Mon, 2014-09-15 at 15:31 -0500, Nathan Fontenot wrote:
For pseries system the kernel will be notified of hotplug requests in
the form of rtas hotplug events.
Can you flesh that design out a
rtas_call() accepts and returns values in CPU endianness.
The ddw_query_response and ddw_create_response structs members are
defined and treated as BE but as they are passed to rtas_call() as
(u32 *) and they get byteswapped automatically, the data is actually
CPU-endian. This fixes
At the moment the iommu_table struct has a set_bypass() which enables/
disables DMA bypass on IODA2 PHB. This is exposed to POWERPC IOMMU code
which calls this callback when external IOMMU users such as VFIO are
about to get over a PHB.
Since the set_bypass() is not really an iommu_table function
This enables PAPR defined feature called Dynamic DMA windows (DDW).
Each Partitionable Endpoint (IOMMU group) has a separate DMA window on
a PCI bus where devices are allows to perform DMA. By default there is
1 or 2GB window allocated at the host boot time and these windows are
used when an
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its physical address to the table.
Otherwise the hardware gets unwanted access to physical memory between
the end of the actual page and the end of the aligned up TCE page.
At the moment pnv_pci_ioda_tce_invalidate() gets the PE pointer via
container_of(tbl). Since we are going to have to add Dynamic DMA windows
and that means having 2 IOMMU tables per PE, this is not going to work.
This implements pnv_pci_ioda(1|2)_tce_invalidate as a pnv_ioda_pe callback.
This
This adds a iommu_table_ops struct and puts pointer to it into
the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
callbacks from ppc_md to the new struct where they really belong to.
This adds an extra @ops parameter to iommu_init_table() to make sure
that we do not leave any
Modern IBM POWERPC systems support multiple IOMMU tables per PE
so we need a more reliable way (compared to container_of()) to get
a PE pointer from the iommu_table struct pointer used in IOMMU functions.
At the moment IOMMU group data points to an iommu_table struct. This
introduces a
This adds missing locks in iommu_take_ownership()/
iommu_release_ownership().
This marks all pages busy in iommu_table::it_map in order to catch
errors if there is an attempt to use this table while ownership over it
is taken.
This only clears TCE content if there is no page marked busy in
The previous patch introduced iommu_table_ops::exchange() callback
which effectively disabled VFIO on pseries. This implements exchange()
for pseries/lpar so VFIO can work in nested guests.
Since exchaange() callback returns an old TCE, it has to call H_GET_TCE
for every TCE being put to the
This makes use of the it_page_size from the iommu_table struct
as page size can differ.
This replaces missing IOMMU_PAGE_SHIFT macro in commented debug code
as recently introduced IOMMU_PAGE_XXX macros do not include
IOMMU_PAGE_SHIFT.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Normally a bitmap from the iommu_table is used to track what TCE entry
is in use. Since we are going to use iommu_table without its locks and
do xchg() instead, it becomes essential not to put bits which are not
implied in the direction flag.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
This defines and implements VFIO IOMMU API which lets the userspace
create and remove DMA windows.
This updates VFIO_IOMMU_SPAPR_TCE_GET_INFO to return the number of
available windows and page mask.
This adds VFIO_IOMMU_SPAPR_TCE_CREATE and VFIO_IOMMU_SPAPR_TCE_REMOVE
to allow the user space to
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without clearing it first.
Another problem this patch is addressing is the use of pool locks for
external IOMMU users such
SPAPR defines an interface to create additional DMA windows dynamically.
Dynamically means that the window is not allocated before the guest
even started, the guest can request it later. In practice, existing linux
guests check for the capability and if it is there, they create and map
a DMA
There moves locked pages accounting to helpers.
Later they will be reused for Dynamic DMA windows (DDW).
While we are here, update the comment explaining why RLIMIT_MEMLOCK
might be required to be bigger than the guest RAM.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
From: Mahesh Salgaonkar mah...@linux.vnet.ibm.com
The flush_tlb hook in cpu_spec was introduced as a generic function hook
to invalidate TLBs. But the current implementation of flush_tlb hook
takes IS (invalidation selector) as an argument which is architecture
dependent. Hence, It is not right
On 09/22/2014 06:21 PM, Scott Wood wrote:
Highlights include DMA32 zone support (SATA, USB, etc now works on 64-bit
FSL kernels), MSI changes, 8xx optimizations and cleanup, t104x board
support, and PrPMC PCI enumeration.
The following changes since commit
Read_msi_msg() only be called in rtas_setup_msi_irqs(),
use __read_msi_msg() instead of read_msi_msg for
simplification.
Signed-off-by: Yijing Wang wangyij...@huawei.com
Acked-by: Michael Ellerman m...@ellerman.id.au
CC: Benjamin Herrenschmidt b...@kernel.crashing.org
CC:
The current implementation of do_page_fault does not check whether the
page being accessed is marked hwpiosoned or not. Hence when an
application tries to access page that is marked hwpoisoned, it results
into Linux hypervisor crash and system goes into IPLing state.
This patch fixes this issue
On Mon, 2014-09-22 at 23:52 -0400, Bob Cochran wrote:
On 09/22/2014 06:21 PM, Scott Wood wrote:
Highlights include DMA32 zone support (SATA, USB, etc now works on 64-bit
FSL kernels), MSI changes, 8xx optimizations and cleanup, t104x board
support, and PrPMC PCI enumeration.
The
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