Hi
On 04/05/2015 08:24 PM, Joe Perches wrote:
These structs can be const, so make them const.
Miscellanea:
o Add static to struct uart_ops declaration in bfin_sport_uart
Signed-off-by: Joe Perches j...@perches.com
---
[...]
for
drivers/tty/serial/st-asc.c | 2 +-
On Tuesday 31 March 2015 16:00:38 Daniel Axtens wrote:
This patch set moves some PCI controller operations out of ppc_md and
into a new pci_controller_ops struct.
This is desirable for systems with more than one type of PCI
controller. In particular, it's intended that this new interface
Le 21/03/2015 00:52, Scott Wood a écrit :
On Fri, Dec 05, 2014 at 12:20:20PM +0100, LEROY Christophe wrote:
include/linux/mm.h: In function 'is_vmalloc_addr':
include/linux/mm.h:367:14: warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
return addr =
Le 21/03/2015 01:47, Scott Wood a écrit :
On Tue, 2015-01-20 at 10:57 +0100, Christophe Leroy wrote:
By default, TASK_SIZE is set to 0x8000 for PPC_8xx, which is most likely
sufficient for most cases. However, kernel configuration allows to set TASK_SIZE
to another value, so the 8xx shall
On Tuesday 07 April 2015 10:31:36 Daniel Axtens wrote:
Please see https://patchwork.ozlabs.org/patch/431333/ for related work.
I'm familiar with that patch series - I've been helping Yijing get it up
to speed on PowerPC.
I think it would be better not to introduce another
On 2015-04-05 at 20:24:54 +0200, Joe Perches j...@perches.com wrote:
[...]
drivers/tty/serial/altera_jtaguart.c| 2 +-
drivers/tty/serial/altera_uart.c| 2 +-
For these two drivers:
Acked-by: Tobias Klauser tklau...@distanz.ch
Le 25/03/2015 01:45, Scott Wood a écrit :
On Fri, 2015-03-13 at 10:34 +1100, Michael Ellerman wrote:
On Thu, 2015-03-12 at 16:24 +0100, Christophe Leroy wrote:
Two config options exist to define powerpc MPC8xx:
* CONFIG_PPC_8xx
* CONFIG_8xx
In addition, CONFIG_PPC_8xx also defines CONFIG_CPM1
On Mon, Apr 06, 2015 at 02:45:58PM -0700, Nishanth Aravamudan wrote:
Hi Peter,
As you are very aware, I think, power has some odd NUMA topologies (and
changes to the those topologies) at run-time. In particular, we can see
a topology at boot:
Node 0: all Cpus
Node 7: no cpus
Then we
On Sunday 05 April 2015 11:55 PM, Joe Perches wrote:
These structs can be const, so make them const.
Miscellanea:
o Add static to struct uart_ops declaration in bfin_sport_uart
Signed-off-by: Joe Perches j...@perches.commailto:j...@perches.com
---
On Sun, 2015-04-05 at 00:04 +0200, Stefan
Memory dlpar handling can return from dlpar_memory() without releasing the
device_hotplug lock. Correct this routine to ensure the lock is released.
This patch applies on top of my previous updates to memory hotplug:
https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-February/124804.html
On 04/03/2015 05:49 PM, Guenter Roeck wrote:
On 04/01/2015 03:15 AM, Cédric Le Goater wrote:
The new OPAL device tree adds a few properties which can be used to add
extra information on the sensor label.
Signed-off-by: Cédric Le Goater c...@fr.ibm.com
---
drivers/hwmon/ibmpowernv.c | 22
The new OPAL device tree adds a few properties which can be used to add
extra information on the sensor label.
In the case of a cpu core sensor, the firmware exposes the physical
identifier of the core in the ibm,pir property. The driver
translates this identifier in a linux cpu number and
On Tue, Apr 07, 2015 at 04:45:56PM +0200, Cédric Le Goater wrote:
The new OPAL device tree adds a few properties which can be used to add
extra information on the sensor label.
In the case of a cpu core sensor, the firmware exposes the physical
identifier of the core in the ibm,pir
Move the entire NX-842 driver for the pSeries platform from the file
nx-842.c to nx-842-pseries.c. This is required by later patches that
add NX-842 support for the PowerNV platform.
This patch does not alter the content of the pSeries NX-842 driver at
all, it only changes the filename.
Add NX-842 frontend that allows using either the pSeries platform
or PowerNV platform driver for the NX-842 hardware. Update the
MAINTAINERS file to include the new filenames.
Signed-off-by: Dan Streetman ddstr...@ieee.org
---
MAINTAINERS| 2 +-
crypto/842.c
Simplify the pSeries NX-842 driver: do not expect incoming buffers to be
exactly page-sized; do not break up input buffers to compress smaller blocks;
do not use any internal headers in the compressed data blocks; remove the
software decompression implementation.
This changes the pSeries NX-842
Add driver for NX-842 hardware on the PowerNV platform.
This allows the use of the 842 compression hardware coprocessor on
the PowerNV platform.
Signed-off-by: Dan Streetman ddstr...@ieee.org
---
drivers/crypto/nx/Kconfig | 10 +
drivers/crypto/nx/Makefile | 2 +
Add an 842-format software decompression function. Update the MAINTAINERS
842 section to include the new files.
This decompression function can decompress any standard-format 842
compressed data. The 842 compressed format is explained in the header
comments. This general-use decompression
Export the of_get_ibm_chip_id() function. This will be used by the
PowerNV NX-842 driver.
Signed-off-by: Dan Streetman ddstr...@ieee.org
---
arch/powerpc/kernel/prom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index
Add configurable module to perform self-tests on any crypto compression
driver.
This allows testing any crypto compression driver with any input buffer,
at varying alignments and lengths. It calculates the average bytes per
second compression and decompression rates. Any errors reported by the
On 07.04.2015 [12:21:47 +0200], Peter Zijlstra wrote:
On Mon, Apr 06, 2015 at 02:45:58PM -0700, Nishanth Aravamudan wrote:
Hi Peter,
As you are very aware, I think, power has some odd NUMA topologies (and
changes to the those topologies) at run-time. In particular, we can see
a
IBM PowerPC processors starting at version P7+ contain a NX coprocessor that
provides various hw-accelerated functions, one of which is memory compression
to the IBM 842 compression format. This NX-842 coprocessor is already
supported on the pSeries platform, by the nx-842.c driver and the crypto
Add the asm ICSWX and ICSWEPX opcodes. Add definitions for the
Coprocessor Request structures needed to use the icswx calls to
coprocessors. Add icswx() function to perform the ICSWX asm
using the provided Coprocessor Command Word value and
Coprocessor Request Block structure.
This is required
Add constraints for the NX-842 driver. The constraints are used to
indicate what the current NX-842 platform driver is capable of. The
constraints tell the NX-842 user what alignment, min and max length, and
length multiple each provided buffers should conform to. These are
required because the
Update the crypto 842 driver to no longer fallback to LZO if the 842
hardware is unavailable. Simplify the crpypto 842 driver to remove all
headers indicating 842/lzo.
The crypto 842 driver should do 842-format compression and decompression
only. It should not fallback to LZO
Hello Guenter,
On 04/07/2015 06:44 PM, Guenter Roeck wrote:
On Tue, Apr 07, 2015 at 04:45:56PM +0200, Cédric Le Goater wrote:
The new OPAL device tree adds a few properties which can be used to add
extra information on the sensor label.
In the case of a cpu core sensor, the firmware exposes
Hi Cedric,
On Tue, Apr 07, 2015 at 08:03:46PM +0200, Cedric Le Goater wrote:
on a P7 :
# ppc64_cpu --info
Core 0:0*1*2*3*
Core 1:4*5*6*7*
Core 2:8*9* 10* 11*
Core 3: 12* 13* 14* 15*
On Tue, Apr 07, 2015 at 10:14:10AM -0700, Nishanth Aravamudan wrote:
So I think (and ISTR having stated this before) that dynamic cpu-node
maps are absolutely insane.
Sorry if I wasn't involved at the time. I agree that it's a bit of a
mess!
There is a ton of stuff that assumes the
On Tue, 2015-04-07 at 20:03 +0200, Cedric Le Goater wrote:
This is a shortcut. The code is for the ibmpowernv platform and assumes
that we are running on a P8 (8 hardware threads). It would be better to
use a maximum threads per core variable but I am not sure this is
available, as it is
On Tue, 2015-04-07 at 10:07 +0200, leroy christophe wrote:
Le 21/03/2015 00:52, Scott Wood a écrit :
On Fri, Dec 05, 2014 at 12:20:20PM +0100, LEROY Christophe wrote:
include/linux/mm.h: In function 'is_vmalloc_addr':
include/linux/mm.h:367:14: warning: comparison between signed and
On Tue, 2015-04-07 at 10:19 +0200, leroy christophe wrote:
Le 25/03/2015 01:45, Scott Wood a écrit :
On Fri, 2015-03-13 at 10:34 +1100, Michael Ellerman wrote:
You'll need to collect ACKs, or get the individual patches merged, and
then we
can take patch 8 through the powerpc tree once
On Sat, 2015-04-04 at 02:40 -0300, Rogério Brito wrote:
Unfortunately, right now, what I see with Linus's tree
(4.0.0-rc6-9-g6c310bc) is the following:
,
| physmap platform flash device: 0040 at ffc0
| physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank. Manufacturer
On Tue, 2015-04-07 at 07:08 +0300, Igal.Liberman wrote:
From: Igal Liberman igal.liber...@freescale.com
Signed-off-by: Igal Liberman igal.liber...@freescale.com
---
.../devicetree/bindings/clock/qoriq-clock.txt | 59
1 file changed, 59 insertions(+)
diff
Unlike normal hardware PMCs, the 24x7 counters[1] in Power8 are stored in
memory and accessed via a hypervisor call (HCALL). A major aspect of the
HCALL is that it allows retireving _SEVERAL_ counters at once (unlike
regular PMCs, which are read one at a time). By reading several counters
at
Dear Scott,
Once again, thank you very much for your answer.
On Apr 07 2015, Scott Wood wrote:
On Tue, 2015-04-07 at 20:58 -0300, Rogério Brito wrote:
This is good to know. Is there any reasonable dts that I can copy/adapt?
I'm not familiar with how flash is connected on this chip, so I
On Fri, 2015-04-03 at 18:35 +0800, Shengzhou Liu wrote:
+ rcpm: global-utilities@e2000 {
+ compatible = fsl,t1023-rcpm, fsl,qoriq-rcpm-2.0;
+ reg = 0xe2000 0x1000;
+ };
+
+ sfp: sfp@e8000 {
+ compatible = fsl,t1023-sfp;
+ reg
On Tue, 2015-04-07 at 20:58 -0300, Rogério Brito wrote:
Dear Scott.
First of all, thank you so very much for your reply.
On Apr 07 2015, Scott Wood wrote:
On Sat, 2015-04-04 at 02:40 -0300, Rogério Brito wrote:
,
| physmap platform flash device: 0040 at ffc0
|
For device resource PREF bit setting under bridge 64-bit pref resource,
we need to make sure only set PREF for 64bit resource, so set IORESOUCE_MEM_64
for 64bit resource during of device resource flags parsing.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96261
Link:
Define a new PERF_PMU_TXN_READ interface to read a group of counters
at once. Note that we use this interface with all PMUs.
PMUs that implement this interface will queue the counters to be read
in -read() and read them all at once in -commit_txn().
PMUs that don't implement PERF_PMU_TXN_READ
The 24x7 counters in Powerpc allow monitoring a large number of counters
simultaneously. They also allow reading several counters in a single
HCALL so we can get a more consistent snapshot of the system.
Use the PMU's transaction interface to monitor and read several event
counters at once. The
Dear Scott.
First of all, thank you so very much for your reply.
On Apr 07 2015, Scott Wood wrote:
On Sat, 2015-04-04 at 02:40 -0300, Rogério Brito wrote:
,
| physmap platform flash device: 0040 at ffc0
| physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank. Manufacturer
Currently, the PMU interface allows reading only one counter at a time.
But some PMUs like the 24x7 counters in Power, support reading several
counters at once. To leveage this functionality, extend the transaction
interface to support a transaction type.
The first type, PERF_PMU_TXN_ADD, refers
On Fri, 2015-04-03 at 18:35 +0800, Shengzhou Liu wrote:
+ board-control@2,0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,t1024-cpld, fsl,deepsleep-cpld;
No fsl,deepsleep-cpld. Just have the driver
perf_event_read_value() is mostly computing the event count and enabled/
running times. Move the perf_event_read() into caller and rename
perf_event_read_value() to perf_event_compute_values().
Changelog[v2]
Export symbol perf_event_read() since x86/kvm needs it now.
Signed-off-by:
perf_event_read() does two things:
- call the PMU to read/update the counter value
- and compute the total count of the event and its children
perf_event_reset() needs the first piece but doesn't need the second.
Similarly, when we implement the ability to read a group of events
On Tue, 2015-04-07 at 21:37 -0300, Rogério Brito wrote:
Dear Scott,
Once again, thank you very much for your answer.
On Apr 07 2015, Scott Wood wrote:
On Tue, 2015-04-07 at 20:58 -0300, Rogério Brito wrote:
This is good to know. Is there any reasonable dts that I can copy/adapt?
On Tue, Apr 7, 2015 at 8:49 PM, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
On Tue, 2015-04-07 at 17:24 -0700, Yinghai Lu wrote:
For device resource PREF bit setting under bridge 64-bit pref resource,
we need to make sure only set PREF for 64bit resource, so set
IORESOUCE_MEM_64
On 04/03/2015 07:50 AM, Alex Williamson wrote:
Should have sent this with the other comments, but found it hiding on my
desktop...
On Sat, 2015-03-28 at 01:55 +1100, Alexey Kardashevskiy wrote:
In order to support memory pre-registration, we need a way to track
the use of every registered
On Tue, 2015-04-07 at 16:31 -0500, Scott Wood wrote:
On Tue, 2015-04-07 at 10:19 +0200, leroy christophe wrote:
Le 25/03/2015 01:45, Scott Wood a écrit :
On Fri, 2015-03-13 at 10:34 +1100, Michael Ellerman wrote:
You'll need to collect ACKs, or get the individual patches merged, and
On Fri, 2015-03-20 at 18:52 -0500, Scott Wood wrote:
On Fri, Dec 05, 2014 at 12:20:20PM +0100, LEROY Christophe wrote:
include/linux/mm.h: In function 'is_vmalloc_addr':
include/linux/mm.h:367:14: warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
On Tue, 2015-04-07 at 09:44 +0200, Arnd Bergmann wrote:
On Tuesday 07 April 2015 10:31:36 Daniel Axtens wrote:
Please see https://patchwork.ozlabs.org/patch/431333/ for related work.
I'm familiar with that patch series - I've been helping Yijing get it up
to speed on PowerPC.
Hi, Scott.
On Apr 07 2015, Scott Wood wrote:
On Tue, 2015-04-07 at 21:37 -0300, Rogério Brito wrote:
I see. If I do some archaeology (read: bisect when it stopped
working), would that help to discover how the flash is connected?
It will probably give you the address and size of the flash,
On Tue, 2015-04-07 at 22:13 -0300, Rogério Brito wrote:
Hi, Scott.
On Apr 07 2015, Scott Wood wrote:
On Tue, 2015-04-07 at 21:37 -0300, Rogério Brito wrote:
I see. If I do some archaeology (read: bisect when it stopped
working), would that help to discover how the flash is connected?
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