Hi Preeti,
On 05/05/2015 09:30 AM, Preeti U Murthy wrote:
> Hi Shilpa,
>
> On 05/04/2015 02:24 PM, Shilpasri G Bhat wrote:
>> Re-evaluate the chip's throttled state on recieving OCC_THROTTLE
>> notification by executing *throttle_check() on any one of the cpu on
>> the chip. This is a sanity chec
Hi Preeti,
On 05/05/2015 09:21 AM, Preeti U Murthy wrote:
> Hi Shilpa,
>
> On 05/04/2015 02:24 PM, Shilpasri G Bhat wrote:
>> The On-Chip-Controller(OCC) can throttle cpu frequency by reducing the
>> max allowed frequency for that chip if the chip exceeds its power or
>> temperature limits. As Pm
Hi Shilpa,
On 05/04/2015 02:24 PM, Shilpasri G Bhat wrote:
> Re-evaluate the chip's throttled state on recieving OCC_THROTTLE
> notification by executing *throttle_check() on any one of the cpu on
> the chip. This is a sanity check to verify if we were indeed
> throttled/unthrottled after receivin
Hi Shilpa,
On 05/04/2015 02:24 PM, Shilpasri G Bhat wrote:
> The On-Chip-Controller(OCC) can throttle cpu frequency by reducing the
> max allowed frequency for that chip if the chip exceeds its power or
> temperature limits. As Pmax capping is a chip level condition report
> this throttling behavi
On 05/04/2015 02:24 PM, Shilpasri G Bhat wrote:
> On a reset cycle of OCC, although the system retires from safe
> frequency state the local pstate is not restored to Pmin or last
> requested pstate. Now if the cpufreq governor initiates a pstate
> change, the local pstate will be in Psafe and we w
On 05/04/2015 02:24 PM, Shilpasri G Bhat wrote:
> OCC is an On-Chip-Controller which takes care of power and thermal
> safety of the chip. During runtime due to power failure or
> overtemperature the OCC may throttle the frequencies of the CPUs to
> remain within the power budget.
>
> We want the
On Tue, 2015-05-05 at 10:27 +0800, Kevin Hao wrote:
> On Mon, May 04, 2015 at 05:17:17PM -0500, Scott Wood wrote:
> > On Thu, 2015-04-30 at 20:29 +0800, Kevin Hao wrote:
> > > In the current code, the RELOCATABLE will be forcedly enabled when
> > > enabling CRASH_DUMP. But for ppc32, the RELOCABLE
On Mon, May 04, 2015 at 05:17:17PM -0500, Scott Wood wrote:
> On Thu, 2015-04-30 at 20:29 +0800, Kevin Hao wrote:
> > In the current code, the RELOCATABLE will be forcedly enabled when
> > enabling CRASH_DUMP. But for ppc32, the RELOCABLE also depend on
> > ADVANCED_OPTIONS and select NONSTATIC_KER
On Thu, 2015-04-30 at 20:29 +0800, Kevin Hao wrote:
> In the current code, the RELOCATABLE will be forcedly enabled when
> enabling CRASH_DUMP. But for ppc32, the RELOCABLE also depend on
> ADVANCED_OPTIONS and select NONSTATIC_KERNEL. This will cause build
> error when CRASH_DUMP=y && ADVANCED_OPT
On Fri, May 01, 2015 at 08:00:14PM -0500, Scott Wood wrote:
> On Tue, 2015-04-28 at 21:01 +0200, christophe leroy wrote:
> > The generated code is most likely different on ppc64. I have no ppc64
> > compiler
For reference: yes you do. Just add -m64.
> Ideal (short of a 64-bit __wsum) would proba
On Mon, 2015-05-04 at 21:17 +, Joakim Tjernlund wrote:
> On Mon, 2015-05-04 at 19:31 +0200, Arnd Bergmann wrote:
> > On Monday 04 May 2015 18:31:31 Joakim Tjernlund wrote:
> > > @@ -252,6 +260,8 @@ static void esdhc_of_platform_init(struct sdhci_host
> > > *host)
> > >
> > > if (vvn
From: "Naveen N. Rao"
If using the symbol table, symbol addresses are not being fixed up
properly, resulting in probes being placed at wrong addresses:
# perf probe do_fork
Added new event:
probe:do_fork(on do_fork)
You can now use it in all perf tools, such as:
per
From: "Naveen N. Rao"
Allow perf probe to work on ppc ABIv1 without the need to specify the
leading dot '.' for functions. 'perf probe do_fork' works with this
patch.
We do this by changing how symbol name comparison works on ppc ABIv1 -
we simply ignore and skip over the initial dot, if one exi
From: "Naveen N. Rao"
On powerpc ABIv2, if no debug-info is found and we use kallsyms, we need
to fixup the function entry to point to the local entry point. Use
offset of 8 since current toolchains always generate 2 instructions (8
bytes).
Signed-off-by: Naveen N. Rao
Reviewed-by: Srikar Drona
From: Ananth N Mavinakayanahalli
ppc64 ELF ABIv2 has a Global Entry Point (GEP) and a Local Entry Point
(LEP). For purposes of probing, we need the LEP - the offset to which is
encoded in st_other.
Signed-off-by: Ananth N Mavinakayanahalli
Reviewed-by: Srikar Dronamraju
Cc: Masami Hiramatsu
C
From: "Naveen N. Rao"
Use the proper prefix when ignoring SyS symbols on ppc ABIv1. While at
it, generalize symbol selection so architectures can implement their own
logic.
Signed-off-by: Naveen N. Rao
Reviewed-by: Srikar Dronamraju
Cc: Ananth N Mavinakayanahalli
Cc: Masami Hiramatsu
Cc: Mic
Hi Ingo,
Besides these 21 patches there are 65 other patches, all present in the
perf-core-for-mingo tag, that I sent a pull request for but had some issues
building on older distros (got reports and fixes for OL6, CentOS6, tested it
all on RHEL6), minor stuff, all noted on the comments ju
From: "Naveen N. Rao"
Currently, perf probe considers patterns including a '.' to be a file.
However, this causes problems on powerpc ABIv1 where all functions have
a leading '.':
$ perf probe -F | grep schedule_timeout_interruptible
.schedule_timeout_interruptible
$ perf probe .schedule_t
From: "Naveen N. Rao"
Use symbol table lookups by default if DWARF is not necessary, since
powerpc ABIv2 encodes local entry points in the symbol table and the
function entry address in DWARF may not be appropriate for kprobes, as
described here:
https://sourceware.org/bugzilla/show_bug.cgi?id=1
Hi Ben,
> On May 2, 2015, at 01:57 , Benjamin Herrenschmidt
> wrote:
>
> On Fri, 2015-05-01 at 13:46 -0500, Rob Herring wrote:
>> On Fri, May 1, 2015 at 10:22 AM, Benjamin Herrenschmidt
>> wrote:
>>> On Fri, 2015-05-01 at 07:54 -0500, Rob Herring wrote:
>>>
The difference seems to be whe
On Mon, 2015-05-04 at 19:31 +0200, Arnd Bergmann wrote:
> On Monday 04 May 2015 18:31:31 Joakim Tjernlund wrote:
> > @@ -252,6 +260,8 @@ static void esdhc_of_platform_init(struct sdhci_host
> > *host)
> >
> > if (vvn > VENDOR_V_22)
> > host->quirks &= ~SDHCI_QUIRK_NO_BUSY
On Mon, 2015-05-04 at 19:41 +0300, Pantelis Antoniou wrote:
>
> You get all of the corner cases handled for free. Perhaps it works for
> your case too.
>
> Perhaps you can educate me on what you need supported and we can make
> sure it’s included.
Which corner cases ?
IE, what I want is simply
Em Wed, Apr 29, 2015 at 11:07:58AM +0530, Srikar Dronamraju escreveu:
> * Arnaldo Carvalho de Melo [2015-04-28 10:54:53]:
>
> > Em Tue, Apr 28, 2015 at 05:35:33PM +0530, Naveen N. Rao escreveu:
> > > This patchset fixes various issues with perf probe on powerpc across
> > > ABIv1 and
> > > ABIv2
On Mon, May 04, 2015 at 08:18:30PM +0300, Andy Shevchenko wrote:
> On Mon, 2015-04-27 at 23:49 -0400, Tejun Heo wrote:
> > On Tue, Apr 28, 2015 at 11:12:25AM +1000, Michael Ellerman wrote:
> > > On Mon, 2015-04-27 at 06:59 -0400, Julian Margetson wrote:
> > > > Kernel 4.1-rc1 build fails on Sam460
On Monday 04 May 2015 18:31:31 Joakim Tjernlund wrote:
> @@ -252,6 +260,8 @@ static void esdhc_of_platform_init(struct sdhci_host
> *host)
>
> if (vvn > VENDOR_V_22)
> host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
> +
> + host->mmc->caps |= MMC_CAP_8_BIT_DATA;
> }
>
Archs like ppc64 require pte_t * to remain stable in some code path.
They use local_irq_disable to prevent a parallel split. Generic code
clear pmd instead of marking it _PAGE_SPLITTING in code path
where we can afford to mark pmd none before splitting. Use a
variant of pmdp_splitting_clear_notify
On Mon, 2015-04-27 at 23:49 -0400, Tejun Heo wrote:
> On Tue, Apr 28, 2015 at 11:12:25AM +1000, Michael Ellerman wrote:
> > On Mon, 2015-04-27 at 06:59 -0400, Julian Margetson wrote:
> > > Kernel 4.1-rc1 build fails on Sam460ex amcc 460ex powerpc Canyonlands
> > > with
> > > CONFIG_SATA_DWC=y
>
Signed-off-by: Joakim Tjernlund
---
drivers/mmc/host/sdhci-of-esdhc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/host/sdhci-of-esdhc.c
index 22e9111..7130130 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host
For PowerPC esdhc pre divider starts at 1, fixing this increases
the actual clock from 40 MHz to 50 MHz.
Signed-off-by: Joakim Tjernlund
---
drivers/mmc/host/sdhci-of-esdhc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c
b/drivers/mmc/
On Monday 04 May 2015 19:09:49 Suman Tripathi wrote:
> This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI
> controller.
>
> v1 change:
> * Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping.
>
> v2 change:
> * Drop the IOMMU support and switching to PIO mode for arasan.
>
On 05/04/2015 03:39 PM, Suman Tripathi wrote:
> This patch adds the quirks and compatible string in sdhci-of-arasan.c
> to support sdhci-arasan4.9a version of controller.
>
> Signed-off-by: Suman Tripathi
> ---
> drivers/mmc/host/sdhci-of-arasan.c | 7 +++
> 1 file changed, 7 insertions(+)
>
On 05/04/2015 03:39 PM, Suman Tripathi wrote:
> This patch updates Arasan SDHC documentation to support
> 4.9a version of Arasan SDHC controller.
>
> Signed-off-by: Suman Tripathi
> ---
> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletio
This patch updates Arasan SDHC documentation to support
4.9a version of Arasan SDHC controller.
Signed-off-by: Suman Tripathi
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/ara
This patch adds the quirks and compatible string in sdhci-of-arasan.c
to support sdhci-arasan4.9a version of controller.
Signed-off-by: Suman Tripathi
---
drivers/mmc/host/sdhci-of-arasan.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/m
This patch adds the arasan sdhc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi
---
arch/arm64/boot/dts/apm-mustang.dts | 4
arch/arm64/boot/dts/apm-storm.dtsi | 44 +
2 files changed, 48 insertions(+)
diff --git a
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI
controller.
v1 change:
* Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping.
v2 change:
* Drop the IOMMU support and switching to PIO mode for arasan.
controller integrated inside APM X-Gene SoC.
v3 change:
* Change t
> I personaly like having set of event files in JSON notation
> rather than having them directly in C structure
Yes, strings are better and JSON input is also better.
I prototyped translating JSON into the proposed structures. I already had to
add three new fields, and it wouldn't work for uncor
If frequency is throttled due to OCC reset then cpus will be in Psafe
frequency, so restore the frequency on all cpus to policy->cur when
OCCs are active again. And if frequency is throttled due to Pmax
capping then restore the frequency of all the cpus in the chip on
unthrottling.
Signed-off-by:
On a reset cycle of OCC, although the system retires from safe
frequency state the local pstate is not restored to Pmin or last
requested pstate. Now if the cpufreq governor initiates a pstate
change, the local pstate will be in Psafe and we will be reporting a
false positive when we are not thrott
OCC is an On-Chip-Controller which takes care of power and thermal
safety of the chip. During runtime due to power failure or
overtemperature the OCC may throttle the frequencies of the CPUs to
remain within the power budget.
We want the cpufreq driver to be aware of such situations to be able
to
Re-evaluate the chip's throttled state on recieving OCC_THROTTLE
notification by executing *throttle_check() on any one of the cpu on
the chip. This is a sanity check to verify if we were indeed
throttled/unthrottled after receiving OCC_THROTTLE notification.
We cannot call *throttle_check() direc
Add OPAL_MSG_OCC message definition to opal_message_type to receive
OCC events like reset, load and throttled. Host performance can be
affected when OCC is reset or OCC throttles the max Pstate.
We can register to opal_message_notifier to receive OPAL_MSG_OCC type
of message and report it to the us
The On-Chip-Controller(OCC) can throttle cpu frequency by reducing the
max allowed frequency for that chip if the chip exceeds its power or
temperature limits. As Pmax capping is a chip level condition report
this throttling behavior at chip level and also do not set the global
'throttled' on Pmax
This patchset intends to add frequency throttle reporting mechanism
to powernv-cpufreq driver when OCC throttles the frequency. OCC is an
On-Chip-Controller which takes care of the power and thermal safety of
the chip. The CPU frequency can be throttled during an OCC reset or
when OCC tries to limi
Compared with Bus PE, VF PE just has one single pci function. This
introduces the difference of error handling on a VF PE.
For example in the hotplug case, EEH needs to remove and re-create the VF
properly. In the case when PF's error_detected() disable SRIOV, this patch
introduces a flag to mark
Since FW is not aware of VFs, the restore action for VF should be done in
kernel.
This patch introduces pnv_eeh_vf_restore_config() for VF.
Signed-off-by: Wei Yang
---
arch/powerpc/include/asm/pci-bridge.h|1 +
arch/powerpc/platforms/powernv/eeh-powernv.c | 77
Before VF PE introduced, there isn't a method to reset an individual pci
function. And since FW is not aware of the VF, the VF's reset should be
done in kernel.
This patch introduce a pnv_eeh_vf_pe_reset() to do the flr or af_flr to a
VF.
Signed-off-by: Wei Yang
---
arch/powerpc/include/asm/eeh
EEH on powerpc platform needs eeh_dev structure to track the pci device
status. Since VFs are created/released dynamically, VF's eeh_dev is also
dynamically created/released in system.
This patch creates/removes eeh_dev when pci_dn is created/removed for VFs,
and marks it with EEH_DEV_VF type.
Si
On powernv platform, VF PE is a special PE which is different from the Bus
PE. On the EEH side, it needs a corresponding concept to handle the VF PE
properly. For example, we need to create VF PE when VF's pci_dev is
initialized in kernel. And add a flag to mark it is a VF PF.
This patch introduc
The address cache is used to find the related eeh_dev for a given MMIO
address. From the definition of pci_dev.resource[], it keeps MMIO address
in following order: 6 normal BAR, ROM BAR, 6 IOV BAR, 4 Bridge window.
In the address cache, first it doesn't cache bridge device, second the IOV
BAR ra
As commit ac205b7b ("PCI: make sriov work with hotplug remove") indicates,
when removing PCI devices on a bus which has VFs, we need to remove them
in the reverse order.
This patch applies this pattern to the hotplug removal code for the powerpc
arch.
Signed-off-by: Wei Yang
Acked-by: Gavin Shan
This patch caches the index of a VF in its PF in pci_dn.
Signed-off-by: Wei Yang
---
arch/powerpc/include/asm/pci-bridge.h |1 +
arch/powerpc/kernel/pci_dn.c |5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h
b/arch/po
During the EEH procedure, when a device's driver is not EEH aware or no
driver is binded with a device, EEH core would do hotplug on this devices.
While it isn't feasible for a VF with usual hotplug procedure. During
removal of a VF, virt_bus should be removed if necessary. During the
re-creation,
This patchset enables EEH on SRIOV VFs. The general idea is to create proper
VF edev and VF PE and handle them properly.
Different from the Bus PE, VF PE just contain one VF. This introduces the
difference of EEH error handling on a VF PE. Generally, it has several
differences.
First, the VF's re
On 05/04/2015 08:03 AM, Suman Tripathi wrote:
> Hi,
>
> On Mon, May 4, 2015 at 11:30 AM, Michal Simek wrote:
>> On 05/01/2015 06:54 AM, Suman Tripathi wrote:
>>> This patch updates Arasan SDHC documentation to support
>>> 4.9a version of Arasan SDHC controller.
>>>
>>> Signed-off-by: Suman Tripat
55 matches
Mail list logo
