On Wed, Aug 5, 2015 at 6:56 AM, Ran Shalit ransha...@gmail.com wrote:
On Wed, Aug 5, 2015 at 12:25 AM, Scott Wood scottw...@freescale.com wrote:
On Wed, 2015-08-05 at 00:22 +0300, Ran Shalit wrote:
On Tue, Aug 4, 2015 at 11:31 PM, Scott Wood scottw...@freescale.com wrote:
On Tue, 2015-08-04
Hi Segher,
Thanks for the suggestions. I will rename the function to
update_power8_hid0() and use asm volatile.
On Tue, Aug 04, 2015 at 09:30:57PM -0500, Segher Boessenkool wrote:
On Tue, Aug 04, 2015 at 08:08:58PM +1000, Michael Ellerman wrote:
+static inline void update_hid0(unsigned long
Section 3.7 of Version 1.2 of the Power8 Processor User's Manual
prescribes that updates to HID0 be preceded by a SYNC instruction and
followed by an ISYNC instruction (Page 91).
Create an inline function name update_power8_hid0() which follows this
recipe and invoke it from the static split core
Bytes alignment is required to manage some special RAM,
so add gen_pool_first_fit_align to genalloc,
meanwhile add gen_pool_alloc_data to pass data to
gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper)
Signed-off-by: Zhao Qiang qiang.z...@freescale.com
---
*v2:
changes:
title has been
From: Igal Liberman igal.liber...@freescale.com
Based on prior work by Andy Fleming aflem...@freescale.com
Signed-off-by: Shruti Kanetkar shr...@freescale.com
Signed-off-by: Emil Medve emilian.me...@freescale.com
Signed-off-by: Igal Liberman igal.liber...@freescale.com
---
v3 --- v4:
-
On Mon, 2015-07-27 at 00:18 +0300, Vladimir Zapolskiy wrote:
The sanity checks for overflow are not needed, because this is done on
caller side in fs/sysfs/file.c
Signed-off-by: Vladimir Zapolskiy v...@mleia.com
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Ian Munsie imun...@au1.ibm.com
Cc:
On Wed, 2015-07-29 at 14:40 +1000, Daniel Axtens wrote:
On Wed, 2015-07-29 at 14:25 +1000, Michael Ellerman wrote:
On Wed, 2015-07-29 at 14:07 +1000, Daniel Axtens wrote:
Previously, when attaching a context in dedicated mode, we ignored
Previously? You mean currently? Now is before
On PPC_8xx, lwz has a 2 cycles latency, and branching also takes
2 cycles. On some other powerpc, lwz has 3 cycles.
As the size of the header is minimum 5 words, we can unroll the loop
for the first words to reduce number of branching, and we can re-order
the instructions to limit loading
On Wed, 2015-08-05 at 00:20 -0500, Segher Boessenkool wrote:
Hi Andy,
On Tue, Aug 04, 2015 at 05:36:45PM +0300, Andy Shevchenko wrote:
+struct device_node *pseries_of_derive_parent(const char *path)
+{
+ struct device_node *parent = NULL;
+ char *parent_path = /;
+ size_t
On Tue, 4 Aug 2015, Boris Ostrovsky wrote:
On 08/04/2015 02:12 PM, Julien Grall wrote:
/*
* We detect special mappings in one of two ways:
@@ -217,9 +232,13 @@ static inline unsigned long bfn_to_local_pfn(unsigned
long mfn)
/* VIRT - MACHINE conversion */
#define
On Tue, 4 Aug 2015, Julien Grall wrote:
Based on include/xen/mm.h [1], Linux is mistakenly using MFN when GFN
is meant, I suspect this is because the first support for Xen was for
PV. This resulted in some misimplementation of helpers on ARM and
confused developers about the expected behavior.
On Tue, Aug 4, 2015 at 5:18 AM, Scott Wood scottw...@freescale.com
wrote:
[Added linuxppc-dev@lists.ozlabs.org. Besides that list being
required for
review of PPC patches, it feeds the patchwork that I use to track and
apply
patches.]
On Mon, 2015-08-03 at 19:52 +0800, Chenhui Zhao wrote:
Hi Boris,
On 05/08/15 00:16, Boris Ostrovsky wrote:
On 08/04/2015 02:12 PM, Julien Grall wrote:
/*
* We detect special mappings in one of two ways:
@@ -217,9 +232,13 @@ static inline unsigned long
bfn_to_local_pfn(unsigned long mfn)
/* VIRT - MACHINE conversion */
#define
On 08/05/2015 06:51 AM, Julien Grall wrote:
diff --git a/drivers/video/fbdev/xen-fbfront.c
b/drivers/video/fbdev/xen-fbfront.c
index 09dc447..25e3cce 100644
--- a/drivers/video/fbdev/xen-fbfront.c
+++ b/drivers/video/fbdev/xen-fbfront.c
@@ -539,7 +539,7 @@ static int xenfb_remove(struct
On 05/08/15 13:19, Boris Ostrovsky wrote:
On 08/05/2015 06:51 AM, Julien Grall wrote:
diff --git a/drivers/video/fbdev/xen-fbfront.c
b/drivers/video/fbdev/xen-fbfront.c
index 09dc447..25e3cce 100644
--- a/drivers/video/fbdev/xen-fbfront.c
+++ b/drivers/video/fbdev/xen-fbfront.c
@@ -539,7
On 08/05/2015 08:33 AM, Julien Grall wrote:
On 05/08/15 13:19, Boris Ostrovsky wrote:
On 08/05/2015 06:51 AM, Julien Grall wrote:
diff --git a/drivers/video/fbdev/xen-fbfront.c
b/drivers/video/fbdev/xen-fbfront.c
index 09dc447..25e3cce 100644
--- a/drivers/video/fbdev/xen-fbfront.c
+++
From: Igal Liberman igal.liber...@freescale.com
The Freescale Data Path Acceleration Architecture (DPAA)
is a set of hardware components on specific QorIQ multicore processors.
This architecture provides the infrastructure to support simplified
sharing of networking interfaces and accelerators by
From: Igal Liberman igal.liber...@freescale.com
The FMan FLib provides the basic API used by the FMan drivers to
configure and control the FMan hardware.
Signed-off-by: Igal Liberman igal.liber...@freescale.com
---
drivers/net/ethernet/freescale/Kconfig |1 +
From: Igal Liberman igal.liber...@freescale.com
The FMan Port FLib provides basic API used by the drivers to
configure and control the FMan Port hardware.
Signed-off-by: Igal Liberman igal.liber...@freescale.com
---
drivers/net/ethernet/freescale/fman/Makefile |2 +
The purpose of this patchset is to optimise csum_partial() on powerpc32.
In the first part, we remove some unneccessary instructions
In the second part, we partially unloop the main loop
Christophe Leroy (2):
Optimise a few instructions in csum_partial()
Optimise csum_partial() loop
r5 does contain the value to be updated, so lets use r5 all way long
for that. It makes the code more readable.
To avoid confusion, it is better to use adde instead of addc
The first addition is useless. Its only purpose is to clear carry.
As r4 is a signed int that is always positive, this can
From: Igal Liberman igal.liber...@freescale.com
Add Frame Manager Multi-User RAM support.
Signed-off-by: Igal Liberman igal.liber...@freescale.com
---
drivers/net/ethernet/freescale/fman/Kconfig|1 +
drivers/net/ethernet/freescale/fman/Makefile |6 +-
On the 8xx, load latency is 2 cycles and taking branches also takes
2 cycles. So let's unroll the loop.
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
v2: Only use lwzu for the last load as lwzu has undocumented
additional latency
arch/powerpc/lib/checksum_32.S | 16
From: Igal Liberman igal.liber...@freescale.com
Add Frame Manger MAC Driver support.
This patch adds The FMan MAC configuration, initialization and
runtime control routines.
This patch contains support for these types of MACs:
tGEC, dTSEC and mEMAC
Signed-off-by: Igal Liberman
From: Igal Liberman igal.liber...@freescale.com
Add Storage Profiles support.
The Storage Profiles contain parameters that are used by the FMan in
order to store frames being received on the Rx ports, or to
determine the parameters that affect writing the Internal Context
in the frame margin on
From: Igal Liberman igal.liber...@freescale.com
This patch adds the Ethernet MAC driver support.
Signed-off-by: Igal Liberman igal.liber...@freescale.com
Signed-off-by: Madalin Bucur madalin.bu...@freescale.com
---
drivers/net/ethernet/freescale/fman/inc/mac.h | 135
From: Igal Liberman igal.liber...@freescale.com
This patch adds The FMan Port configuration, initialization and
runtime control routines.
Signed-off-by: Igal Liberman igal.liber...@freescale.com
---
drivers/net/ethernet/freescale/fman/Makefile |2 +-
From: Igal Liberman igal.liber...@freescale.com
Add Frame Manger Driver support.
This patch adds The FMan configuration, initialization and
runtime control routines.
Signed-off-by: Igal Liberman igal.liber...@freescale.com
---
drivers/net/ethernet/freescale/fman/Makefile |2 +-
On Wed, Aug 5, 2015 at 9:11 AM, Ran Shalit ransha...@gmail.com wrote:
On Wed, Aug 5, 2015 at 6:56 AM, Ran Shalit ransha...@gmail.com wrote:
On Wed, Aug 5, 2015 at 12:25 AM, Scott Wood scottw...@freescale.com wrote:
On Wed, 2015-08-05 at 00:22 +0300, Ran Shalit wrote:
On Tue, Aug 4, 2015 at
IPG clock have to be enabled during AC'97 CODEC register
access in fsl_ssi driver.
Signed-off-by: Maciej Szmigiero m...@maciej.szmigiero.name
---
This is a resend without changes, to keep the whole series
together.
sound/soc/fsl/fsl_ssi.c | 19 +++
1 files changed, 19
AC'97 DAI driver struct need the same probe method as
I2S one to setup DMA params in fsl_ssi driver.
Signed-off-by: Maciej Szmigiero m...@maciej.szmigiero.name
---
This is a resend without changes, to keep the whole series
together.
sound/soc/fsl/fsl_ssi.c |1 +
1 files changed, 1
AC'97 bus can support asymmetric playback/capture rates
so enable them in this case in fsl_ssi driver.
Signed-off-by: Maciej Szmigiero m...@maciej.szmigiero.name
---
This is a resend without changes, to keep the whole series
together.
sound/soc/fsl/fsl_ssi.c |4 +++-
1 files changed, 3
Instantiate AC'97 CODEC in fsl_ssi driver AC'97 mode.
Signed-off-by: Maciej Szmigiero m...@maciej.szmigiero.name
---
This is a resend without changes, to keep the whole series
together.
sound/soc/fsl/fsl_ssi.c | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff
Adjust set DAI format function in fsl_ssi driver
so it doesn't fail and clears RXDIR in AC'97 mode.
Signed-off-by: Maciej Szmigiero m...@maciej.szmigiero.name
---
Changes from v1: fix indentation to be consistent with rest
of the driver.
sound/soc/fsl/fsl_ssi.c |8 +---
1 files changed,
Check whether setting AC'97 ops succeeded and clean them
on removal so the fsl_ssi driver can be reloaded.
Signed-off-by: Maciej Szmigiero m...@maciej.szmigiero.name
---
This is a resend without changes, to keep the whole series
together.
sound/soc/fsl/fsl_ssi.c |9 -
1 files
This patch series adds the Ethernet driver for the Freescale
QorIQ Data Path Acceleration Architecture (DPAA).
This version includes changes following the feedback received
on previous versions from Eric Dumazet, Bob Cochran, Joe Perches,
Paul Bolle, Joakim Tjernlund, Scott Wood, David Miller -
Introduce managed counterparts for alloc_percpu() and free_percpu().
Add devm_alloc_percpu() and devm_free_percpu() into the managed
interfaces list.
Signed-off-by: Madalin Bucur madalin.bu...@freescale.com
---
Documentation/driver-model/devres.txt | 4 +++
drivers/base/devres.c
Add support for Scater/Gather (S/G) frames. The FMan can place
the frame content into multiple buffers and provide a S/G Table
(SGT) into one first buffer with references to the others.
Signed-off-by: Madalin Bucur madalin.bu...@freescale.com
---
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
This introduces the Freescale Data Path Acceleration Architecture
(DPAA) Ethernet driver (dpaa_eth) that builds upon the DPAA QMan,
BMan, PAMU and FMan drivers to deliver Ethernet connectivity on
the Freescale DPAA QorIQ platforms.
Signed-off-by: Madalin Bucur madalin.bu...@freescale.com
---
Allow the selection of the transmission queue based on the CPU id.
Signed-off-by: Madalin Bucur madalin.bu...@freescale.com
---
drivers/net/ethernet/freescale/dpaa/Kconfig | 10 ++
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c| 3 +++
Export Frame Queue and Buffer Pool IDs through sysfs.
Signed-off-by: Madalin Bucur madalin.bu...@freescale.com
---
drivers/net/ethernet/freescale/dpaa/Makefile | 2 +-
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c | 2 +
drivers/net/ethernet/freescale/dpaa/dpaa_eth.h | 3 +
Export per CPU counters through debugfs.
Signed-off-by: Madalin Bucur madalin.bu...@freescale.com
---
drivers/net/ethernet/freescale/dpaa/Kconfig| 7 +
drivers/net/ethernet/freescale/dpaa/Makefile | 3 +
drivers/net/ethernet/freescale/dpaa/dpaa_debugfs.c | 272
Add support for basic ethtool operations.
Signed-off-by: Madalin Bucur madalin.bu...@freescale.com
---
drivers/net/ethernet/freescale/dpaa/Makefile | 2 +-
.../net/ethernet/freescale/dpaa/dpaa_eth_common.c | 2 +
.../net/ethernet/freescale/dpaa/dpaa_eth_common.h | 3 +
Add a series of counters to be exported through debugfs:
- add detailed counters for reception errors;
- add detailed counters for QMan enqueue reject events;
- count the number of fragmented skbs received from the stack;
- count all frames received on the Tx confirmation path;
- add congestion
Add trace points on the hot processing path.
Signed-off-by: Ruxandra Ioana Radulescu ruxandra.radule...@freescale.com
---
drivers/net/ethernet/freescale/dpaa/Makefile | 1 +
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c | 12 ++
drivers/net/ethernet/freescale/dpaa/dpaa_eth.h |
On Wed, Aug 05, 2015 at 11:08:55AM +0100, Stefano Stabellini wrote:
On Tue, 4 Aug 2015, Julien Grall wrote:
Based on include/xen/mm.h [1], Linux is mistakenly using MFN when GFN
is meant, I suspect this is because the first support for Xen was for
PV. This resulted in some misimplementation
On Tue, Aug 04, 2015 at 07:12:48PM +0100, Julien Grall wrote:
[...]
diff --git a/drivers/net/xen-netback/netback.c
b/drivers/net/xen-netback/netback.c
index 7d50711..3b7b7c3 100644
--- a/drivers/net/xen-netback/netback.c
+++ b/drivers/net/xen-netback/netback.c
@@ -314,7 +314,7 @@ static
On Wed, Aug 05, 2015 at 12:32:55PM +0300, Andy Shevchenko wrote:
If path doesn't contain any slash this will do interesting things;
you might want to fix that too while you're at it :-)
No problem, though it is in the original code. I would do as a separate
patch on top of the series. Will
On Thu, Jul 30, 2015 at 08:13:09AM +, Hongtao Jia wrote:
- Any specific reason why not using OF thermal?
- No, actually.
I'd like to use OF thermal after some clarification.
Regarding to cooling-maps. For some cases there should be more than one cpus
as cooling device and they are
On Wed, 2015-08-05 at 19:30 -0500, Segher Boessenkool wrote:
On Wed, Aug 05, 2015 at 03:29:35PM +0200, Christophe Leroy wrote:
On the 8xx, load latency is 2 cycles and taking branches also takes
2 cycles. So let's unroll the loop.
This is not true for most other 32-bit PowerPC; this patch
The original implementation of pnv_ioda_setup_dma() iterates the
list of PEs and configures the DMA32 space for them one by one.
The function was designed to be called during PHB fixup time.
When configuring PE's DMA32 space in pcibios_setup_bridge(), in
order to support PCI hotplug, we have to
unflatten_dt_node() is called recursively to unflatten FDT nodes
with the assumption that FDT blob has only one root node, which
isn't true when the FDT blob represents device sub-tree. This
improves the function to supporting device sub-tree that have
multiple nodes in the first level:
*
pcibios_setup_bridge() is normally called to update PCI bridge
windows. It allocates PE for PCI buses. However it is not called
on a root bus which does not have an upstream bridge.
This reserves PE# for a root bus in advance. This will be used in
the subsequent patch to do setup.
Signed-off-by:
This introduces one more argument to of_fdt_unflatten_tree()
to specify the root node for the FDT blob, which is going to be
unflattened. In the result, the function can be used to unflatten
FDT blob, which represents device sub-tree in PowerNV hotplug
driver.
Signed-off-by: Gavin Shan
This converts pnv_eeh_poll() to pnv_pci_poll() in order to:
* Return linux error code other than OPAL error code.
* The return value from last OPAL call, requested delay, is
passed to pnv_pci_poll() and delay accordingly. Thus one
call to opal_pci_poll() is saved.
* More
On Thu, Aug 6, 2015 at 11:16 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 19:08 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 8:22 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-07-31 at 17:20 +0800, b29983@freescale.comwrote:
+ /*
On Wed, Aug 05, 2015 at 09:31:41PM -0500, Scott Wood wrote:
On Wed, 2015-08-05 at 19:30 -0500, Segher Boessenkool wrote:
On Wed, Aug 05, 2015 at 03:29:35PM +0200, Christophe Leroy wrote:
On the 8xx, load latency is 2 cycles and taking branches also takes
2 cycles. So let's unroll the
On Wed, 2015-08-05 at 14:50 +0800, Zhao Qiang wrote:
Bytes alignment is required to manage some special RAM,
so add gen_pool_first_fit_align to genalloc,
meanwhile add gen_pool_alloc_data to pass data to
gen_pool_first_fit_align(modify gen_pool_alloc as a wrapper)
Signed-off-by: Zhao Qiang
Nobody is using the this function. The patch drops it.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
Reviewed-by: Alexey Kardashevskiy a...@ozlabs.ru
---
arch/powerpc/platforms/powernv/pci-ioda.c | 71 ---
1 file changed, 71 deletions(-)
diff --git
On P7IOC, the whole DMA32 space is divided evenly to 256MB segments.
Each PE can consume one or multiple DMA32 segments. Current code
doesn't trace the available DMA32 segments and those consumed by
one particular PE. It's conflicting with PCI hotplug.
The patch introduces one bitmap to PHB to
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood scottw...@freescale.com
wrote:
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at
The patch is adding 6 bitmaps, three to PE and three to PHB, to track
the consumed by one particular PE, which can be released once the PE
is destroyed during PCI unplugging time. Also, we're using fixed
quantity of bits to trace the used IO, M32 and M64 segments by PEs
in one particular PHB.
There're 3 windows (IO, M32 and M64) for PHB, root port and upstream
port of the PCIE switch behind root port. In order to support PCI
hotplug, we extend the start/end address of those 3 windows of root
port or upstream port to the start/end address of the 3 PHB's windows.
The current
The patch overrides pcibios_setup_bridge(), called to update PCI
bridge windows at completion of PCI resource assignment, to assign
PE and setup various (resource) mapping in next patch.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pci-bridge.h | 2 ++
The patch exports 4 functions, which base on corresponding OPAL
APIs to get or set PCI slot status. Those functions are going to
be used by PCI hotplug module in subsequent patches:
pnv_pci_get_device_tree() opal_get_device_tree()
pnv_pci_get_presence_status()
Currently, the PEs and their associated resources are assigned
in ppc_md.pcibios_fixup() except those consumed by SRIOV VFs.
The function is called for once after PCI probing and resources
assignment is finished which isn't hotplug friendly.
The patch creates PEs dynamically by
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood scottw...@freescale.com
wrote:
On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
On Sat, Aug 1,
On Wed, Aug 05, 2015 at 09:24:58AM +0800, Wei Yang wrote:
On PHB_IODA2, we enable SRIOV devices by mapping IOV BAR with M64 BARs. If
a SRIOV device's BAR is not 64-bit prefetchable, this is not assigned from
M64 windwo, which means M64 BAR can't work on it.
s/PHB_IODA2/PHB3
s/windwo/window
This
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood scottw...@freescale.com
wrote:
On Mon, 2015-08-03 at
Currently, PowerPC PowerNV platform utilizes ppc_md.pcibios_fixup(),
which is called for once after PCI probing and resource assignment
are completed, to allocate platform required resources for PCI devices:
PE#, IO and MMIO mapping, DMA address translation (TCE) table etc.
Obviously, it's not
Several functions used to configure PE take pe_number to indentify
PE instance. As the pe_number is included in PE instance after it
is reserved or allocated. It's convienent for those functions to
return PE instance which includes the required pe_number.
Signed-off-by: Gavin Shan
The PowerNV PCI hotplug driver is going to use the OF changeset
to manage the changed device sub-tree, which requires those OF
changeset functions are exported.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
drivers/of/dynamic.c | 65 ---
On Wed, Aug 05, 2015 at 09:25:02AM +0800, Wei Yang wrote:
Each VF could have 6 BARs at most. When the total BAR size exceeds the
gate, after expanding it will also exhaust the M64 Window.
This patch limits the boundary by checking the total VF BAR size instead of
the individual BAR.
On Wed, Aug 05, 2015 at 09:25:03AM +0800, Wei Yang wrote:
When M64 BAR is set to Single PE mode, the PE# assigned to VF could be
discrete.
This patch restructures the patch to allocate discrete PE# for VFs when M64
BAR is set to Single PE mode.
Signed-off-by: Wei Yang weiy...@linux.vnet.ibm.com
For P7IOC, the whole available DMA32 space, which is below the
MEM32 space, is divided evenly into 256MB segments. The number
of continuous segments assigned to one particular PE depends on
the PE's DMA weight that is calculated based on the type of each
PCI devices contained in the PE, and PHB's
The patch enables M64 window on P7IOC, which has been enabled on
PHB3. Different from PHB3 where 16 M64 BARs are supported and each
of them can be owned by one particular PE# exclusively or divided
evenly to 256 segments, each P7IOC PHB has 16 M64 BARs and each
of them are divided into 8 segments.
This renames pcibios_{add,remove}_pci_devices to avoid conflicts
with names of weak functions in PCI subsystem. This doesn't
introduce logicial changes.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/pci-bridge.h | 4 ++--
arch/powerpc/kernel/eeh_driver.c
This renames the fields related to PE# in struct pnv_phb for
better reflecting of their usages as Alexey suggested. It doesn't
introduce behavioural changes.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-powernv.c | 2 +-
On Wed, 2015-08-05 at 17:27 +0300, Ran Shalit wrote:
On Wed, Aug 5, 2015 at 9:11 AM, Ran Shalit ransha...@gmail.com wrote:
On Wed, Aug 5, 2015 at 6:56 AM, Ran Shalit ransha...@gmail.com wrote:
On Wed, Aug 5, 2015 at 12:25 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed,
Each PHB maintains an array helping to translate RID (Request
ID) to PE# with the assumption that PE# takes 8 bits, indicating
that we can't have more than 256 PEs. However, pci_dn-pe_number
already had 4-bytes for the PE#.
The patch extends the PE# capacity so that each of them will be
4-bytes
Every PHB maintains a list of PEs based on their DMA32 weight. After
patch powerpc/powernv: Create PEs dynamically, the list is useless
and it's safe to remove it.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci-ioda.c | 18 --
The device tree nodes will be changed dynamically on PCI hotplug
events on PowerNV platform. This enables CONFIG_OF_DYNAMIC on
PowerNV platform to support that.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/Kconfig | 1 +
1 file changed, 1 insertion(+)
This simplifies pnv_eeh_reset() by avoiding the unnecessary nested
if statement. No logicial changes introduced by this.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-powernv.c | 65 +---
1 file changed, 31 insertions(+), 34
In hotplug case, function pcibios_add_pci_devices() is called to
rescan the specified PCI bus, which might not have any child devices.
Access to the PCI bus's child device node will cause kernel crash
without exception.
This adds condition of skipping scanning PCI bus without child devices
in
On Wed, Aug 05, 2015 at 09:25:01AM +0800, Wei Yang wrote:
Based on the limitation of M64 Window size, when VF BAR size is bigger than
64MB, IOV BAR just round up power of 2 of the total_vfs. While the 64MB is
a magic boundary in code, which is hard to maintain.
This patch replaces the hard coded
Ping?
I think I've addressed all the comments in this version. Is there anything else
I need to look at?
Cheers,
Sam.
On Wed, May 27, 2015 at 09:56:57AM +1000, Sam Bobroff wrote:
In 64 bit kernels, the Fixed Point Exception Register (XER) is a 64
bit field (e.g. in kvm_regs and kvm_vcpu_arch)
The available PE#, represented by a bitmap in the PHB, is allocated
in ascending order. It conflicts with the fact that M64 segments are
assigned in same order. In order to avoid the conflict, the patch
allocates PE# in descending order.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
The patch intends to add standalone driver to support PCI hotplug
for PowerPC PowerNV platform, which runs on top of skiboot firmware.
The firmware identified hotpluggable slots and marked their device
tree node with proper ibm,slot-pluggable and ibm,reset-by-firmware.
The driver simply scans
The pci_dn instances are allocated from memblock or bootmem when
creating PCI controller (hoses) in setup_arch(). The PCI hotplug,
which will be supported by proceeding patches, will release PCI
device nodes and their corresponding pci_dn on unplugging event.
The pci_dn instance memory chunks
The original implementation of pnv_ioda_setup_pe_seg() configures
IO and M32 segments by separate logics, which can be merged by
by caching @seg_bitmap, @seg_size, @win in advance. The patch
shouldn't cause any behavioural changes.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
The patch moves functions related to releasing PE around so that
we don't need extra declaration for them in subsequent patches.
Also, it fixes warnings from scripts/checkpatch.pl. It doesn't
introduce any behavioural changes.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
Previously we wouldn't remove pdn because PCI hotplug isn't
supported. update_dn_pci_info() is called at system booting
time to create pdn for PCI device nodes. However, it's going
to be changed later because of PCI hotplug.
This converts update_dn_pci_info() to add_pci_device_node_info(),
On Wed, Aug 05, 2015 at 09:25:00AM +0800, Wei Yang wrote:
In current implementation, when VF BAR is bigger than 64MB, it uses 4 M64
BAR in Single PE mode to cover the number of VFs required to be enabled.
By doing so, several VFs would be in one VF Group and leads to interference
between VFs in
This changes of_fdt_unflatten_tree() so that it returns the allocated
memory chunk for unflattened device-tree, which can be released once
it's obsoleted.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
drivers/of/fdt.c | 11 ++-
include/linux/of_fdt.h | 2 +-
2 files
The skiboot firmware might provide the capability of resetting PCI
slot by property ibm,reset-by-firmware on the PCI slot associated
device node. The patch checks on the property and route the reset
to firmware if the property exists. Otherwise, we fail back to the
old path as before.
pnv_pci_reset_secondary_bus(), invoked by pcibios_reset_secondary_bus()
on PowerNV platform. The latter can't be called on root bus. So the
former needn't cover root bus as well.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/eeh-powernv.c | 12
The patch introduces helper function pnv_ioda_init_pe(), which
initialize PE instance after reserving or allocating PE#, to
simplify the code. The patch doesn't introduce behavioural
changes.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci-ioda.c | 20
This adds the refcount to PE, which represents number of PCI
devices contained in the PE. When last device leaves from the
PE, the PE together with its consumed resources (IO, DMA, PELTM,
PELTV) are released, to support PCI hotplug.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
On Wed, Aug 05, 2015 at 09:24:59AM +0800, Wei Yang wrote:
The alignment of IOV BAR on PowerNV platform is the total size of the IOV
BAR. No matter whether the IOV BAR is truncated or not, the total size
could be calculated by (vfs_expanded * VF size).
s/VF size/VF BAR size
I think the changelog
On Thu, 2015-08-06 at 12:32 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 11:16 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 19:08 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 8:22 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-07-31 at
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