The previous patch introduced a flag that specified pages in a VMA
should be placed on the unevictable LRU, but they should not be made
present when the area is created. This patch adds the ability to set
this state via the new mlock system calls.
We add MLOCK_ONFAULT for mlock2 and MCL_ONFAULT
mlock() allows a user to control page out of program memory, but this
comes at the cost of faulting in the entire mapping when it is
allocated. For large mappings where the entire area is not necessary
this is not ideal. Instead of forcing all locked pages to be present
when they are allocated,
2015-08-26 11:26 GMT+03:00 Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com:
Hi,
This patchset implements kernel address sanitizer for ppc64.
Since ppc64 virtual address range is divided into different regions,
we can't have one contigous area for the kasan shadow range. Hence
we don't
2015-08-26 11:26 GMT+03:00 Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com:
Conditionalize the check using #ifdef
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
mm/kasan/report.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git
On 08/26/2015 07:44 AM, Joseph Myers wrote:
On Thu, 20 Aug 2015, Michael Ellerman wrote:
On Wed, 2015-08-19 at 14:39 +, Joseph Myers wrote:
I'd like to ping this patch series, not having seen any comments on it.
[PATCH 0/8] math-emu: Update kernel math-emu code from current glibc soft-fp
With the refactored mlock code, introduce a new system call for mlock.
The new call will allow the user to specify what lock states are being
added. mlock2 is trivial at the moment, but a follow on patch will add
a new mlock state making it useful.
Signed-off-by: Eric B Munson emun...@akamai.com
Implement code that returns the generic CPU ID string for Powerpc.
This will be used to identify the specific table of PMU events to
parse/compare user specified events against.
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Acked-by: Jiri Olsa jo...@redhat.com
---
Changelog[v14]
From: Andi Kleen a...@linux.intel.com
Automatically adapt the now wider and word wrapped perf list
output to wider terminals. This requires querying the terminal
before the auto pager takes over, and exporting this
information from the pager subsystem.
Signed-off-by: Andi Kleen
From: Andi Kleen a...@linux.intel.com
Add a --no-desc flag to perf list to not print the event descriptions
that were earlier added for JSON events. This may be useful to
get a less crowded listing.
It's still default to print descriptions as that is the more useful
default for most users.
From: Andi Kleen a...@linux.intel.com
Add a PERF_CPUID variable to override the CPUID of the current CPU (within
the current architecture). This is useful for testing, so that all event
lists can be tested on a single system.
Signed-off-by: Andi Kleen a...@linux.intel.com
Signed-off-by: Sukadev
CPUs support a large number of performance monitoring events (PMU events)
and often these events are very specific to an architecture/model of the
CPU. To use most of these PMU events with perf, we currently have to identify
them by their raw codes:
perf stat -e r100f2 sleep 1
This
Allow assigning categories Topics field to the PMU events i.e.
process the topic field from the JSON file and add a corresponding
topic field to the generated C events tables.
Signed-off-by: Andi Kleen a...@linux.intel.com
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Acked-by:
Implement support in jevents to parse long descriptions for events
that may have them in the JSON files. A follow on patch will make this
long description available to user through the 'perf list' command.
Signed-off-by: Andi Kleen a...@linux.intel.com
Signed-off-by: Sukadev Bhattiprolu
At run time (when 'perf' is starting up), locate the specific table
of PMU events that corresponds to the current CPU. Using that table,
create aliases for the each of the PMU events in the CPU. The use
these aliases to parse the user specified perf event.
In short this would allow the user to
Previously we were dropping the useful longer descriptions that some
events have in the event list completely. Now that jevents provides
support for longer descriptions (see previous patch), add support for
parsing the long descriptions
Signed-off-by: Andi Kleen a...@linux.intel.com
Previously we were dropping the useful longer descriptions that some
events have in the event list completely. This patch makes them appear with
perf list.
Old perf list:
baclears:
baclears.all
[Counts the number of baclears]
vs new:
perf list -v:
...
baclears:
baclears.all
From: Andi Kleen a...@linux.intel.com
Add support to print alias descriptions in perf list, which
are taken from the generated event files.
The sorting code is changed to put the events with descriptions
at the end. The descriptions are printed as possibly multiple word
wrapped lines.
Example
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Acked-by: Jiri Olsa jo...@redhat.com
---
tools/perf/pmu-events/README | 122 ++
1 file changed, 122 insertions(+)
create mode 100644 tools/perf/pmu-events/README
diff --git
From: Andi Kleen a...@linux.intel.com
Implement the code to match CPU types to mapfile types for x86
based on CPUID. This extends an existing similar function,
but changes it to use the x86 mapfile cpu description.
This allows to resolve event lists generated by jevents.
Signed-off-by: Andi
From: Andi Kleen a...@linux.intel.com
Add support to group the output of perf list by the Topic field
in the JSON file.
Example output:
% perf list
...
Cache:
l1d.replacement
[L1D data line replacements]
l1d_pend_miss.pending
[L1D miss oustandings duration in cycles]
From: Andi Kleen a...@linux.intel.com
To work with existing mapfiles, assume that the first line in
'mapfile.csv' is a header line and skip over it.
Signed-off-by: Andi Kleen a...@linux.intel.com
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Acked-by: Jiri Olsa jo...@redhat.com
From: Andi Kleen a...@linux.intel.com
This is a modified version of an earlier patch by Andi Kleen.
We expect architectures to describe the performance monitoring events
for each CPU in a corresponding JSON file, which look like:
[
{
EventCode: 0x00,
UMask: 0x01,
From: Andi Kleen a...@linux.intel.com
I need a JSON parser. This adds the simplest JSON
parser I could find -- Serge Zaitsev's jsmn `jasmine' --
to the perf library. I merely converted it to (mostly)
Linux style and added support for non 0 terminated input.
The parser is quite straight forward
On Wed, 2015-08-26 at 21:47 +1000, Michael Ellerman wrote:
Mostly uninteresting, though a few worth noting:
CONFIG_BLK_DEV_XIP - CONFIG_BLK_DEV_RAM_DAX
CONFIG_CLK_PPC_CORENET - CONFIG_CLK_QORIQ
CONFIG_CRYPTO_ANSI_CPRNG- was default=m, not
Andrey Ryabinin ryabinin@gmail.com writes:
2015-08-26 11:26 GMT+03:00 Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com:
Hi,
This patchset implements kernel address sanitizer for ppc64.
Since ppc64 virtual address range is divided into different regions,
we can't have one contigous area
2015-08-26 11:26 GMT+03:00 Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com:
The function only disable/enable reporting. In the later patch
we will be adding a kasan early enable/disable. Rename kasan_enabled
to properly reflect its function.
Signed-off-by: Aneesh Kumar K.V
On Wed, Aug 26, 2015 at 08:09:47PM +0800, Chenhui Zhao wrote:
+int check_cpu_dead(unsigned int cpu)
+{
+ return per_cpu(cpu_state, cpu) == CPU_DEAD;
+}
I'm not sure this needs to be a function versus open-coded, but if you do
want to make it a function, make it more obvious from the
On Wed, Aug 26, 2015 at 08:09:45PM +0800, Chenhui Zhao wrote:
+#ifdef CONFIG_PPC_BOOK3E
+static void qoriq_disable_thread(int cpu)
+{
+ int hw_cpu = get_hard_smp_processor_id(cpu);
+ int thread = cpu_thread_in_core(hw_cpu);
+
+ mtspr(SPRN_TENC, TEN_THREAD(thread));
+}
+#endif
On Wed, Aug 26, 2015 at 08:09:48PM +0800, Chenhui Zhao wrote:
+ .globl booting_thread_hwid
+booting_thread_hwid:
+ .long INVALID_THREAD_HWID
+ .align 3
The commit message goes into no detail about the changes you're making to
thread handling, nor are there relevant comments.
For T4240-R1.0-R2.0, the HOSTVER register has incorrcet vender
version value and sdhc spec version value. This will break down
the ADMA data transfer. So add workaround to get right value
VVN=0x13, SVN = 0x1.
So T4240-R1.0-R2.0 is the version of the controller, right?
On 06/24/2015 03:25 PM, Benjamin Herrenschmidt wrote:
Now that the table and the offset can co-exist, we no longer need
to flip/flop, we can just establish both once at boot time.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/platforms/powernv/pci-ioda.c | 3
On 24.08.15 10:36, Geert Uytterhoeven wrote:
On Mon, Aug 24, 2015 at 10:34 AM, Geert Uytterhoeven
ge...@linux-m68k.org wrote:
JFYI, when comparing v4.2-rc8[1] to v4.2-rc7[3], the summaries are:
- build errors: +4/-7
4 regressions:
+ /home/kisskb/slave/src/include/linux/kvm_host.h:
Now that we have two features KASAN and KASAN_INLINE, add new feature
support file for the same.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
.../debug/KASAN/KASAN_INLINE/arch-support.txt | 40 ++
.../KASAN/{ = KASAN_OUTLINE}/arch-support.txt |
Some archs may want to provide kasan shadow memory as a constant
offset from the address. Such arch even though cannot use inline kasan
support, they can work with outofline kasan support.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
include/linux/kasan.h | 3 +++
This add helper virt_to_pfn and remove the opencoded usage of the
same.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/page.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/page.h
We use the region with region ID 0xe as the kasan shadow region. Since
we use hash page table, we can't have the early zero page based shadow
region support. Hence we disable kasan in the early code and runtime
enable this. We could imporve the condition using static keys. (but
that is for a later
We we end up calling kasan_report in real mode, our shadow mapping
for even spinlock variable will show poisoned. This will result
in us calling kasan_report_error with lock_report spin lock held.
To prevent this disable kasan reporting when we are priting
error w.r.t kasan.
Signed-off-by: Aneesh
On 08/26/2015 03:11 PM, Alexey Kardashevskiy wrote:
On 08/19/2015 12:01 PM, Wei Yang wrote:
In original design, it tries to group VFs to enable more number of VFs in
the
system, when VF BAR is bigger than 64MB. This design has a flaw in which one
error on a VF will interfere other VFs in the
We add enable/disable callbacks in this patch which architecture
can implemement. We will use this in the later patches for architecture
like ppc64, that cannot have early zero page kasan shadow region for the
entire virtual address space. Such architectures also cannot use
inline kasan support.
Some of the archs, may find it difficult to support inline KASan
mode. Add HAVE_ARCH_KASAN_INLINE so that we can disable inline
support at config time.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
arch/x86/Kconfig | 1 +
lib/Kconfig.kasan | 2 ++
The function only disable/enable reporting. In the later patch
we will be adding a kasan early enable/disable. Rename kasan_enabled
to properly reflect its function.
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
mm/kasan/kasan.h | 2 +-
mm/kasan/report.c | 2 +-
2 files
Missed to cherry-pick the updated version of this patch, before sending
the series out.
commit aeb324e09d95c189eda4ce03790da94b535d1dfc
Author: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
Date: Fri Aug 14 12:28:58 2015 +0530
kasan: Don't use kasan shadow pointer in generic functions
Conditionalize the check using #ifdef
Signed-off-by: Aneesh Kumar K.V aneesh.ku...@linux.vnet.ibm.com
---
mm/kasan/report.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/mm/kasan/report.c b/mm/kasan/report.c
index e07c94fbd0ac..71ce7548d914 100644
---
Freescale CoreNet-based and Non-CoreNet-based platforms require
different PM operations. This patch extracted existing PM operations
on Non-CoreNet-based platforms to a new file which can accommodate
both platforms.
In this way, PM operation codes are clearer structurally.
Signed-off-by: Chenhui
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback function will flush all
There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.
Signed-off-by: Chenhui
Support Freescale E6500 core-based platforms, like t4240.
Support disabling/enabling individual CPU thread dynamically.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
major changes for v2:
* start Thread1 by Thread0 when we want to boot Thread1 only replacing
the method of changing
On Mon, 2015-24-08 at 12:42:47 UTC, Michael Ellerman wrote:
From: Guilherme G. Piccoli gpicc...@linux.vnet.ibm.com
Since commit 1851617cd2da (PCI/MSI: Disable MSI at enumeration even if
kernel doesn't support MSI), the setup of dev-msi_cap/msix_cap and the
disable of MSI/MSI-X interrupts
Mostly uninteresting, though a few worth noting:
CONFIG_BLK_DEV_XIP- CONFIG_BLK_DEV_RAM_DAX
CONFIG_CLK_PPC_CORENET- CONFIG_CLK_QORIQ
CONFIG_CRYPTO_ANSI_CPRNG - was default=m, not anymore
CONFIG_EXT2_FS_XIP- CONFIG_FS_DAX
Freescale E500MC and E5500 core-based platforms, like P4080, T1040,
support disabling/enabling CPU dynamically.
This patch adds this feature on those platforms.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@feescale.com
---
major changes for v2:
On Wed, 2015-08-26 at 02:49 -0500, Lu Yangbo-B47093 wrote:
For T4240-R1.0-R2.0, the HOSTVER register has incorrcet vender
version value and sdhc spec version value. This will break down
the ADMA data transfer. So add workaround to get right value
VVN=0x13, SVN = 0x1.
On Mon, 2015-08-17 at 23:30 -0500, Scott Wood wrote:
Highlights include 32-bit memcpy/memset optimizations, checksum
optimizations, 85xx config fragments and updates, device tree updates,
e6500 fixes for non-SMP, and misc cleanup and minor fixes.
The following changes since commit
On Thu, 20 Aug 2015, Michael Ellerman wrote:
On Wed, 2015-08-19 at 14:39 +, Joseph Myers wrote:
I'd like to ping this patch series, not having seen any comments on it.
[PATCH 0/8] math-emu: Update kernel math-emu code from current glibc soft-fp
https://lkml.org/lkml/2015/7/2/394
On Wed, Aug 26, 2015 at 4:44 PM, Joseph Myers jos...@codesourcery.com wrote:
Ping again for the other-architecture maintainers (alpha, s390, sh,
sparc)
sh is orphaned, cfr. MAINTAINERS.
Perhaps the J2/J4 people are interested in maintainership?
Gr{oetje,eeting}s,
Hi,
This patchset implements kernel address sanitizer for ppc64.
Since ppc64 virtual address range is divided into different regions,
we can't have one contigous area for the kasan shadow range. Hence
we don't support the INLINE kasan instrumentation. With Outline
instrumentation, we override the
We can't use generic functions like print_hex_dump to access kasan
shadow region. This require us to setup another kasan shadow region
for the address passed (kasan shadow address). Most architecture won't
be able to do that. Hence remove dumping kasan shadow region dump. If
we really want to do
On Wed, 2015-08-26 at 18:52 +1000, Alexey Kardashevskiy wrote:
On 06/24/2015 03:25 PM, Benjamin Herrenschmidt wrote:
Now that the table and the offset can co-exist, we no longer need
to flip/flop, we can just establish both once at boot time.
Signed-off-by: Benjamin Herrenschmidt
On Wed, 2015-08-26 at 09:14 -0500, Scott Wood wrote:
On Mon, 2015-08-17 at 23:30 -0500, Scott Wood wrote:
Highlights include 32-bit memcpy/memset optimizations, checksum
optimizations, 85xx config fragments and updates, device tree updates,
e6500 fixes for non-SMP, and misc cleanup and
No need to have two atomic opertions (update and fetch/check) when
decreasing PE's number of passed devices as one atomic operation
is enough.
Signed-off-by: Gavin Shan gws...@linux.vnet.ibm.com
---
arch/powerpc/kernel/eeh.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
On Wed, 2015-08-26 at 14:44 +, Joseph Myers wrote:
On Thu, 20 Aug 2015, Michael Ellerman wrote:
On Wed, 2015-08-19 at 14:39 +, Joseph Myers wrote:
I'd like to ping this patch series, not having seen any comments on it.
[PATCH 0/8] math-emu: Update kernel math-emu code from
Commit cca87d30 (powerpc/pci: Refactor pci_dn) introduced pdn
list for SRIOV VFs. It means the pdn is be put into the child list
of its parent pdn when the pdn is created. When doing PCI hot
unplugging on pSeries, the PCI device node as well as its pdn are
released through procfs entry
This applies cleanup on pci_dn_reconfig_notifier(), no functional
changes:
* Rename variable pci to pdn to indicate its purpose clearly.
* The parent node can be released at any time. So it should be
hold with of_get_parent() before accessing it.
* The device node doesn't have to
On Wed, 2015-08-26 at 09:21 -0500, Scott Wood wrote:
On Wed, 2015-08-26 at 21:47 +1000, Michael Ellerman wrote:
Mostly uninteresting, though a few worth noting:
...
91 files changed, 19 insertions(+), 128 deletions(-)
This conflicts with the 85xx config fragment patches that I've already
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