The existing device tree bindings are error-prone and inflexible.
Correct the mistake by moving the knowledge into the driver, which has
more flexibility in describing the quirks of each chip. This leaves the
device tree to its proper role of identifying a programming interface
rather than
The device tree should describe the chips (or chip-like subblocks) in
the system, but it generally does not describe individual registers --
it should identify, rather than describe, a programming interface.
This has not been the case with the QorIQ clockgen nodes. The
knowledge of what each bit
Freescale's Layerscape ARM chips use the same structure.
Signed-off-by: Scott Wood
---
v3: was patch 2/5
arch/powerpc/include/asm/fsl_guts.h| 192 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +-
Le 09/18/15 02:46, Russell King - ARM Linux a écrit :
> Hi,
>
> While looking at the phy code, I identified a number of weaknesses
> where refcounting on device structures was being leaked, where
> modules could be removed while in-use, and where the fixed-phy could
> end up having unintended
From: poonam aggrwal
Device Tree Bindings for DSP CPU clusters and DSP CPUs for Freescale PowerPC
SOCs which have DSP CPUs in addition to PowerPC CPUs.
For example B4860 has 3 DSP clusters which have 2 SC3900 cores each.
Signed-off-by: Poonam Aggrwal
Get the CPU clock's potential parent clocks from the clock interface
itself, rather than manually parsing the clocks property to find a
phandle, looking at the clock-names property of that, and assuming that
those are valid parent clocks for the cpu clock.
This is necessary now that the clocks
LS2080A is the first implementation of the chassis 3 clockgen, which
has a different register layout than previous chips. It is also little
endian, unlike previous chips.
Signed-off-by: Scott Wood
---
v3: new patch
drivers/clk/Kconfig | 2 +-
Commit fc4a05d4b0eb ("clk: Remove unused provider APIs") removed
__clk_get_num_parents() and clk_hw_get_parent_by_index(), leaving only
true provider API versions that operate on struct clk_hw.
qoriq-cpufreq needs these functions in order to determine the options
it has for calling
On Sat, 2015-09-19 at 23:46 +0530, Poonam Aggrwal wrote:
> From: poonam aggrwal
>
> Device Tree Bindings for DSP CPU clusters and DSP CPUs for Freescale PowerPC
> SOCs which have DSP CPUs in addition to PowerPC CPUs.
> For example B4860 has 3 DSP clusters which have
To make provision for more than one L2 caches in the system, change the name
from L2 to L2_1; same as in T4 platforms.
* Also remove the L2 entry from common file
"arch/powerpc/boot/dts/fsl/b4si-post.dtsi"
Keep them only in separate files for b4860 and b4420.
Signed-off-by: Shaveta Leekha
B4860 has 3 DSP clusters, each cluster having 2 DSP cores (SC3900),
and every cluster has a shared L2 cache.
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
---
- based of:
B4420 has 1 DSP cluster, having 2 DSP cores (SC3900), and a shared L2 cache.
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
---
- based of: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
branch master
On Fri, Sep 18, 2015 at 09:47:32AM -0600, Alex Williamson wrote:
> On Fri, 2015-09-18 at 16:24 +1000, Gavin Shan wrote:
> > This allows to accept IOMMU group (PE) ID from the parameter from userland
> > when handling EEH operation so that the operation only affects the target
> > IOMMU group (PE).
Hi Will,
On Fri, Sep 18, 2015 at 05:59:02PM +0100, Will Deacon wrote:
> On Wed, Sep 16, 2015 at 04:49:31PM +0100, Boqun Feng wrote:
> > On powerpc, we don't need a general memory barrier to achieve acquire and
> > release semantics, so __atomic_op_{acquire,release} can be implemented
> > using
On PowerPC, currently we support different value of PAGE_SIZE and different
value of IOMMU Page Size.
In case the PAGE_SIZE is 4K and the IOMMU Page Size is 16M, and driver
asked for some DMA less than 16M, the current calculation would return 0
and the following allocation in iommu_alloc() would
15 matches
Mail list logo