Now that other PTE fields have been moved out of the way, we can
expand the RPN field of the PTE on 64-bit Book 3S systems and align
it with the RPN field in the radix PTE format used by PowerISA v3.0
CPUs in radix mode. For 64k page size, this means we need to move
the _PAGE_COMBO and _PAGE_4K_PF
This moves the _PAGE_BUSY, _PAGE_SPECIAL and _PAGE_SOFT_DIRTY bits
in the Linux PTE on 64-bit Book 3S systems to bit positions which
are designated for software use in the radix PTE format used by
PowerISA v3.0 CPUs in radix mode.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/book3s
This moves the _PAGE_EXEC, _PAGE_RW and _PAGE_USER bits around in
the Linux PTE on 64-bit Book 3S systems to correspond with the bit
positions used in radix mode by PowerISA v3.0 CPUs. This also adds
a _PAGE_READ bit corresponding to the read permission bit in the
radix PTE. _PAGE_READ is current
This moves the _PAGE_HASHPTE, _PAGE_F_GIX and _PAGE_F_SECOND fields in
the Linux PTE on 64-bit Book 3S systems to the most significant byte.
Of the 5 bits, one is a software-use bit and the other four are
reserved bit positions in the PowerISA v3.0 radix PTE format.
Using these bits is OK because t
This changes _PAGE_PTE for 64-bit Book 3S processors from 0x1 to
0x4000___, because that bit is used as the L (leaf)
bit by PowerISA v3.0 CPUs in radix mode. The "leaf" bit indicates
that the PTE points to a page directly rather than another radix
level, which is what the _PAGE_PTE bit
This changes _PAGE_PRESENT for 64-bit Book 3S processors from 0x2 to
0x8000___, because that is where PowerISA v3.0 CPUs in
radix mode will expect to find it.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 10 +-
arch/powerpc/include/asm/boo
This changes the Linux page tables to store physical addresses
rather than kernel virtual addresses in the upper levels of the
tree (pgd, pud and pmd) for all 64-bit machines.
This frees up some high order bits, and will be needed with book3s
PowerISA v3.0 machines which read the page table tree i
This frees up bits 57-63 in the Linux PTE on 64-bit Book 3S machines.
In the 4k page case, this is done just by reducing the size of the
RPN field to 39 bits, giving 51-bit real addresses. In the 64k page
case, we had 10 unused bits in the middle of the PTE, so this moves
the RPN field down 10 bit
No code changes.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/book3s/64/hash.h | 13 ++---
arch/powerpc/mm/hash64_64k.c | 3 +--
arch/powerpc/mm/hash_utils_64.c | 10 +-
3 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/arch/po
This patch series modifies the Linux PTE format used on 64-bit Book3S
processors (i.e. POWER server processors) to make the bits line up
with the PTE format used in the radix trees defined in PowerISA v3.0.
This will reduce the amount of further change required to make a
kernel that can run with ei
On Sat, Feb 20, 2016 at 12:39:42PM +1100, Paul Mackerras wrote:
> It seems there's something wrong with our transparent hugepage
> implementation on POWER server processors as of v4.5-rc4. I have seen
> the email thread on "[BUG] random kernel crashes after THP rework on
> s390 (maybe also on Powe
From: Madhavan Srinivasan
Add sample_reg_mask array with pt_regs registers.
This is needed for printing supported regs ( -I? option).
Signed-off-by: Madhavan Srinivasan
---
tools/perf/arch/powerpc/util/Build | 1 +
tools/perf/arch/powerpc/util/perf_regs.c | 49 ++
Map ID values with corresponding register names. These names are then
displayed when user issues perf record with the -I option
followed by perf report/script with -D option.
To test this patchset,
Eg:
$ perf record -I ls # record machine state at interrupt
$ perf script -D # read the perf.
The perf infrastructure uses a bit mask to find out valid
registers to display. Define a register mask for supported
registers defined in asm/perf_regs.h. The bit positions also
correspond to register IDs which is used by perf infrastructure
to fetch the register values. CONFIG_HAVE_PERF_REGS enabl
The enum definition assigns an 'id' to each register in "struct pt_regs"
of arch/powerpc. The order of these values in the enum definition are
based on the corresponding macros in arch/powerpc/include/uapi/asm/ptrace.h.
Signed-off-by: Anju T
---
arch/powerpc/include/uapi/asm/perf_regs.h | 50 +++
This short patch series adds the ability to sample the interrupted
machine state for each hardware sample.
To test this patchset,
Eg:
$ perf record -I? # list supported registers
output:
available registers: r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16
r17 r18 r19 r20 r21 r22
Hi Linus,
Please pull some more powerpc fixes for 4.5:
The following changes since commit 2d19fc639516dc7b4184450b315c931d38549e61:
powerpc/mm: Fixup _HPAGE_CHG_MASK (2016-01-28 23:49:43 +1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/li
It seems there's something wrong with our transparent hugepage
implementation on POWER server processors as of v4.5-rc4. I have seen
the email thread on "[BUG] random kernel crashes after THP rework on
s390 (maybe also on PowerPC and ARM)", but this doesn't seem exactly
the same as that (though it
On Thu, 18 Feb 2016, Kirill A. Shutemov wrote:
> I worth minimizing kernel config on which you can see the bug. Things like
> CONFIG_DEBUG_PAGEALLOC used to interfere with THP before.
I disabled all debugging options (using
arch/s390/configs/performance_defconfig) - we still chrashed.
Sebastian
On Wed, 2016-17-02 at 07:26:31 UTC, Alexey Kardashevskiy wrote:
> Quite often drivers set only "write" permission assuming that this
> includes "read" permission as well and this works on plenty platforms.
> However IODA2 is strict about this and produces an EEH when "read"
> permission is not and
On 19/02/16 03:44, Aneesh Kumar K.V wrote:
> We can get a hash pte fault with 4k base page size and find the pte
> already inserted with 64K base page size. In that case we need to clear
> the existing slot information from the old pte. Fix this correctly
>
> With THP, we also clear the slot infor
On 02/19/2016 04:00 PM, Michael Ellerman wrote:
> On Fri, 2016-02-19 at 10:24 +0530, Anshuman Khandual wrote:
>> > On 02/18/2016 08:07 PM, Michael Ellerman wrote:
>>> > > On Wed, 2016-02-17 at 17:42 +0530, Anshuman Khandual wrote:
>>> > >
> > > This renames the global list which tracks all th
On Fri, 2016-02-19 at 11:23 +0530, Anshuman Khandual wrote:
> On 02/18/2016 10:14 PM, Aneesh Kumar K.V wrote:
> > We can get a hash pte fault with 4k base page size and find the pte
> > already inserted with 64K base page size. In that case we need to clear
...
>
> > diff --git a/arch/powerpc/mm/ha
On Fri, 2016-02-19 at 10:24 +0530, Anshuman Khandual wrote:
> On 02/18/2016 08:07 PM, Michael Ellerman wrote:
> > On Wed, 2016-02-17 at 17:42 +0530, Anshuman Khandual wrote:
> >
> > > This renames the global list which tracks all the virtual to physical
> > > mapping and also the global list which
On Friday 19 February 2016 12:55:43 Rashmica Gupta wrote:
>
> config FORCE_MAX_ZONEORDER
> int "Maximum zone order"
> - range 9 64 if PPC64 && PPC_64K_PAGES
> + range 9 9 if PPC64 && PPC_64K_PAGES
> default "9" if PPC64 && PPC_64K_PAGES
> range 13 64 if PPC64 &
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