RE: [PATCH v2 3/5] powerpc/dts: add a compatible string to gpio0

> -Original Message- > From: linuxppc-release-boun...@linux.freescale.net [mailto:linuxppc-release- > boun...@linux.freescale.net] On Behalf Of Chenhui Zhao > Sent: Friday, April 15, 2016 6:13 AM > To: linuxppc-dev@lists.ozlabs.org; o...@buserror.net > Cc: Chenhui Zhao

Re: [PATCH v8 00/45] powerpc/powernv: PCI hotplug support

On Wed, Apr 13, 2016 at 8:30 PM, Gavin Shan wrote: > On Thu, Apr 14, 2016 at 09:57:32AM +1000, Alistair Popple wrote: >>Hi Gavin, >> >> >> >>> >Why exactly cannot EEH reset changes go to a smaller separate patchset >>> >(before hotplug)? >>> > >>> >>> As I explained

Re: [PATCH 0/5] Live patching for powerpc

On Thu, 14 Apr 2016, Michael Ellerman wrote: > Topic branch here: > > > https://git.kernel.org/cgit/linux/kernel/git/powerpc/linux.git/log/?h=topic/livepatch > > I will merge that before Monday (my time) if I don't hear any objections. I've now pulled this into

Re: [1/3] powerpc: scan_features() updates incorrect bits

On Fri, 2016-15-04 at 02:06:13 UTC, Unknown sender due to SPF wrote: > The real LE feature entry in the ibm_pa_feature struct has the > wrong number of elements. Instead of checking for byte 5, bit 0, > we check for byte 0, bit 0, and we also incorrectly update cpu user > feature bit 5. > > Fixes:

Re: [PATCH 0/5] Live patching for powerpc

On Fri, 2016-04-15 at 07:59 -0500, Josh Poimboeuf wrote: > On Fri, Apr 15, 2016 at 09:22:49PM +1000, Michael Ellerman wrote: > > On Thu, 2016-04-14 at 11:41 -0500, Josh Poimboeuf wrote: > > > On Thu, Apr 14, 2016 at 05:20:29PM +0200, Torsten Duwe wrote: > > > > On Thu, Apr 14, 2016 at 11:08:02PM

Re: [v4, 2/3] ppc64/book3s: make some room for common interrupt vector code

On Fri, 2016-04-15 at 21:06 +1000, Michael Ellerman wrote: > Hi Hari, > > Thanks for persisting with this. > > On Thu, 2016-07-04 at 21:58:50 UTC, Hari Bathini wrote: > > With the previous patch, we choke out whatever little space is left > > below 0x7000 (FWNMI hard block) while there is a hole

Re: [PATCH 0/5] Live patching for powerpc

On Fri, Apr 15, 2016 at 09:22:49PM +1000, Michael Ellerman wrote: > On Thu, 2016-04-14 at 11:41 -0500, Josh Poimboeuf wrote: > > On Thu, Apr 14, 2016 at 05:20:29PM +0200, Torsten Duwe wrote: > > > On Thu, Apr 14, 2016 at 11:08:02PM +1000, Michael Ellerman wrote: > > > > On Thu, 2016-04-14 at 14:57

Ran out of outbound PCI ATMUs for IO resource

Hi, I run into this message "Ran out of outbound PCI ATMUs for IO resource". The only solution I found so far is to replace few lines in this way: pci0: pcie@f1008000 { reg = <0xf1008000 0x1000>; - ranges = <0x0200 0x0 0x8000 0x8000 0x0 0x1000 - 0x4200 0x0

Re: [PATCH 0/5] Live patching for powerpc

On Thu, 2016-04-14 at 16:34 +0200, Jiri Kosina wrote: > On Thu, 14 Apr 2016, Torsten Duwe wrote: > > > > > > It's unchanged since the version I posted on March 24, with the > > > > > > exception that > > > > > > I've dropped the first patch, which was a testing-only patch. > > > > Confirmed. And

[PATCH v2 1/1] powerpc/86xx: Set the right interrupt-cells for pcie nodes

Commit 595207b93fe4 ("powerpc/86xx: Update device tree") removes wrongly #interrupt-cells from pcie nodes. Fix it letting these come back to the right place. Signed-off-by: Alessio Igor Bogani --- v1 -> v2 Move #interrupt-cells on the pcie child-node to avoid

[PATCH v2 1/5] powerpc/85xx: support sleep feature on QorIQ SoCs with RCPM

In sleep mode, the clocks of e500 cores and unused IP blocks is turned off. The IP blocks which are allowed to wake up the processor are still running. The sleep mode is equal to the Standby state in Linux. Use the command to enter sleep mode: echo standby > /sys/power/state Signed-off-by:

[PATCH v2 4/5] powerpc/pm: support deep sleep feature on T104x

T104x has deep sleep feature, which can switch off most parts of the SoC when it is in deep sleep mode. This way, it becomes more energy-efficient. The DDR controller will also be powered off in deep sleep. Therefore, the last stage (the latter part of fsl_dp_enter_low) will run without DDR

[PATCH v2 5/5] powerpc/pm: save and restore registers during deep sleep

Some CCSR registers will lost during deep sleep. Therefore, should save them before entering deep sleep, and restore them when resuming from deep sleep. Signed-off-by: Tang Yuantian Signed-off-by: Chenhui Zhao --- arch/powerpc/include/asm/fsl_pm.h

[PATCH v2 0/5] powerpc/pm: QorIQ deep sleep

Changes for v2: * Ioremap every dts node used in the patches. * Check the board compatible string to see if the board supports deep sleep. * Can not reserve the first page of DDR memory, because PPC64 doesn't support changing the kernel base address. So still save and restore the first 128

[PATCH v2 2/5] powerpc: pm: add EPU FSM configuration for deep sleep

In the last stage of deep sleep, software will trigger a Finite State Machine (FSM) to control the hardware precedure, such as board isolation, killing PLLs, removing power, and so on. When the system is waked up by an interrupt, the FSM controls the hardware to complete the early resume

Re: [PATCH 0/5] Live patching for powerpc

On Thu, 2016-04-14 at 11:41 -0500, Josh Poimboeuf wrote: > On Thu, Apr 14, 2016 at 05:20:29PM +0200, Torsten Duwe wrote: > > On Thu, Apr 14, 2016 at 11:08:02PM +1000, Michael Ellerman wrote: > > > On Thu, 2016-04-14 at 14:57 +0200, Torsten Duwe wrote: > > > > FTR: then I still have a few ppc64

[PATCH] powerpc/dts: fix rcpm compatible string

For T1040, T1042, T1023, and T1024, they should use the compatible string "fsl,qoriq-rcpm-2.1". Signed-off-by: Chenhui Zhao --- arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 2 +- arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 2 +- 2 files changed, 2 insertions(+), 2

[PATCH v2 3/5] powerpc/dts: add a compatible string to gpio0

All gpio nodes used the same compatible string "fsl,qoriq-gpio". To identify the node corresponding to the GPIO1 pins, add a compatible string "fsl,qoriq-gpio-1". Signed-off-by: Chenhui Zhao --- arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi | 2 +- 1 file changed, 1

Re: [v4, 2/3] ppc64/book3s: make some room for common interrupt vector code

Hi Hari, Thanks for persisting with this. On Thu, 2016-07-04 at 21:58:50 UTC, Hari Bathini wrote: > With the previous patch, we choke out whatever little space is left > below 0x7000 (FWNMI hard block) while there is a hole of ~1400 bytes > below __end_interrupts marker when CONFIG_CBE_RAS is

Re: [PATCH 3/3] powerpc: Load Monitor Register Tests

On Tuesday 12 April 2016 12:27 AM, Jack Miller wrote: > Adds two tests. One is a simple test to ensure that the new registers > LMRR and LMSER are properly maintained. The other actually uses the > existing EBB test infrastructure to test that LMRR and LMSER behave as > documented. > >

Re: Live patching for powerpc

On Fri, 2016-04-15 at 10:28 +0200, Miroslav Benes wrote: > On Thu, 14 Apr 2016, Jessica Yu wrote: > > For the 32-bit module code, I don't believe we would need to preserve > > the .init.plt section for livepatch's call to apply_relocate_add(), > > since relocations to init sections should've been

Re: Live patching for powerpc

On Thu, 14 Apr 2016, Jessica Yu wrote: > +++ Miroslav Benes [14/04/16 15:28 +0200]: > > On Wed, 13 Apr 2016, Jessica Yu wrote: > > > > A second concern I have is that apply_relocate_add() relies on > > > sections like .stubs and .toc (for 64-bit) and .init.plt and .plt > > > sections (for

Re: [RFC PATCH 1/1] powerpc/fsl: Fix build of the dtb embedded kernel images

Hi, On 6 April 2016 at 15:45, Alessio Igor Bogani wrote: > The commit dc37374 move a lot of device tree files into fsl directory > fixing Makefile for cuImage target only. Unfortunately there are others > target which require to embebbed device tree into the kernel

[PATCH 1/1] powerpc/86xx: Set the right interrupt-cells for pcie nodes

Commit 595207b93fe4 ("powerpc/86xx: Update device tree") removes wrongly #interrupt-cells from pcie nodes. Fix it letting these come back to the right place. Signed-off-by: Alessio Igor Bogani --- arch/powerpc/boot/dts/fsl/gef_sbc310.dts | 1 +

Re: [PATCH kernel v3 9/9] powerpc/powernv/npu: Enable NVLink pass through

On Tue, Apr 12, 2016 at 06:37:50PM +1000, Alexey Kardashevskiy wrote: > IBM POWER8 NVlink systems come with Tesla K40-ish GPUs each of which > also has a couple of fast speed links (NVLink). The interface to links > is exposed as an emulated PCI bridge which is included into the same > IOMMU group

[PATCH v2 2/2] cpufreq: powernv: Ramp-down global pstate slower than local-pstate

The frequency transition latency from pmin to pmax is observed to be in few millisecond granurality. And it usually happens to take a performance penalty during sudden frequency rampup requests. This patch set solves this problem by using an entity called "global pstates". The global pstate is a

[PATCH v2 1/2] cpufreq: powernv: Remove flag use-case of policy->driver_data

From: Shilpasri G Bhat commit 1b0289848d5d ("cpufreq: powernv: Add sysfs attributes to show throttle stats") used policy->driver_data as a flag for one-time creation of throttle sysfs files. Instead of this use 'kernfs_find_and_get()' to check if the attribute

[PATCH v2 0/2] cpufreq: powernv: Ramp-down global pstate slower than local-pstate

The frequency transition latency from pmin to pmax is observed to be in few millisecond granurality. And it usually happens to take a performance penalty during sudden frequency rampup requests. This patch set solves this problem by using a chip-level entity called "global pstates". Global