Re: [PATCH v2 1/9] powerpc/powernv: Move CHECK_HMI_INTERRUPT to exception-64s header

On Tue, May 03, 2016 at 01:54:30PM +0530, Shreyas B. Prabhu wrote: > CHECK_HMI_INTERRUPT is used to check for HMI's in reset vector. Move > the macro to a common location (exception-64s.h) > This patch does not change any functionality. > I suppose this code movement is to facilitate the

[PATCH v6] powerpc/pci: Assign fixed PHB number based on device-tree properties

The domain/PHB field of PCI addresses has its value obtained from a global variable, incremented each time a new domain (represented by struct pci_controller) is added on the system. The domain addition process happens during boot or due to PHB hotplug add. As recent kernels are using predictable

[PATCH 4/4] powerpc/sparse: Use LE definition of REG_BYTE

Sparse complains that it doesn't know what REG_BYTE is: arch/powerpc/kernel/align.c:313:29: error: undefined identifier 'REG_BYTE' arch/powerpc/kernel/align.c:320:37: error: undefined identifier 'REG_BYTE' arch/powerpc/kernel/align.c:328:29: error: cast from unknown type

[PATCH 3/4] powerpc/sparse: Include headers containing prototypes

Sometimes headers that provide prototypes for functions are accidentally omitted from the files that define the functions. Fix a couple of times that occurs. Signed-off-by: Daniel Axtens --- arch/powerpc/kernel/smp.c | 1 + arch/powerpc/platforms/pseries/power.c |

[PATCH 2/4] powerpc: Introduce asm-prototypes.h

Sparse picked up a number of functions that are implemented in C and then only referred to in asm code. This introduces asm-prototypes.h, which provides a place for prototypes of these functions. This silences some sparse warnings. Signed-off-by: Daniel Axtens ---

[PATCH 1/4] powerpc/sparse: make some things static

This is just a smattering of things picked up by sparse that should be made static. Signed-off-by: Daniel Axtens --- arch/powerpc/kernel/crash.c | 2 +- arch/powerpc/kernel/sysfs.c | 2 +- arch/powerpc/platforms/powernv/idle.c |

Re: usb: dwc2: regression on MyBook Live Duo / Canyonlands since 4.3.0-rc4

On 5/14/2016 6:11 AM, Christian Lamparter wrote: > On Thursday, May 12, 2016 11:40:28 AM John Youn wrote: >> On 5/12/2016 6:30 AM, Christian Lamparter wrote: >>> On Thursday, May 12, 2016 01:55:44 PM Arnd Bergmann wrote: On Thursday 12 May 2016 11:58:18 Christian Lamparter wrote:

Re: livepatch: change to a per-task consistency model

+++ Josh Poimboeuf [28/04/16 15:44 -0500]: [snip] diff --git a/Documentation/livepatch/livepatch.txt b/Documentation/livepatch/livepatch.txt index 6c43f6e..bee86d0 100644 --- a/Documentation/livepatch/livepatch.txt +++ b/Documentation/livepatch/livepatch.txt @@ -72,7 +72,8 @@ example, they

[RFC PATCH 3/3] arch/powerpc : Enable optprobes support in powerpc

Signed-off-by: Anju T --- Documentation/features/debug/optprobes/arch-support.txt | 2 +- arch/powerpc/Kconfig| 1 + arch/powerpc/kernel/Makefile| 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff

[RFC PATCH 2/3] arch/powerpc : optprobes for powerpc core

Instruction slot for detour buffer is allocated from the reserved area. For the time being 64KB is reserved in memory for this purpose. ppc_get_optinsn_slot() and ppc_free_optinsn_slot() are geared towards the allocation and freeing of memory from this area. Signed-off-by: Anju T

[RFC PATCH 1/3] arch/powerpc : Add detour buffer support for optprobes

Detour buffer contains instructions to create an in memory pt_regs. After the execution of prehandler a call is made for instruction emulation. The NIP is decided after the probed instruction is executed. Hence a branch instruction is created to the NIP returned by emulate_step(). Signed-off-by:

Re: [PATCH v2 1/7] powerpc/8xx: Fix vaddr for IMMR early remap

Le 17/05/2016 à 01:11, Scott Wood a écrit : On Fri, 2016-05-13 at 11:25 +0200, Christophe Leroy wrote: Le 11/05/2016 à 22:38, Scott Wood a écrit : On Wed, 2016-05-11 at 17:03 +0200, Christophe Leroy wrote: Memory: 124428K/131072K available (3748K kernel code, 188K rwdata, 648K rodata, 508K

Re: [PATCH] kvm-pr: manage illegal instructions

On 17/05/2016 10:37, Alexander Graf wrote: > On 05/17/2016 10:35 AM, Laurent Vivier wrote: >> >> On 12/05/2016 16:23, Laurent Vivier wrote: >>> >>> On 12/05/2016 11:27, Alexander Graf wrote: On 05/12/2016 11:10 AM, Laurent Vivier wrote: > On 11/05/2016 13:49, Alexander Graf wrote:

for muram in DTS file, why change #address-cells from <1> to <2>?

currently working on a project involving MPC8360 board, and was handed a patch to the system .dts file that contained the following snippet for the muram node: muram@1 { - #address-cells = <1>; + #address-cells = <2>;

[PATCH v3 2/2] powerpc32: fix check_io_access()

On processors like the 8xx, the machine check exception can also happen directly on the load/store instruction itself, so that case needs to be handled as well Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/ppc-opcode.h | 1 + arch/powerpc/kernel/traps.c

[PATCH v3 1/2] powerpc32: Use instruction symbolic names in check_io_access()

Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/ppc-opcode.h | 1 + arch/powerpc/kernel/traps.c | 7 +++ 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/include/asm/ppc-opcode.h

Re: [PATCH] kvm-pr: manage illegal instructions

On 05/17/2016 10:35 AM, Laurent Vivier wrote: On 12/05/2016 16:23, Laurent Vivier wrote: On 12/05/2016 11:27, Alexander Graf wrote: On 05/12/2016 11:10 AM, Laurent Vivier wrote: On 11/05/2016 13:49, Alexander Graf wrote: On 05/11/2016 01:14 PM, Laurent Vivier wrote: On 11/05/2016 12:35,

Re: [PATCH] kvm-pr: manage illegal instructions

On 12/05/2016 16:23, Laurent Vivier wrote: > > > On 12/05/2016 11:27, Alexander Graf wrote: >> On 05/12/2016 11:10 AM, Laurent Vivier wrote: >>> >>> On 11/05/2016 13:49, Alexander Graf wrote: On 05/11/2016 01:14 PM, Laurent Vivier wrote: > On 11/05/2016 12:35, Alexander Graf wrote:

[PATCH v2 6/6] powerpc: pseries: pv-qspinlock build config/make

pseries can use pv-qspinlock. Signed-off-by: Pan Xinhui --- arch/powerpc/kernel/Makefile | 1 + arch/powerpc/platforms/pseries/Kconfig | 8 2 files changed, 9 insertions(+) diff --git a/arch/powerpc/kernel/Makefile

[PATCH v2 5/6] pv-qspinlock: use cmpxchg_release in __pv_queued_spin_unlock

cmpxchg_release is lighter, we can gain a better performace then. Suggested-by: Boqun Feng Signed-off-by: Pan Xinhui --- kernel/locking/qspinlock_paravirt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH v2 4/6] pv-qspinlock: powerpc support pv-qspinlock

As we need let pv-qspinlock-kernel run on all environment which might have no powervm, we should runtime choose which qspinlock version to use. The default pv-qspinlock use native version. pv_lock initialization should be done in bootstage with irq disabled. And if possible, restore pv_lock_ops

[PATCH v2 3/6] powerpc: lib/locks.c: cpu yield/wake helper function

pv-qspinlock core has pv_wait/pv_kick which will give a better performace by yielding and kicking cpu at some cases. lets support them by adding two corresponding helper functions. Signed-off-by: Pan Xinhui --- arch/powerpc/include/asm/spinlock.h | 4

[PATCH v2 2/6] powerpc: pseries/Kconfig: qspinlock build config

pseries will use qspinlock by default. Signed-off-by: Pan Xinhui --- arch/powerpc/platforms/pseries/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig index bec90fb..f669323

[PATCH v2 1/6] qspinlock: powerpc support qspinlock

Base code to enable qspinlock on powerpc. this patch add some #ifdef here and there. Although there is no paravirt related code, we can successfully build a qspinlock kernel after apply this patch. Signed-off-by: Pan Xinhui --- arch/powerpc/include/asm/qspinlock.h

[PATCH v3 0/6] powerpc use pv-qpsinlock instead of spinlock

change fome v1: separate into 6 pathes from one patch some minor code changes. benchmark test results are below. run 3 tests on pseries IBM,8408-E8E with 32cpus, 64GB memory perf bench futex hash perf bench futex lock-pi perf record -advRT || perf bench sched messaging -g 1000 ||

[PATCH 2/2] powerpc/SROP mitigation: Add cookies to sigframes

This patch adds SROP mitigation logic to the powerpc signal delivery and sigreturn code. The cookie is placed in the sigframe just after (at a lower address) the ABI gap. This is derived from the x86 SROP mitigation patch: https://lkml.org/lkml/2016/3/29/791. Signed-off-by: Rashmica Gupta

[PATCH 1/2] powerpc/SROP Mitigation: Architecture independent SROP mitigation code

This is based off Scotty's patch: https://lkml.org/lkml/2016/3/29/792. The only difference being that the sig_cookie is apart of the struct sighand_struct instead of task_struct so the the sig_cookie is shared between threads. Signed-off-by: Rashmica Gupta --- fs/exec.c

[RFC 0/2] SROP Mitigation for powerpc

This is all derived from Scott Bauer's x86 patches (https://lkml.org/lkml/2016/3/29/788). Have tested rc5 with these patches on: - BE VM - BE bare metal - LE VM - LE bare metal with the Linux Test Project runltp test script with all default configs. From rc5 to

[PATCH v3 6/7] powerpc/8xx: Rework CONFIG_PIN_TLB handling

On recent kernels, with some debug options like for instance CONFIG_LOCKDEP, the BSS requires more than 8M memory, allthough the kernel code fits in the first 8M. Today, it is necessary to activate CONFIG_PIN_TLB to get more than 8M at startup, allthough pinning TLB is not necessary for that. We

[PATCH v3 7/7] powerpc/8xx: add CONFIG_PIN_TLB_IMMR

CONFIG_PIN_TLB maps IMMR area and the first 24 Mbytes of memory. In some circunstances it might be more interesting to not map IMMR but map 32 Mbytes of memory instead. Therefore we add config option CONFIG_PIN_TLB_IMMR to select if IMMR shall be pinned or not, hence whether we pin 24 or 32

[PATCH v3 5/7] powerpc/8xx: Don't use page table for linear memory space

Instead of using the first level page table to define mappings for the linear memory space, we can use direct mapping from the TLB handling routines. This has several advantages: * No need to read the tables at each TLB miss * No issue in 16k pages mode where the 1st level table maps 64 Mbytes

[PATCH v3 4/7] powerpc/8xx: unpin all TLBs before flushing

Bootloader may have pinned some TLB entries so the kernel must unpin them before flushing TLBs with tlbia otherwise pinned TLB entries won't get flushed Signed-off-by: Christophe Leroy --- v2: No change v3: No change arch/powerpc/kernel/head_8xx.S | 18

[PATCH v3 3/7] powerpc/8xx: CONFIG_PIN_TLB unneeded for CONFIG_PPC_EARLY_DEBUG_CPM

IMMR is now mapped by a fixed 512k page managed by the TLB miss handler so it is not anymore necessary to PIN TLBs Signed-off-by: Christophe Leroy --- v2: No change v3: No change arch/powerpc/Kconfig.debug | 1 - 1 file changed, 1 deletion(-) diff --git

[PATCH v3 2/7] powerpc/8xx: Map IMMR area with 512k page at a fixed address

Once the linear memory space has been mapped with 8Mb pages, as seen in the related commit, we get 11 millions DTLB missed during the reference 600s period. 77% of the misses are on user addresses and 23% are on kernel addresses (1 fourth for linear address space and 3 fourth for virtual address

[PATCH v3 1/7] powerpc/8xx: Fix vaddr for IMMR early remap

Memory: 124428K/131072K available (3748K kernel code, 188K rwdata, 648K rodata, 508K init, 290K bss, 6644K reserved) Kernel virtual memory layout: * 0xfffdf000..0xf000 : fixmap * 0xfde0..0xfe00 : consistent mem * 0xfddf6000..0xfde0 : early ioremap *

[PATCH v3 0/7] powerpc/8xx: Optimisation of TLB handling for IMMR and RAM

The purpose of this set of patches is to continue on TLB handling optimisation on the 8xx with the handling of IMMR area as a single 512k area instead of multiple 4k pages. This set includes a rework of linear RAM mapping in order to not use page table but direct linear mapping. The result is

[PATCH RESEND v8] powerpc32: provide VIRT_CPU_ACCOUNTING

This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture. PPC32 doesn't have the PACA structure, so we use the task_info structure to store the accounting data. In order to reuse on PPC32 the PPC64 functions, all u64 data has been replaced by 'unsigned long' so that it is u32 on PPC32 and u64