[PATCH 00/21] Delete CURRENT_TIME and CURRENT_TIME_SEC macros

The series is aimed at getting rid of CURRENT_TIME and CURRENT_TIME_SEC macros. The macros are not y2038 safe. There is no plan to transition them into being y2038 safe. ktime_get_* api's can be used in their place. And, these are y2038 safe. All filesystem timestamps use current_fs_time() for

Re: [PATCH, RFC] cxl: Add support for CAPP DMA mode

Ian Munsie writes: > From: Ian Munsie > > This adds support for using CAPP DMA mode, which is required for XSL > based cards such as the Mellanox CX4 to function. > > This is currently an RFC as it depends on the corresponding support to > be merged

Re: [PATCH 2/5] selftests/powerpc: Add test to check TM ucontext creation

I'm trying not to be too nit picky or difficult on tests, so here's a pre-written commit message for you: "The kernel sets up two sets of ucontexts if the signal was to be delivered while the thread was in a transaction. Expected behaviour is that the currently executing code is in the first and

Re: [PATCH v5 08/11] powerpc/powernv: Add platform support for stop instruction

On Thu, Jun 02, 2016 at 07:38:58AM -0500, Shreyas B. Prabhu wrote: ... > +/* Power Management - PSSCR Fields */ It might be nice to give the full name of the register, as below with the FPSCR. > +#define PSSCR_RL_MASK0x000F > +#define PSSCR_MTL_MASK 0x00F0

Re: [PATCH] powerpc/mm: Use jump label to speed up radix_enabled check

On Wed, 2016-04-27 at 12:30 +0530, Aneesh Kumar K.V wrote: > Benjamin Herrenschmidt writes: > > > > > On Wed, 2016-04-27 at 11:00 +1000, Balbir Singh wrote: > > > > > > Just basic testing across CPUs with various mm features  > > > enabled/disabled. Just for sanity >

Re: [PATCH 6/6] ppc: ebpf/jit: Implement JIT compiler for extended BPF

Naveen, can you point out where in the patch you update the variable: idx, a member of codegen_contex structure? Somehow I am unable to figure it out. I can only see that we set it to 0 in the bpf_int_jit_compile function. Since all your test cases pass, I am clearly overlooking something.

Re: [PATCH 1/5] selftests/powerpc: Check for VSX preservation across userspace preemption

On Thu, 2016-06-09 at 11:35 +1000, Daniel Axtens wrote: > > +/* > > + * Copyright 2015, Cyril Bur, IBM Corp. > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License > > + * as published by the Free Software

[PATCH v7 3/3] powerpc: Load Monitor Register Tests

From: Jack Miller Adds two tests. One is a simple test to ensure that the new registers LMRR and LMSER are properly maintained. The other actually uses the existing EBB test infrastructure to test that LMRR and LMSER behave as documented. Signed-off-by: Jack Miller

[PATCH v7 2/3] powerpc: Load Monitor Register Support

From: Jack Miller This enables new registers, LMRR and LMSER, that can trigger an EBB in userspace code when a monitored load (via the new ldmx instruction) loads memory from a monitored space. This facility is controlled by a new FSCR bit, LM. This patch disables the FSCR LM

[PATCH v7 1/3] powerpc: Improve FSCR init and context switching

This fixes a few issues with FSCR init and switching. In this patch: powerpc: Create context switch helpers save_sprs() and restore_sprs() Author: Anton Blanchard commit 152d523e6307c7152f9986a542f873b5c5863937 We moved the setting of the FSCR register from inside an

[PATCH v7 0/3] POWER9 Load Monitor Support

This patches series adds support for the POWER9 Load Monitor instruction (ldmx) based on work from Jack Miller. The first patch is a clean up of the FSCR handling. The second patch adds the actual ldmx support to the kernel. The third patch is a couple of ldmx selftests. v7: - Suggestions from

Re: [PATCH 1/5] selftests/powerpc: Check for VSX preservation across userspace preemption

Yay for tests! I have a few minor nits, and one more major one (rc == 2 below). > +/* > + * Copyright 2015, Cyril Bur, IBM Corp. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the

Re: [RFC] Implementing HUGEPAGE on MPC 8xx

On Wed, 2016-06-08 at 09:03 +0200, Christophe Leroy wrote: > In see in the current ppc kernel that for PPC32, SYS_SUPPORTS_HUGETLBFS > is selected only if we have PHYS_64BIT. > What is the reason for only implementing HUGETLBFS with 64 bits phys > addresses ? That's not for PPC32 in general --

Re: [PATCH] powerpc/nohash: Fix build break with 4K pages

On Wed, 2016-06-08 at 20:19 +0530, Aneesh Kumar K.V wrote: > Michael Ellerman writes: > > > Commit 74701d5947a6 "powerpc/mm: Rename function to indicate we are > > allocating fragments" renamed page_table_free() to pte_fragment_free(). > > One occurrence was mistyped as

Re: [PATCH v12 01/15] PCI: Let pci_mmap_page_range() take extra resource pointer

On Wed, Jun 8, 2016 at 3:35 PM, Yinghai Lu wrote: > At the same time, can you kill __pci_mmap_set_pgprot() for powerpc. Can you please put your two patches and this attached one into to pci/next? Then I could send updated PCI: Let pci_mmap_page_range() take resource

Re: [RFC] Implementing HUGEPAGE on MPC 8xx

Hello Christophe. I’m surprised there is still any interest in this processor family :) On Jun 8, 2016, at 12:03 AM, Christophe Leroy wrote: > MPC 8xx has several page sizes: 4k, 16k, 512k and 8M. > Today, 4k and 16k sizes are implemented as normal page sizes and 8M

[PATCH v3 3/7] powerpc: use the new LED disk activity trigger

- dts: rename 'ide-disk' to 'disk-activity' - defconfig: rename 'ADB_PMU_LED_IDE' to 'ADB_PMU_LED_DISK' Cc: Joseph Jezak Cc: Nico Macrionitis Cc: Jörg Sommer Signed-off-by: Stephan Linz ---

Re: [PATCH v5 08/11] powerpc/powernv: Add platform support for stop instruction

On Wed, 2016-06-08 at 22:31 +0530, Shreyas B Prabhu wrote: > Hi Ben, > > Sorry for the delayed response. > > On 06/06/2016 03:58 AM, Benjamin Herrenschmidt wrote: > > > > On Thu, 2016-06-02 at 07:38 -0500, Shreyas B. Prabhu wrote: > > > > > > @@ -61,8 +72,13 @@ save_sprs_to_stack: > > >    

Re: [PATCH v12 01/15] PCI: Let pci_mmap_page_range() take extra resource pointer

On Fri, Jun 03, 2016 at 05:06:28PM -0700, Yinghai Lu wrote: > This one is preparing patch for next one: > PCI: Let pci_mmap_page_range() take resource addr > > We need to pass extra resource pointer to avoid searching that again > for powerpc and microblaze prot set operation. I'm not

Re: [PATCH V2 1/7] dt-bindings: Update QorIQ TMU thermal bindings

On Tue, Jun 07, 2016 at 11:27:34AM +0800, Jia Hongtao wrote: > For different types of SoC the sensor id and endianness may vary. > "#thermal-sensor-cells" is used to provide sensor id information. > "little-endian" property is to tell the endianness of TMU. > > Signed-off-by: Jia Hongtao

Re: [PATCH] drivers/net/fsl_ucc: Do not prefix header guard with CONFIG_

From: Andreas Ziegler Date: Wed, 8 Jun 2016 11:40:28 +0200 > The CONFIG_ prefix should only be used for options which > can be configured through Kconfig and not for guarding headers. > > Signed-off-by: Andreas Ziegler Applied.

Re: [PATCH 6/6] ppc: ebpf/jit: Implement JIT compiler for extended BPF

On 2016/06/07 03:56PM, Alexei Starovoitov wrote: > On Tue, Jun 07, 2016 at 07:02:23PM +0530, Naveen N. Rao wrote: > > PPC64 eBPF JIT compiler. > > > > Enable with: > > echo 1 > /proc/sys/net/core/bpf_jit_enable > > or > > echo 2 > /proc/sys/net/core/bpf_jit_enable > > > > ... to see the

Re: [PATCH v5 08/11] powerpc/powernv: Add platform support for stop instruction

Hi Ben, Sorry for the delayed response. On 06/06/2016 03:58 AM, Benjamin Herrenschmidt wrote: > On Thu, 2016-06-02 at 07:38 -0500, Shreyas B. Prabhu wrote: >> @@ -61,8 +72,13 @@ save_sprs_to_stack: >> * Note all register i.e per-core, per-subcore or per-thread is saved >> *

[PATCH v6 11/11] powerpc/powernv: Use deepest stop state when cpu is offlined

If hardware supports stop state, use the deepest stop state when the cpu is offlined. Reviewed-by: Gautham R. Shenoy Signed-off-by: Shreyas B. Prabhu --- - No changes since v1 arch/powerpc/platforms/powernv/idle.c| 15 +--

[PATCH v6 10/11] cpuidle/powernv: Add support for POWER ISA v3 idle states

POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction. Supported idle states and value to be written to PSSCR register to enter any idle

[PATCH v6 09/11] cpuidle/powernv: Use CPUIDLE_STATE_MAX instead of MAX_POWERNV_IDLE_STATES

Use cpuidle's CPUIDLE_STATE_MAX macro instead of powernv specific MAX_POWERNV_IDLE_STATES. Cc: Rafael J. Wysocki Cc: Daniel Lezcano Cc: linux...@vger.kernel.org Suggested-by: Daniel Lezcano Signed-off-by: Shreyas

[PATCH v6 05/11] powerpc/powernv: Make pnv_powersave_common more generic

pnv_powersave_common does common steps needed before entering idle state and eventually changes MSR to MSR_IDLE and does rfid to pnv_enter_arch207_idle_mode. Move the updation of HSTATE_HWTHREAD_STATE to pnv_powersave_common from pnv_enter_arch207_idle_mode and make it more generic by passing the

[PATCH v6 08/11] powerpc/powernv: Add platform support for stop instruction

POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named Processor Stop Status and Control Register (PSSCR) is added which controls

[PATCH v6 06/11] powerpc/powernv: abstraction for saving SPRs before entering deep idle states

Create a function for saving SPRs before entering deep idle states. This function can be reused for POWER9 deep idle states. Reviewed-by: Gautham R. Shenoy Signed-off-by: Shreyas B. Prabhu --- - No changes since v3 Changes in v3:

[PATCH v6 07/11] powerpc/powernv: set power_save func after the idle states are initialized

pnv_init_idle_states discovers supported idle states from the device tree and does the required initialization. Set power_save function pointer only after this initialization is done Reviewed-by: Gautham R. Shenoy Signed-off-by: Shreyas B. Prabhu

[PATCH v6 01/11] powerpc/powernv: Use PNV_THREAD_WINKLE macro while requesting for winkle

Signed-off-by: Shreyas B. Prabhu --- -No changes since v4 Changes in v4 = - New in v4 arch/powerpc/kernel/idle_power7.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/idle_power7.S

[PATCH v6 03/11] powerpc/powernv: Rename idle_power7.S to idle_power_common.S

idle_power7.S handles idle entry/exit for POWER7, POWER8 and in next patch for POWER9. Rename the file to a non-hardware specific name. Reviewed-by: Gautham R. Shenoy Signed-off-by: Shreyas B. Prabhu --- - No changes since v3 Changes in v3:

[PATCH v6 04/11] powerpc/powernv: Rename reusable idle functions to hardware agnostic names

Functions like power7_wakeup_loss, power7_wakeup_noloss, power7_wakeup_tb_loss are used by POWER7 and POWER8 hardware. They can also be used by POWER9. Hence rename these functions hardware agnostic names. Suggested-by: Gautham R. Shenoy Signed-off-by: Shreyas B. Prabhu

[PATCH v6 02/11] powerpc/kvm: make hypervisor state restore a function

In the current code, when the thread wakes up in reset vector, some of the state restore code and check for whether a thread needs to branch to kvm is duplicated. Reorder the code such that this duplication is avoided. At a higher level this is what the change looks like- Before this patch -

[PATCH v6 00/11] powerpc/powernv/cpuidle: Add support for POWER ISA v3 idle states

POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction.

Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

Hi Aneesh, We use it only in the file "pci-common.c". Part of the Nemo patch with ISA_IO_BASE: diff -rupN linux-4.7/arch/powerpc/kernel/pci-common.c linux-4.7-nemo/arch/powerpc/kernel/pci-common.c --- linux-4.7/arch/powerpc/kernel/pci-common.c2016-05-20 10:23:06.588299920 +0200 +++

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

Darren Stevens writes: > Hello Christian > That's not where I ended up with my bisect, this commit is about 10 before the > one I found to be bad, which is: > > commit d6a9996e84ac4beb7713e9485f4563e100a9b03e > Author: Aneesh Kumar K.V

[PATCH V2 16/16] powerpc/mm: Support segment table for Power9

PowerISA 3.0 adds an in memory table for storing segment translation information. In this mode, which is enabled by setting both HOST RADIX and GUEST RADIX bits in partition table to 0 and enabling UPRT to 1, we have a per process segment table. The segment table details are stored in the process

Re: [PATCH V2 16/16] powerpc/mm: Support segment table for Power9

"Aneesh Kumar K.V" writes: > PowerISA 3.0 adds an in memory table for storing segment translation > information. In this mode, which is enabled by setting both HOST RADIX > and GUEST RADIX bits in partition table to 0 and enabling UPRT to > 1, we have a per

Re: [PATCH] powerpc/nohash: Fix build break with 4K pages

Michael Ellerman writes: > Commit 74701d5947a6 "powerpc/mm: Rename function to indicate we are > allocating fragments" renamed page_table_free() to pte_fragment_free(). > One occurrence was mistyped as pte_fragment_fre(). > > This only breaks the nohash 4K page build, which

[PATCH V2 15/16] powerpc/mm: Switch user slb fault handling to translation enabled

We also handle fault with proper stack initialized. This enable us to callout to C in fault handling routines. We don't do this for kernel mapping, because of the possibility of taking recursive fault if kernel stack in not yet mapped by an slb entry. This enable us to handle Power9 slb fault

[PATCH V2 14/16] powerpc/mm: Cleanup LPCR defines

This makes it easy to verify we are not overloading the bits. No functionality change by this patch. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/reg.h | 54 +- 1 file changed, 27 insertions(+), 27

[PATCH V2 13/16] powerpc/mm: remove flush_tlb_page_nohash

This should be same as flush_tlb_page except for hash32. For hash32 I guess the existing code is wrong, because we don't seem to be flushing tlb for Hash != 0 case at all. Fix this by switching to calling flush_tlb_page() which does the right thing by flushing tlb for both hash and nohash case

[PATCH V2 12/16] powerpc/mm/hugetlb: Add flush_hugetlb_tlb_range

Some archs like ppc64 need to do special things when flushing tlb for hugepage. Add a new helper to flush hugetlb tlb range. This helps us to avoid flushing the entire tlb mapping for the pid. Signed-off-by: Aneesh Kumar K.V ---

[PATCH V2 11/16] powerpc/mm/radix/hugetlb: Add helper for finding page size from hstate

Use the helper instead of open coding the same at multiple place Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hugetlb-radix.h | 15 +++ .../powerpc/include/asm/book3s/64/tlbflush-radix.h | 4 +--

[PATCH V2 10/16] powerpc/mm/radix: Rename function and drop unused arg

Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 10 +- arch/powerpc/mm/hugetlbpage-radix.c | 4 ++-- arch/powerpc/mm/tlb-radix.c | 16 3 files changed, 15

[PATCH V2 09/16] powerpc/mm/radix: Add tlb flush of THP ptes

Instead of flushing the entire mm, implement a flush_pmd_tlb_range Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 2 ++ arch/powerpc/include/asm/book3s/64/tlbflush.h | 9 +

[PATCH V2 08/16] powerpc/mm: Drop multiple definition of mm_is_core_local

Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/tlb.h | 13 + arch/powerpc/mm/tlb-radix.c| 6 -- arch/powerpc/mm/tlb_nohash.c | 6 -- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git

[PATCH V2 07/16] powerpc/mm: Use hugetlb flush functions

Use flush_hugetlb_page instead of flush_tlb_page when we clear flush the pte. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/hugetlb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/hugetlb.h

[PATCH V2 06/16] powerpc/mm/hash: Add helper for finding SLBE LLP encoding

Replace opencoding of the same at multiple places with the helper. No functional change with this patch. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/mmu-hash.h | 9 + arch/powerpc/include/asm/kvm_book3s_64.h | 3 +--

[PATCH V2 05/16] powerpc/mm: Make MMU_FTR_RADIX a MMU family feature

MMU feature bits are defined such that we use the lower half to present MMU family features. Remove the strict split of half and also move Radix to a mmu family feature. Radix introduce a new MMU model and strictly speaking it is a new MMU family. This also free up bits which can be used for

[PATCH V2 04/16] powerpc/mm/radix: Implement tlb mmu gather flush efficiently

Now that we track page size in mmu_gather, we can use address based tlbie format when doing a tlb_flush(). We don't do this if we are invalidating the full address space. Signed-off-by: Aneesh Kumar K.V --- .../powerpc/include/asm/book3s/64/tlbflush-radix.h | 2

[PATCH V2 03/16] mm/mmu_gather: Track page size with mmu gather and force flush if page size change

This allows arch which need to do special handing with respect to different page size when flushing tlb to implement the same in mmu gather Signed-off-by: Aneesh Kumar K.V --- arch/arm/include/asm/tlb.h | 12 arch/ia64/include/asm/tlb.h | 12

[PATCH V2 02/16] mm: Change the interface for __tlb_remove_page

This update the generic and arch specific implementation to return true if we need to do a tlb flush. That means if a __tlb_remove_page indicate a flush is needed, the page we try to remove need to be tracked and added again after the flush. We need to track it because we have already update the

[PATCH V2 01/16] mm/hugetlb: Simplify hugetlb unmap

For hugetlb like THP (and unlike regular page), we do tlb flush after dropping ptl. Because of the above, we don't need to track force_flush like we do now. Instead we can simply call tlb_remove_page() which will do the flush if needed. No functionality change in this patch. Signed-off-by:

[PATCH V2 00/16] TLB flush improvments and Segment table support

This series include patches which got posted earlier as independent series. Some of this patches will go upstream via -mm tree. Changes from V1: * Address review feedback * rebase on top of radix fixes which got posted earlier * Fixes for segment table support. NOTE: Even though the patch

[PATCH V2 10/10] powerpc/mm/hash: Update SDR1 size encoding as documented in ISA 3.0

ISA 3.0 document hash table size in bytes = 2^(HTABSIZE + 18) No functionality change by this patch. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/hash_utils_64.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git

[PATCH V2 09/10] powerpc/mm: Print formation regarding the the MMU mode

This helps in easily identifying the MMU mode with which the kernel is operating. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/hash_utils_64.c | 3 ++- arch/powerpc/mm/pgtable-radix.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git

[PATCH V2 08/10] powerpc/mm: Clear top 16 bits of va only on older cpus

As per ISA, we need to do this only for architecture version 2.02 and earlier. This continued to work even for 2.07. But let's not do this for anything after 2.02 Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/mmu.h | 12 +---

[PATCH V2 07/10] powerpc/hash: Use the correct ppp mask when updating hpte

With commit: e58e87adc8bf9 ("powerpc/mm: Update _PAGE_KERNEL_RO") we now use all the three PPP bits. The top bit is now used to have a PPP value of 0b110 which will be mapped to kernel read only. When updating the hpte entry use right mask such that we update the 63rd bit (top 'P' bit) too.

[PATCH V2 06/10] powerpc/mm: Compile out radix related functions if RADIX_MMU is disabled

Currently we depend on mmu_has_feature to evalute to zero based on MMU_FTRS_POSSIBLE mask. In a later patch, we want to update radix_enabled() to runtime update the conditional operation to a jump instruction. This implies we cannot depend on MMU_FTRS_POSSIBLE mask. Instead define radix_enabled to

[PATCH V2 05/10] powerpc/mm: use _raw variant of page table accessors

This switch few of the page table accessor to use the __raw variant and does the cpu to big endian conversion of constants. This helps in generating better code. For ex: a pgd_none(pgd) check with and without fix is listed below Without fix: 2240:20 00 61 eb ld

[PATCH V2 04/10] powerpc/mm/radix: Update LPCR HR bit as per ISA

PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor to be mirrored in the LPCR register, in addition to the partition table. This is done to avoid fetching from the table when deciding, among other things, how to perform transitions to HV mode on some interrupts. So let's set it

[PATCH V2 03/10] powerpc/mm/radix: Flush page walk cache when freeing page table

Even though a tlb_flush() does a flush with invalidate all cache, we can end up doing an RCU page table free before calling tlb_flush(). That means we can have page walk cache entries even after we free the page table pages. This can result in us doing wrong page table walk. Avoid this by doing

[PATCH V2 02/10] powerpc/mm/radix: Update to tlb functions ric argument

Radix invalidate control (RIC) is used to control which cache to flush using tlb instructions. When doing a PID flush, we currently flush everything including page walk cache. For address range flush, we flush only the TLB. In the later patch, we add support for flushing only page walk cache.

[PATCH V2 00/10] Fixes for Radix support

Hi Michael, This series includes patches I had posted before. I collected them in a series and marked the series V2. This address the review feedback I received from last post. Aneesh Kumar K.V (9): powerpc/mm/radix: Update to tlb functions ric argument powerpc/mm/radix: Flush page walk

[PATCH V2 01/10] Fix .long's in mm/tlb-radix.c to more meaningful

From: Balbir Singh The .longs with the shifts are harder to read, use more meaningful names for the opcodes. PPC_TLBIE_5 is introduced for the 5 opcode variation of the instruction due to an existing op-code for the 2 opcode variant Signed-off-by: Balbir Singh

Re: [PATCH v3] powerpc: spinlock: Fix spin_unlock_wait()

On Wed, Jun 08, 2016 at 11:49:20PM +1000, Michael Ellerman wrote: > > Ok; what tree does this go in? I have this dependent series which I'd > > like to get sorted and merged somewhere. > > Ah sorry, I didn't realise. I was going to put it in my next (which doesn't > exist yet but hopefully will

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

On Wed, 2016-06-08 at 12:33 +0100, Darren Stevens wrote: > On 07/06/2016, Christian Zigotzky wrote: > > > > 764041e0f43cc7846f6d8eb246d65b53cc06c764 is the first bad commit > > commit 764041e0f43cc7846f6d8eb246d65b53cc06c764 > > Author: Aneesh Kumar K.V > > Date:

Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

Hi All, I tried to revert this commit but unfortunately I doesn't work: git revert d6a9996e84ac4beb7713e9485f4563e100a9b03e error: could not revert d6a9996... powerpc/mm: vmalloc abstraction in preparation for radix hint: after resolving the conflicts, mark the corrected paths hint: with

Re: [PATCH v3] powerpc: spinlock: Fix spin_unlock_wait()

On Wed, 2016-06-08 at 14:35 +0200, Peter Zijlstra wrote: > On Wed, Jun 08, 2016 at 09:20:45PM +1000, Michael Ellerman wrote: > > On Mon, 2016-06-06 at 16:46 +0200, Peter Zijlstra wrote: > > > On Mon, Jun 06, 2016 at 10:17:25PM +1000, Michael Ellerman wrote: > > > > On Mon, 2016-06-06 at 13:56

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

Hello Christian On 07/06/2016, Christian Zigotzky wrote: > "range.size, pgprot_val(pgprot_noncached(__pgprot(0;" isn't the > problem. :-) It works. > > 764041e0f43cc7846f6d8eb246d65b53cc06c764 is the first bad commit > commit 764041e0f43cc7846f6d8eb246d65b53cc06c764 > Author: Aneesh Kumar

Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

Hi Darren, Many thanks for your help. I started my bisect with the following commits: git bisect start git bisect good 8ffb4103f5e28d7e7890ed4774d8e009f253f56e git bisect bad 1a695a905c18548062509178b98bc91e67510864 (Linux 4.7-rc1) Did you start your bisect with the same bad and good commit?

[PATCH] powerpc/nohash: Fix build break with 4K pages

Commit 74701d5947a6 "powerpc/mm: Rename function to indicate we are allocating fragments" renamed page_table_free() to pte_fragment_free(). One occurrence was mistyped as pte_fragment_fre(). This only breaks the nohash 4K page build, which is not the default or enabled in any defconfig. Fixes:

Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

Hi Michael, Thanks a lot for the hint. I compiled it without the commit below but unfortunately it doesn't boot. Cheers, Christian On 08 June 2016 at 1:30 PM, Michael Ellerman wrote: It's not a merge, so just plain git revert: $ git clone

Re: [PATCH v3] powerpc: spinlock: Fix spin_unlock_wait()

On Wed, Jun 08, 2016 at 09:20:45PM +1000, Michael Ellerman wrote: > On Mon, 2016-06-06 at 16:46 +0200, Peter Zijlstra wrote: > > On Mon, Jun 06, 2016 at 10:17:25PM +1000, Michael Ellerman wrote: > > > On Mon, 2016-06-06 at 13:56 +0200, Peter Zijlstra wrote: > > > > On Mon, Jun 06, 2016 at

Re: [PATCH 5/8] dmaengine: ste_dma40: Only calculate residue if txstate exists.

On Tue, Jun 7, 2016 at 7:38 PM, Peter Griffin wrote: > There is no point calculating the residue if there is > no txstate to store the value. > > Signed-off-by: Peter Griffin Acked-by: Linus Walleij Yours, Linus

Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

Hi Michael, On 08 June 2016 at 04:52 AM, Michael Ellerman wrote: On Tue, 2016-06-07 at 22:17 +0200, Christian Zigotzky wrote: 764041e0f43cc7846f6d8eb246d65b53cc06c764 is the first bad commit commit 764041e0f43cc7846f6d8eb246d65b53cc06c764 Author: Aneesh Kumar

[PATCH] powerpc/nvram: remove unused pstore headers

Since the pstore code has moved away from nvram.c, remove unused pstore headers pstore.h and kmsg_dump.h. Signed-off-by: Geliang Tang --- arch/powerpc/platforms/pseries/nvram.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/powerpc/platforms/pseries/nvram.c

[PATCH] drivers/net/fsl_ucc: Do not prefix header guard with CONFIG_

The CONFIG_ prefix should only be used for options which can be configured through Kconfig and not for guarding headers. Signed-off-by: Andreas Ziegler --- drivers/net/wan/fsl_ucc_hdlc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [PATCH 7/8] dmaengine: tegra20-apb-dma: Only calculate residue if txstate exists.

Hi Peter, On 07/06/16 18:38, Peter Griffin wrote: > There is no point calculating the residue if there is > no txstate to store the value. > > Signed-off-by: Peter Griffin > --- > drivers/dma/tegra20-apb-dma.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >

Re: [PATCH 8/8] dmaengine: Remove site specific OOM error messages on kzalloc

On 07/06/16 18:38, Peter Griffin wrote: > If kzalloc() fails it will issue it's own error message including > a dump_stack(). So remove the site specific error messages. > > Signed-off-by: Peter Griffin > --- > drivers/dma/amba-pl08x.c| 10 +- >

Re: [PATCH 3/8] dmaengine: coh901318: Only calculate residue if txstate exists.

On Tue, Jun 7, 2016 at 7:38 PM, Peter Griffin wrote: > There is no point in calculating the residue if there is no > txstate to store the value. > > Signed-off-by: Peter Griffin Acked-by: Linus Walleij Yours, Linus

Re: [PATCH 8/8] dmaengine: Remove site specific OOM error messages on kzalloc

On Tue, Jun 7, 2016 at 7:38 PM, Peter Griffin wrote: > If kzalloc() fails it will issue it's own error message including > a dump_stack(). So remove the site specific error messages. > > Signed-off-by: Peter Griffin Acked-by: Linus Walleij

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

On Wed, 2016-06-08 at 12:58 +0200, Christian Zigotzky wrote: > On 08 June 2016 at 04:52 AM, Michael Ellerman wrote: > > On Tue, 2016-06-07 at 22:17 +0200, Christian Zigotzky wrote: > > > 764041e0f43cc7846f6d8eb246d65b53cc06c764 is the first bad commit > > > commit

Re: [PATCH] powerpc/pseries: Add POWER8NVL support to ibm,client-architecture-support call

On Wed, 2016-06-08 at 13:17 +0200, Thomas Huth wrote: > On 08.06.2016 12:44, Michael Ellerman wrote: > > On Wed, 2016-06-08 at 11:14 +1000, Balbir Singh wrote: > > > Don't we need to update IBM_ARCH_VEC_NRCORES_OFFSET as well? > > > > Yep, patch sent this morning. > > Ok, looks like BenH already

Re: [PATCH v3] powerpc: spinlock: Fix spin_unlock_wait()

On Mon, 2016-06-06 at 16:46 +0200, Peter Zijlstra wrote: > On Mon, Jun 06, 2016 at 10:17:25PM +1000, Michael Ellerman wrote: > > On Mon, 2016-06-06 at 13:56 +0200, Peter Zijlstra wrote: > > > On Mon, Jun 06, 2016 at 09:42:20PM +1000, Michael Ellerman wrote: > > > > > > Why the move to in-line

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

On Mon, 2016-06-06 at 14:27 +0530, Anshuman Khandual wrote: > On 06/03/2016 03:56 AM, Cyril Bur wrote: > > > > At the moment is is rather confusing since pt_regs is the always the 'live' > > state and theres a ckpt_regs that is the pt_regs for the checkpointed state. > > FPU/VMX/VSX is done

Re: [PATCH] powerpc/pseries: Add POWER8NVL support to ibm,client-architecture-support call

On 08.06.2016 12:44, Michael Ellerman wrote: > On Wed, 2016-06-08 at 11:14 +1000, Balbir Singh wrote: >> On 31/05/16 20:32, Michael Ellerman wrote: >>> On Tue, 2016-05-31 at 12:19 +0200, Thomas Huth wrote: On 31.05.2016 12:04, Michael Ellerman wrote: > On Tue, 2016-05-31 at 07:51 +0200,

Re: [PATCH] of: fix autoloading due to broken modalias with no 'compatible'

On Mon, 2016-06-06 at 18:48 +0200, Wolfram Sang wrote: > Because of an improper dereference, a stray 'C' character was output to > the modalias when no 'compatible' was specified. This is the case for > some old PowerMac drivers which only set the 'name' property. Fix it to > let them match again.

Re: [PATCH] powerpc: Fix IBM_ARCH_VEC_NRCORES_OFFSET value

On 08.06.2016 00:51, Benjamin Herrenschmidt wrote: > Commit 7cc851039d643a2ee7df4d18177150f2c3a484f5 > "powerpc/pseries: Add POWER8NVL support to ibm,client-architecture-support > call" > introduced a regression by adding fields to the beginning of the > ibm_architecture_vec structure without

Re: [PATCH] powerpc/pseries: Add POWER8NVL support to ibm,client-architecture-support call

On 08.06.2016 03:14, Balbir Singh wrote: > > On 31/05/16 20:32, Michael Ellerman wrote: >> On Tue, 2016-05-31 at 12:19 +0200, Thomas Huth wrote: >>> On 31.05.2016 12:04, Michael Ellerman wrote: On Tue, 2016-05-31 at 07:51 +0200, Thomas Huth wrote: > If we do not provide the PVR for

Re: [PATCH] powerpc/pseries: Add POWER8NVL support to ibm,client-architecture-support call

On Wed, 2016-06-08 at 11:14 +1000, Balbir Singh wrote: > On 31/05/16 20:32, Michael Ellerman wrote: > > On Tue, 2016-05-31 at 12:19 +0200, Thomas Huth wrote: > > > On 31.05.2016 12:04, Michael Ellerman wrote: > > > > On Tue, 2016-05-31 at 07:51 +0200, Thomas Huth wrote: > > > > > If we do not

[PATCH v6 3/3] powerpc: Load Monitor Register Tests

From: Jack Miller Adds two tests. One is a simple test to ensure that the new registers LMRR and LMSER are properly maintained. The other actually uses the existing EBB test infrastructure to test that LMRR and LMSER behave as documented. Signed-off-by: Jack Miller

[PATCH v6 2/3] powerpc: Load Monitor Register Support

From: Jack Miller This enables new registers, LMRR and LMSER, that can trigger an EBB in userspace code when a monitored load (via the new ldmx instruction) loads memory from a monitored space. This facility is controlled by a new FSCR bit, LM. This patch disables the FSCR LM

[PATCH v6 1/3] powerpc: Improve FSCR init and context switching

This fixes a few issues with FSCR init and switching. In this patch: powerpc: Create context switch helpers save_sprs() and restore_sprs() Author: Anton Blanchard commit 152d523e6307c7152f9986a542f873b5c5863937 We moved the setting of the FSCR register from inside an

[PATCH v6 0/3] POWER9 Load Monitor Support

This patches series adds support for the POWER9 Load Monitor instruction (ldmx) based on work from Jack Miller. The first patch is a clean up of the FSCR handling. The second patch adds the actual ldmx support to the kernel. The third patch is a couple of ldmx selftests. v6: - PATCH 1/3: -

Re: [RESEND PATCH v2 0/6] vfio-pci: Add support for mmapping MSI-X table

Hi, Eric On 2016/6/8 15:41, Auger Eric wrote: Hi Yongji, Le 02/06/2016 à 08:09, Yongji Xie a écrit : Current vfio-pci implementation disallows to mmap the page containing MSI-X table in case that users can write directly to MSI-X table and generate an incorrect MSIs. However, this will

Re: [PATCH v2 0/7] crypto: talitos - implementation of AEAD for SEC1

On Mon, Jun 06, 2016 at 01:20:31PM +0200, Christophe Leroy wrote: > This set of patches provides the implementation of AEAD for > talitos SEC1. All applied. Thanks. -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key:

Re: [RESEND PATCH v2 0/6] vfio-pci: Add support for mmapping MSI-X table

Hi Yongji, Le 02/06/2016 à 08:09, Yongji Xie a écrit : > Current vfio-pci implementation disallows to mmap the page > containing MSI-X table in case that users can write directly > to MSI-X table and generate an incorrect MSIs. > > However, this will cause some performance issue when there > are

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