Re: [PATCH v3 0/4] implement vcpu preempted check

在 2016/9/29 18:31, Peter Zijlstra 写道: On Thu, Sep 29, 2016 at 12:23:19PM +0200, Christian Borntraeger wrote: On 09/29/2016 12:10 PM, Peter Zijlstra wrote: On Thu, Jul 21, 2016 at 07:45:10AM -0400, Pan Xinhui wrote: change from v2: no code change, fix typos, update some comments

Re: [PATCH v5 4/4] PCI: Add a macro to set default alignment for all PCI devices

On 2016/9/29 22:00, Bjorn Helgaas wrote: On Tue, Sep 13, 2016 at 05:00:34PM +0800, Yongji Xie wrote: When vfio passthroughs a PCI device of which MMIO BARs are smaller than PAGE_SIZE, guest will not handle the mmio accesses to the BARs which leads to mmio emulations in host. This is because

Re: [PATCH v3 0/4] implement vcpu preempted check

在 2016/9/29 18:10, Peter Zijlstra 写道: On Thu, Jul 21, 2016 at 07:45:10AM -0400, Pan Xinhui wrote: change from v2: no code change, fix typos, update some comments change from v1: a simplier definition of default vcpu_is_preempted skip mahcine type check on ppc, and add

Re: [PATCH v5 3/4] PCI: Add a new option for resource_alignment to reassign alignment

On 2016/9/29 19:54, Bjorn Helgaas wrote: On Thu, Sep 29, 2016 at 10:38:01AM +0800, Yongji Xie wrote: On 2016/9/29 6:42, Bjorn Helgaas wrote: On Tue, Sep 13, 2016 at 05:00:33PM +0800, Yongji Xie wrote: When using resource_alignment kernel parameter, the current implement reassigns the

[PATCH v15 15/15] selftests/powerpc: Fix a build issue

From: Anshuman Khandual Fixes the following build failure - cp_abort.c:90:3: error: ‘for’ loop initial declarations are only allowed in C99 or C11 mode for (int i = 0; i < NUM_LOOPS; i++) { ^ cp_abort.c:90:3: note: use option -std=c99, -std=gnu99, -std=c11 or

[PATCH v15 14/15] selftests/powerpc: Add .gitignore file for ptrace executables

From: Anshuman Khandual This patch adds a .gitignore file for all the executables in the ptrace test directory thus making invisible with git status query. Signed-off-by: Anshuman Khandual Signed-off-by: Simon Guo

[PATCH v15 13/15] selftests/powerpc: Add ptrace tests for TM SPR registers

From: Anshuman Khandual This patch adds ptrace interface test for TM SPR registers. This also adds ptrace interface based helper functions related to TM SPR registers access. Signed-off-by: Anshuman Khandual Signed-off-by: Simon Guo

[PATCH v15 12/15] selftests/powerpc: Add ptrace tests for VSX, VMX registers in suspended TM

From: Anshuman Khandual This patch adds ptrace interface test for VSX, VMX registers inside suspended TM context. Signed-off-by: Anshuman Khandual Signed-off-by: Simon Guo ---

[PATCH v15 11/15] selftests/powerpc: Add ptrace tests for VSX, VMX registers in TM

From: Anshuman Khandual This patch adds ptrace interface test for VSX, VMX registers inside TM context. This also adds ptrace interface based helper functions related to chckpointed VSX, VMX registers access. Signed-off-by: Anshuman Khandual

[PATCH v15 10/15] selftests/powerpc: Add ptrace tests for VSX, VMX registers

From: Anshuman Khandual This patch adds ptrace interface test for VSX, VMX registers. This also adds ptrace interface based helper functions related to VSX, VMX registers access. This also adds some assembly helper functions related to VSX and VMX registers.

[PATCH v15 09/15] selftests/powerpc: Add ptrace tests for TAR, PPR, DSCR in suspended TM

From: Anshuman Khandual This patch adds ptrace interface test for TAR, PPR, DSCR registers inside suspended TM context. Signed-off-by: Anshuman Khandual Signed-off-by: Simon Guo ---

[PATCH v15 08/15] selftests/powerpc: Add ptrace tests for TAR, PPR, DSCR in TM

From: Anshuman Khandual This patch adds ptrace interface test for TAR, PPR, DSCR registers inside TM context. This also adds ptrace interface based helper functions related to checkpointed TAR, PPR, DSCR register access. Signed-off-by: Anshuman Khandual

[PATCH v15 07/15] selftests/powerpc: Add ptrace tests for TAR, PPR, DSCR registers

From: Anshuman Khandual This patch adds ptrace interface test for TAR, PPR, DSCR registers. This also adds ptrace interface based helper functions related to TAR, PPR, DSCR register access. Signed-off-by: Anshuman Khandual

[PATCH v15 06/15] selftests/powerpc: Add ptrace tests for GPR/FPR registers in suspended TM

From: Anshuman Khandual This patch adds ptrace interface test for GPR/FPR registers inside suspended TM context. Signed-off-by: Anshuman Khandual Signed-off-by: Simon Guo ---

[PATCH v15 05/15] selftests/powerpc: Add ptrace tests for GPR/FPR registers in TM

From: Anshuman Khandual This patch adds ptrace interface test for GPR/FPR registers inside TM context. This adds ptrace interface based helper functions related to checkpointed GPR/FPR access. Signed-off-by: Anshuman Khandual

[PATCH v15 04/15] selftests/powerpc: Add ptrace tests for GPR/FPR registers

From: Anshuman Khandual This patch adds ptrace interface test for GPR/FPR registers. This adds ptrace interface based helper functions related to GPR/FPR access and some assembly helper functions related to GPR/FPR registers. Signed-off-by: Anshuman Khandual

[PATCH v15 03/15] selftests/powerpc: Add ptrace tests for EBB

From: Anshuman Khandual This patch adds ptrace interface test for EBB/PMU specific registers. This also adds some generic ptrace interface based helper functions to be used by other patches later on in the series. Signed-off-by: Anshuman Khandual

[PATCH v15 02/15] selftests/powerpc: move shared utility files into new utility/ dir

From: Simon Guo There are some functions, especially register related, which can be shared across multiple selftests/powerpc test directories. This patch creates a new utility directory to store those shared functionalities, so that the file layout becomes more neat.

[PATCH v15 01/15] selftests/powerpc: Add more SPR numbers, TM & VMX instructions to 'reg.h'/'instructions.h'

From: Anshuman Khandual This patch adds SPR number for TAR, PPR, DSCR special purpose registers. It also adds TM, VSX, VMX related instructions which will then be used by patches later in the series. Now that the new DSCR register definitions (SPRN_DSCR_PRIV and

[PATCH v15 00/15] selftests/powerpc: Add ptrace tests for ppc registers

From: Simon Guo This selftest suite is for PPC register ptrace functionality. It is also useful for Transaction Memory functionality verification. Signed-off-by: Anshuman Khandual Signed-off-by: Simon Guo Test

Re: [PATCH v14 13/15] selftests/powerpc: Add ptrace tests for TM SPR registers

Hi Cyril, On Wed, Sep 14, 2016 at 03:04:12PM +1000, Cyril Bur wrote: > On Mon, 2016-09-12 at 15:33 +0800, wei.guo.si...@gmail.com wrote: > > From: Anshuman Khandual > > > > This patch adds ptrace interface test for TM SPR registers. This > > also adds ptrace

[PATCH] powerpc/fadump: Fix build break when CONFIG_PROC_VMCORE=n

The fadump code calls vmcore_cleanup() which only exists if CONFIG_PROC_VMCORE=y. We don't want to depend on CONFIG_PROC_VMCORE, because it's user selectable, so just wrap the call in an #ifdef. Signed-off-by: Michael Ellerman --- arch/powerpc/kernel/fadump.c | 2 ++ 1 file

Re: [PATCH] PCI: Add parameter @mmio_force_on to pci_update_resource()

On Wed, Sep 28, 2016 at 11:14:08AM +1000, Gavin Shan wrote: >On Wed, Sep 28, 2016 at 10:06:44AM +1000, Benjamin Herrenschmidt wrote: >>On Wed, 2016-09-28 at 09:37 +1000, Gavin Shan wrote: >>> >>> Yeah, it's safe to update it with memory decoding on. As the function call >>> flow I listed in the

[PATCH v2 2/2] PCI: Don't disable PF's memory decoding when enabling SRIOV

pci_update_resource() might be called to update (shift) IOV BARs in PPC PowerNV specific pcibios_sriov_enable() when enabling PF's SRIOV capability. At that point, the PF have been functional if the SRIOV is enabled through sysfs entry "sriov_numvfs". The PF's memory decoding (0x2 in PCI_COMMAND)

[PATCH v2 1/2] pci: Call pcibios_sriov_enable() before IOV BARs are enabled

In current implementation, pcibios_sriov_enable() is used by PPC PowerNV platform only. In PowerNV specific pcibios_sriov_enable(), PF's IOV BARs might be updated (shifted) by pci_update_resource(). It means the IOV BARs aren't ready for decoding incoming memory address until

Re: [PATHC v2 0/9] ima: carry the measurement list across kexec

Am Donnerstag, 29 September 2016, 16:43:08 schrieb Eric W. Biederman: > Thiago Jung Bauermann writes: > > Hello Eric, > > > > Am Dienstag, 20 September 2016, 11:07:29 schrieb Eric W. Biederman: > >> A semi-generic concept called a hand-over buffer seems to be a > >>

Re: [PATCH v21 00/20] perf, tools: Add support for PMU events in JSON format

Em Tue, Sep 27, 2016 at 04:18:46PM +0200, Jiri Olsa escreveu: > On Mon, Sep 26, 2016 at 09:59:54AM -0700, Andi Kleen wrote: > > On Mon, Sep 26, 2016 at 12:03:43PM -0300, Arnaldo Carvalho de Melo wrote: > > > Em Mon, Sep 26, 2016 at 10:35:33AM +0200, Jiri Olsa escreveu: > > > > ping.. is that

Re: [PATCH v5 00/10] ima: carry the measurement list across kexec

On Thu, 2016-09-29 at 16:37 -0500, Eric W. Biederman wrote: > Mimi Zohar writes: > > > The TPM PCRs are only reset on a hard reboot. In order to validate a > > TPM's quote after a soft reboot (eg. kexec -e), the IMA measurement list > > of the running kernel must be

Re: [PATHC v2 0/9] ima: carry the measurement list across kexec

Thiago Jung Bauermann writes: > Hello Eric, > > Am Dienstag, 20 September 2016, 11:07:29 schrieb Eric W. Biederman: >> A semi-generic concept called a hand-over buffer seems to be a >> construction of infrustructure for no actual reason that will just >> result in

Re: [PATCH v5 00/10] ima: carry the measurement list across kexec

Mimi Zohar writes: > The TPM PCRs are only reset on a hard reboot. In order to validate a > TPM's quote after a soft reboot (eg. kexec -e), the IMA measurement list > of the running kernel must be saved and then restored on the subsequent > boot, possibly of a

Re: [GIT PULL 00/27] perf/core improvements and fixes

b6af76096: > > Merge tag 'perf-core-for-mingo-20160922' of > git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core > (2016-09-23 07:21:38 +0200) > > are available in the git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/acme/li

RE: [PATCH] dma/fsldma : Unmap region obtained by of_iomap

> -Original Message- > From: Arvind Yadav [mailto:arvind.yadav...@gmail.com] > Sent: Wednesday, September 28, 2016 5:45 AM > To: le...@freescale.com; z...@zh-kernel.org; vinod.k...@intel.com > Cc: dan.j.willi...@intel.com; linuxppc-dev@lists.ozlabs.org; > dmaeng...@vger.kernel.org;

Re: [PATCH v5] powerpc: Do not make the entire heap executable

On 09/28, Kees Cook wrote: > > This is where the flags are actually built from what's coming in > through the newly created exported function vm_brk_flags() below. The > only flag we're acting on is VM_EXEC (passed in from set_brk() above). > I think do_brk_flags() should mask the valid flags, or

[GIT PULL 00/27] perf/core improvements and fixes

/acme/linux into perf/core (2016-09-23 07:21:38 +0200) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-20160929 for you to fetch changes up to d18019a53a07e009899ff6b8dc5ec30f249360d9: perf tests: Add dwarf unwind

[PATCH 27/27] perf tests: Add dwarf unwind test for powerpc

From: Ravi Bangoria The user stack dump feature was recently added for powerpc. But there was no test case available to test it. This test works same as on other architectures by preparing a stack frame on the perf test thread and comparing each frame by

Re: [PATCH v5 4/4] PCI: Add a macro to set default alignment for all PCI devices

On Tue, Sep 13, 2016 at 05:00:34PM +0800, Yongji Xie wrote: > When vfio passthroughs a PCI device of which MMIO BARs are > smaller than PAGE_SIZE, guest will not handle the mmio > accesses to the BARs which leads to mmio emulations in host. > > This is because vfio will not allow to passthrough

Re: powerpc/vdso64: Use double word compare on pointers

On Sun, 2016-25-09 at 07:16:53 UTC, Anton Blanchard wrote: > From: Anton Blanchard > > __kernel_get_syscall_map and __kernel_clock_getres use cmpli to > check if the passed in pointer is non zero. cmpli maps to a 32 bit > compare on binutils, so we ignore the top 32 bits. > > A

Re: [v3] KVM: PPC: Book3S HV: Migrate pinned pages out of CMA

On Tue, 2016-06-09 at 06:27:31 UTC, Balbir Singh wrote: > When PCI Device pass-through is enabled via VFIO, KVM-PPC will > pin pages using get_user_pages_fast(). One of the downsides of > the pinning is that the page could be in CMA region. The CMA > region is used for other allocations like the

Re: powerpc/powernv: Call opal_pci_poll() if needed

On Fri, 2016-24-06 at 06:44:19 UTC, Gavin Shan wrote: > When issuing PHB reset, OPAL API opal_pci_poll() is called to drive > the state machine in OPAL forward. However, we needn't always call > the function under some circumstances like reset deassert. > > This avoids calling opal_pci_poll()

Re: [v3,1/6] powerpc/eeh: Allow to freeze PE in eeh_pe_set_option()

On Wed, 2016-28-09 at 04:34:53 UTC, Gavin Shan wrote: > Function eeh_pe_set_option() is used to apply the requested options > (enable, disable, unfreeze) in EEH virtualization path. The semantics > of this function isn't complete until freezing is supported. > > This allows to freeze the

Re: [PATCH v5 3/4] PCI: Add a new option for resource_alignment to reassign alignment

On Thu, Sep 29, 2016 at 10:38:01AM +0800, Yongji Xie wrote: > On 2016/9/29 6:42, Bjorn Helgaas wrote: > > >On Tue, Sep 13, 2016 at 05:00:33PM +0800, Yongji Xie wrote: > >>When using resource_alignment kernel parameter, the current > >>implement reassigns the alignment by changing resources' size

Re: [PATCH v3 0/4] implement vcpu preempted check

On 09/29/2016 12:40 PM, Christian Borntraeger wrote: > On 09/29/2016 12:23 PM, Christian Borntraeger wrote: >> On 09/29/2016 12:10 PM, Peter Zijlstra wrote: >>> On Thu, Jul 21, 2016 at 07:45:10AM -0400, Pan Xinhui wrote: change from v2: no code change, fix typos, update some comments

Re: [PATCH v3 0/4] implement vcpu preempted check

On 09/29/2016 12:23 PM, Christian Borntraeger wrote: > On 09/29/2016 12:10 PM, Peter Zijlstra wrote: >> On Thu, Jul 21, 2016 at 07:45:10AM -0400, Pan Xinhui wrote: >>> change from v2: >>> no code change, fix typos, update some comments >>> >>> change from v1: >>> a simplier definition of

Re: [PATCH v3 0/4] implement vcpu preempted check

On Thu, Sep 29, 2016 at 12:23:19PM +0200, Christian Borntraeger wrote: > On 09/29/2016 12:10 PM, Peter Zijlstra wrote: > > On Thu, Jul 21, 2016 at 07:45:10AM -0400, Pan Xinhui wrote: > >> change from v2: > >>no code change, fix typos, update some comments > >> > >> change from v1: > >>a

Re: [PATCH v3 0/4] implement vcpu preempted check

On 09/29/2016 12:10 PM, Peter Zijlstra wrote: > On Thu, Jul 21, 2016 at 07:45:10AM -0400, Pan Xinhui wrote: >> change from v2: >> no code change, fix typos, update some comments >> >> change from v1: >> a simplier definition of default vcpu_is_preempted >> skip mahcine type check on

Re: [v3,4/5] powerpc/pm: support deep sleep feature on T104x

From: Scott Wood Sent: Thursday, September 29, 2016 4:03 AM To: C.H. Zhao Cc: linuxppc-dev@lists.ozlabs.org; linux-ker...@vger.kernel.org; z.chen...@gmail.com; Jason Jin Subject: Re: [v3,4/5] powerpc/pm: support deep sleep feature on T104x   On Tue, 2016-09-27 at 11:05

Re: [PATCH v3 0/4] implement vcpu preempted check

On Thu, Jul 21, 2016 at 07:45:10AM -0400, Pan Xinhui wrote: > change from v2: > no code change, fix typos, update some comments > > change from v1: > a simplier definition of default vcpu_is_preempted > skip mahcine type check on ppc, and add config. remove dedicated macro. >

[PATCH 2/2] powernv: Pass PSSCR value and mask to power9_idle_stop

From: "Gautham R. Shenoy" The power9_idle_stop method currently takes only the requested stop level as a parameter and picks up the rest of the PSSCR bits from a hand-coded macro. This is not a very flexible design, especially when the firmware has the capability to

[PATCH 1/2] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro

From: "Gautham R. Shenoy" Currently all the low-power idle states are expected to wake up at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ that puts the CPU to an idle state and never returns. On ISA_300, when the ESL and EC bits in the PSSCR are zero,

[PATCH 0/2] powernv:stop: Use psscr_val,mask provided by firmware

From: "Gautham R. Shenoy" Hi, In the current implementation, the code for ISA v3.0 stop implementation has a couple of shortcomings. a) The code hand-codes the values for ESL,EC,TR,MTL bits of PSSCR and uses only the RL field from the firmware. While this is not

[PATCH v6 4/4] PCI: Add a macro to set default alignment for all PCI devices

When vfio passthroughs a PCI device of which MMIO BARs are smaller than PAGE_SIZE, guest will not handle the mmio accesses to the BARs which leads to mmio emulations in host. This is because vfio will not allow to passthrough one BAR's mmio page which may be shared with other BARs. Otherwise,

[PATCH v6 3/4] PCI: Don't change resources' size when using resource_alignment

When using resource_alignment kernel parameter, the current implement reassigns the alignment by changing resources' size which can potentially break some drivers. For example, the driver uses the size to locate some register whose length is related to the size. This patch tries to use

[PATCH v6 2/4] PCI: Ignore enforced alignment to VF BARs

VF BARs are read-only zeroes according to SRIOV spec, the normal way(writing BARs) of allocating resources wouldn't be applied to VFs. The VFs' resources would be allocated when we enable SR-IOV capability. So we should not try to reassign alignment after we enable VFs. It's meaningless and will

[PATCH v6 1/4] PCI: Ignore enforced alignment when kernel uses existing firmware setup

PCI resources allocator will use firmware setup and not try to reassign resource when PCI_PROBE_ONLY or IORESOURCE_PCI_FIXED is set. The enforced alignment in pci_reassigndev_resource_alignment() should be ignored in this case. Otherwise, some PCI devices' resources would be released here and not

[PATCH v6 0/4] PCI: Introduce a way to enforce all MMIO BARs not to share PAGE_SIZE

This series introduces a way for PCI resource allocator to force MMIO BARs not to share PAGE_SIZE. This would make sense to VFIO driver. Because current VFIO implementation disallows to mmap sub-page(size < PAGE_SIZE) MMIO BARs which may share the same page with other BARs for security reasons.

[PATCH v4 5/7] drivers/pci/hotplug: Remove likely() and unlikely() in powernv driver

This removes likely() and unlikely() in pnv_php.c as the code isn't running in hot path. Those macros to affect CPU's branch stream don't help a lot for performance. I used them to identify the cases are likely or unlikely to happen. No logical changes introduced. Signed-off-by: Gavin Shan