Re: [PATCH] powerpc/mm/hugetlb: Filter out hugepage size not supported by page table layout

Benjamin Herrenschmidt writes: > On Mon, 2017-02-20 at 09:02 +0530, Aneesh Kumar K.V wrote: >> To avoid crashes like the one reported in the commit message due to  >> buggy firmware ? > > I don't want Linux to make those assumptions. We should fix the FW. > I was not

Re: [next-20170217] WARN @/arch/powerpc/include/asm/xics.h:124 .icp_hv_eoi+0x40/0x140

>> While booting next-20170217 on a POWER6 box, I ran into following >> warning. This is a full system lpar. Previous next tree was good. >> I will try a bisect tomorrow. > > Do you have CONFIG_DEBUG_SHIRQ=y ? > Yes. CONFIG_DEBUG_SHIRQ is enabled. As suggested by you reverting following

Re: [PATCH] powernv/opal: Handle OPAL_WRONG_STATE error from OPAL fails

Stewart Smith writes: > Vipin K Parashar writes: >> On Monday 13 February 2017 06:13 AM, Michael Ellerman wrote: >>> Vipin K Parashar writes: >>> OPAL returns OPAL_WRONG_STATE for XSCOM operations

Re: [PATCH] powerpc/xmon: Fix an unexpected xmon onoff state change

Pan Xinhui writes: > 在 2017/2/17 14:05, Michael Ellerman 写道: >> Pan Xinhui writes: >>> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c >>> index 9c0e17c..f6e5c3d 100644 >>> --- a/arch/powerpc/xmon/xmon.c >>> +++

Re: [PATCH 06/35] powerpc: Convert remaining uses of pr_warning to pr_warn

On Mon, 2017-02-20 at 15:40 +1100, Michael Ellerman wrote: > Joe Perches writes: > > > To enable eventual removal of pr_warning > > > > This makes pr_warn use consistent for arch/powerpc > > > > Prior to this patch, there were 36 uses of pr_warning and > > 217 uses of pr_warn

Re: [PATCH 06/35] powerpc: Convert remaining uses of pr_warning to pr_warn

Joe Perches writes: > To enable eventual removal of pr_warning > > This makes pr_warn use consistent for arch/powerpc > > Prior to this patch, there were 36 uses of pr_warning and > 217 uses of pr_warn in arch/powerpc > > Signed-off-by: Joe Perches Can I

Re: [next-20170217] WARN @/arch/powerpc/include/asm/xics.h:124 .icp_hv_eoi+0x40/0x140

On Sun, 2017-02-19 at 20:39 +0530, Sachin Sant wrote: > While booting next-20170217 on a POWER6 box, I ran into following > warning. This is a full system lpar. Previous next tree was good. > I will try a bisect tomorrow. >  > ipr: IBM Power RAID SCSI Device Driver version: 2.6.3 (October 17,

Re: [PATCH] powerpc/mm/hugetlb: Filter out hugepage size not supported by page table layout

On Mon, 2017-02-20 at 09:02 +0530, Aneesh Kumar K.V wrote: > To avoid crashes like the one reported in the commit message due to  > buggy firmware ? I don't want Linux to make those assumptions. We should fix the FW. Think of backward compat for example. > Also > It can serve as an easy way to

Re: [PATCH] powerpc/mm/hugetlb: Filter out hugepage size not supported by page table layout

On Monday 20 February 2017 02:35 AM, Benjamin Herrenschmidt wrote: On Sun, 2017-02-19 at 15:48 +0530, Aneesh Kumar K.V wrote: +#ifdef CONFIG_PPC_BOOK3S_64 + /* +* We need to make sure that for different page sizes reported by +* firmware we only add hugetlb support for

[PATCH v4 10/10] powerpc/perf: Thread IMC PMU functions

This patch adds the PMU functions required for event initialization, read, update, add, del etc. for thread IMC PMU. Thread IMC PMUs are used for per-task monitoring. These PMUs don't need any hotplugging support. For each CPU, a page of memory is allocated and is kept static i.e., these pages

[PATCH v4 09/10] powerpc/powernv: Thread IMC events detection

Patch adds support for detection of thread IMC events. It adds a new domain IMC_DOMAIN_THREAD and it is determined with the help of the compatibility string "ibm,imc-counters-thread" based on the IMC device tree. Cc: Madhavan Srinivasan Cc: Michael Ellerman

[PATCH v4 08/10] powerpc/perf: PMU functions for Core IMC and hotplugging

This patch adds the PMU function to initialize a core IMC event. It also adds cpumask initialization function for core IMC PMU. For initialization, a page of memory is allocated per core where the data for core IMC counters will be accumulated. The base address for this page is sent to OPAL via an

[PATCH v4 07/10] powerpc/powernv: Core IMC events detection

This patch adds support for detection of core IMC events along with the Nest IMC events. It adds a new domain IMC_DOMAIN_CORE and its determined with the help of the compatibility string "ibm,imc-counters-core" based on the IMC device tree. Cc: Madhavan Srinivasan Cc:

[PATCH v4 06/10] powerpc/perf: IMC pmu cpumask and cpu hotplug support

Adds cpumask attribute to be used by each IMC pmu. Only one cpu (any online CPU) from each chip for nest PMUs is designated to read counters. On CPU hotplug, dying CPU is checked to see whether it is one of the designated cpus, if yes, next online cpu from the same chip (for nest units) is

[PATCH v4 05/10] powerpc/perf: Generic imc pmu event functions

Since, the IMC counters' data are periodically fed to a memory location, the functions to read/update, start/stop, add/del can be generic and can be used by all IMC PMU units. This patch adds a set of generic imc pmu related event functions to be used by each imc pmu unit. Add code to setup

[PATCH v4 04/10] powerpc/perf: Add event attribute and group to IMC pmus

Device tree IMC driver code parses the IMC units and their events. It passes the information to IMC pmu code which is placed in powerpc/perf as "imc-pmu.c". This patch creates only event attributes and attribute groups for the IMC pmus. Cc: Madhavan Srinivasan Cc:

[PATCH v4 03/10] powerpc/powernv: Detect supported IMC units and its events

Parse device tree to detect IMC units. Traverse through each IMC unit node to find supported events and corresponding unit/scale files (if any). The device tree for IMC counters starts at the node : "imc-counters". This node contains all the IMC PMU nodes and event nodes for these IMC PMUs. The

[PATCH v4 02/10] powerpc/powernv: Autoload IMC device driver module

This patch does three things : - Enables "opal.c" to create a platform device for the IMC interface according to the appropriate compatibility string. - Find the reserved-memory region details from the system device tree and get the base address of HOMER region address for each chip. - We

[PATCH v4 01/10] powerpc/powernv: Data structure and macros definitions

Create new header file "imc-pmu.h" to add the data structures and macros needed for IMC pmu support. Cc: Madhavan Srinivasan Cc: Michael Ellerman Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Anton

[PATCH v4 00/10] IMC Instrumentation Support

Power 9 has In-Memory-Collection (IMC) infrastructure which contains various Performance Monitoring Units (PMUs) at Nest level (these are on-chip but off-core), Core level and Thread level. The Nest PMU counters are handled by a Nest IMC microcode which runs in the OCC (On-Chip Controller)

Re: [next-20170217] WARN @/arch/powerpc/include/asm/xics.h:124 .icp_hv_eoi+0x40/0x140

Sachin Sant writes: > While booting next-20170217 on a POWER6 box, I ran into following > warning. This is a full system lpar. Previous next tree was good. > I will try a bisect tomorrow. Do you have CONFIG_DEBUG_SHIRQ=y ? cheers > ipr: IBM Power RAID SCSI Device

Re: [RFC PATCH 4/9] powerpc/4xx: Create 4xx pseudo-platform in platforms/4xx

On Fri, 17 Feb 2017 17:32:14 +1100 Michael Ellerman wrote: > We have a lot of code in sysdev for supporting 4xx, ie. either 40x or > 44x. Instead it would be cleaner if it was all in platforms/4xx. > > This is slightly odd in that we don't actually define any machines in >

[PATCH 2/2] powerpc/mm: Enable page table accounting

Enabled __GFP_ACCOUNT in pgtable_get_gfp_flags(). This allows accounting of page table allocation via kmem to the correct cgroup. Basic testing was done to see if the accounting reflects in 1. perf record tracing 2. memory.kmem.slabinfo Signed-off-by: Balbir Singh ---

[PATCH 1/2] powerpc/mm: Refactor page table allocation

Introduce a helper pgtable_get_gfp_flags() which just returns the current gfp flags. In a future patch, we can enable __GFP_ACCOUNT based on the calling context. Signed-off-by: Balbir Singh --- arch/powerpc/include/asm/book3s/64/pgalloc.h | 22 --

Re: [PATCH] powerpc/powernv: Make PCI non-optional

On Fri, Feb 17, 2017 at 05:34:13PM +1100, Michael Ellerman wrote: >Bare metal systems without PCI don't exist, so there's no real point in >making PCI optional, it just breaks the build from time to time. In fact >the build is broken now if you turn off PCI_MSI but enable KVM. > >Using select for

Re: [PATCH] powerpc/mm/hugetlb: Filter out hugepage size not supported by page table layout

On Sun, 2017-02-19 at 15:48 +0530, Aneesh Kumar K.V wrote: > +#ifdef CONFIG_PPC_BOOK3S_64 > +   /* > +    * We need to make sure that for different page sizes reported by > +    * firmware we only add hugetlb support for page sizes that can be > +    * supported by linux page table

[next-20170217] WARN @/arch/powerpc/include/asm/xics.h:124 .icp_hv_eoi+0x40/0x140

While booting next-20170217 on a POWER6 box, I ran into following warning. This is a full system lpar. Previous next tree was good. I will try a bisect tomorrow. ipr: IBM Power RAID SCSI Device Driver version: 2.6.3 (October 17, 2015) ipr 0200:00:01.0: Found IOA with IRQ: 305 [ cut

next-20170217 boot on POWER8 LPAR : WARNING @kernel/jump_label.c:287

While booting next-20170217 on a POWER8 LPAR following warning is displayed. Reverting the following commit helps boot cleanly. commit 3821fd35b5 : jump_label: Reduce the size of struct static_key [ 11.393008] [ cut here ] [ 11.393031] WARNING: CPU: 5 PID: 2890 at

Re: [v2] powerpc: Add POWER9 architected mode to cputable

On Fri, 2017-02-17 at 02:01:35 UTC, Russell Currey wrote: > PVR value of 0x0F05 means we are arch v3.00 compliant (i.e. POWER9). > > Acked-by: Michael Neuling > Signed-off-by: Russell Currey Applied to powerpc next, thanks.

Re: [1/2] powerpc/mm: Convert slb_finish_load[_1T] to local symbols

On Thu, 2017-02-16 at 05:38:44 UTC, Michael Ellerman wrote: > slb_finish_load and slb_finish_load_1T are both only used within > slb_low.S, so make them local symbols. > > This makes the code a little clearer, as it's more obvious neither is > intended to be an entry point from arbitrary other

Re: [PATCHv3,4/4] MAINTAINERS: Remove powerpc's opal match

On Thu, 2017-02-16 at 00:37:15 UTC, Stewart Smith wrote: > Remove OPAL regex in powerpc to avoid false match > > Signed-off-by: Stewart Smith > Reviewed-by: Andrew Donnellan Applied to powerpc next, thanks.

Re: [1/3] pci/hotplug/pnv-php: Remove WARN_ON() in pnv_php_put_slot()

On Wed, 2017-02-15 at 23:22:32 UTC, Gavin Shan wrote: > The WARN_ON() causes unnecessary backtrace when putting the parent > slot, which is likely to be NULL. > > WARNING: CPU: 2 PID: 1071 at drivers/pci/hotplug/pnv_php.c:85 \ > pnv_php_release+0xcc/0x150 [pnv_php]

Re: [v7, 4/4] powerpc/pseries: Implement indexed-count hotplug memory remove

On Wed, 2017-02-15 at 18:46:18 UTC, Nathan Fontenot wrote: > From: Sahil Mehta > > Indexed-count remove for memory hotplug guarantees that a contiguous block > of lmbs beginning at a specified will be unassigned (NOT > that lmbs will be removed). Because of Qemu's

Re: [v7, 3/4] powerpc/pseries: Implement indexed-count hotplug memory add

On Wed, 2017-02-15 at 18:45:56 UTC, Nathan Fontenot wrote: > From: Sahil Mehta > > Indexed-count add for memory hotplug guarantees that a contiguous block > of lmbs beginning at a specified will be assigned, > any LMBs in this range that are not already assigned will be

Re: powerpc/perf: Avoid FAB_*_MATCH checks for power9

On Mon, 2017-02-13 at 11:32:54 UTC, Madhavan Srinivasan wrote: > Since power9 does not support FAB_*_MATCH bits in MMCR1, > avoid these checks for power9. For this, patch factor out > code in isa207_get_constraint() to retain these checks > only for power8. > > Patch also updates the comment in

Re: [v2,1/6] powerpc/perf: Factor of event_alternative function

On Sun, 2017-02-12 at 17:03:10 UTC, Madhavan Srinivasan wrote: > Factor out the power8 event_alternative function to share > the code with power9. > > Signed-off-by: Madhavan Srinivasan Series applied to powerpc next, thanks.

Re: [v2] powerpc/mm: Fix typo in set_pte_at()

On Wed, 2017-02-08 at 03:16:50 UTC, Gavin Shan wrote: > This fixes the typo about the _PAGE_PTE in set_pte_at() by changing > "tryint" to "trying to". > > Signed-off-by: Gavin Shan > Acked-by: Balbir Singh Applied to powerpc next, thanks.

Re: [v2] powerpc/kernel: Remove error message in pcibios_setup_phb_resources()

On Wed, 2017-02-08 at 03:11:03 UTC, Gavin Shan wrote: > The CAPI driver creates virtual PHB (vPHB) from the CAPI adapter. > The vPHB's IO and memory windows aren't built from device-tree node > as we do for normal PHBs. A error message is thrown in below path > when trying to probe AFUs contained

Re: powerpc/powernv: Remove unused variable in pnv_pci_sriov_disable()

On Wed, 2017-01-11 at 01:09:05 UTC, Gavin Shan wrote: > The local variable @iov isn't used, to remove it. > > Signed-off-by: Gavin Shan > Reviewed-by: Andrew Donnellan Applied to powerpc next, thanks.

Re: powerpc: implement clear_bit_unlock_is_negative_byte()

On Tue, 2017-01-03 at 18:58:28 UTC, Nicholas Piggin wrote: > Commit b91e1302ad9b8 ("mm: optimize PageWaiters bit use for > unlock_page()") added a special bitop function to speed up > unlock_page(). Implement this for powerpc. ... > > Signed-off-by: Nicholas Piggin Applied to

Re: powerpc/perf: use is_kernel_addr macro in perf_get_misc_flags()

On Sat, 2016-12-24 at 06:05:49 UTC, Madhavan Srinivasan wrote: > Cleanup to use is_kernel_addr macro. > > Signed-off-by: Madhavan Srinivasan Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/a2391b35f1d9d5b51d43a9150c7239 cheers

Re: [PATCH] cxl: Enable PCI device ID for future IBM CXL adapter

On 17/02/17 14:45, Uma Krishnan wrote: From: "Matthew R. Ochs" Add support for a future IBM Coherent Accelerator (CXL) device with an ID of 0x0623. Signed-off-by: Matthew R. Ochs Signed-off-by: Uma Krishnan

Re: [PATCH V3 0/3] Numabalancing preserve write fix

I am not sure whether we want to merge this debug patch. This will help us in identifying wrong pte_wrprotect usage in the kernel. >From a0fb302fd204159a1327b67decb8f14ffa21 Mon Sep 17 00:00:00 2001 From: "Aneesh Kumar K.V" Date: Sat, 18 Feb 2017 10:39:47

[PATCH] powerpc/mm/hugetlb: Filter out hugepage size not supported by page table layout

Without this if firmware reports 1MB page size support we will crash trying to use 1MB as hugetlb page size. echo 300 > /sys/kernel/mm/hugepages/hugepages-1024kB/nr_hugepages kernel BUG at ./arch/powerpc/include/asm/hugetlb.h:19! . [c000e2c27b30] c029dae8

[PATCH] powerpc/mm: Add translation mode information in /proc/cpuinfo

With this we have on powernv and pseries /proc/cpuinfo reporting timebase: 51200 platform: PowerNV model : 8247-22L machine : PowerNV 8247-22L firmware: OPAL translation : Hash Signed-off-by: Aneesh Kumar K.V ---

[PATCH V3 10/10] powerpc/mm/slice: Update slice mask printing to use bitmap printing.

We now get output like below which is much better. [0.935306] good_mask low_slice: 0-15 [0.935360] good_mask high_slice: 0-511 Compared to [0.953414] good_mask: - 1. I also fixed an error with slice_dbg printing. Signed-off-by: Aneesh Kumar

[PATCH V3 09/10] powerpc/mm/slice: Move slice_mask struct definition to slice.c

This structure definition need not be in a header since this is used only by slice.c file. So move it to slice.c. This also allow us to use SLICE_NUM_HIGH instead of 512 and also helps in getting rid of one BUILD_BUG_ON(). I also switch the low_slices type to u64 from u16. This doesn't have an

[PATCH V3 08/10] powerpc/mm/hash: Increase VA range to 128TB

We update the hash linux page table layout such that we can support 512TB. But we limit the TASK_SIZE to 128TB. We can switch to 128TB by default without conditional because that is the max virtual address supported by other architectures. We will later add a mechanism to on-demand increase the

[PATCH V3 07/10] powerpc/mm/slice: Use mm task_size as max value of slice index

In the followup patch, we will increase the slice array sice to handle 512TB range, but will limit the task size to 128TB. Avoid doing uncessary computation and avoid doing slice mask related operation above task_size. Signed-off-by: Aneesh Kumar K.V ---

[PATCH V3 06/10] powerpc/mm: Remove redundant TASK_SIZE_USER64 checks

The check against VSID range is implied when we check task size against hash and radix pgtable range[1], because we make sure page table range cannot exceed vsid range. [1] BUILD_BUG_ON(TASK_SIZE_USER64 > H_PGTABLE_RANGE); BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE); The check for

[PATCH V3 05/10] powerpc/mm: Move copy_mm_to_paca to paca.c

We will be updating this later to use struct mm_struct. Move this so that function finds the definition of struct mm_struct; Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/paca.h | 18 +- arch/powerpc/kernel/paca.c | 19

[PATCH V3 04/10] powerpc/mm/hash: Support 68 bit VA

Inorder to support large effective address range (512TB), we want to increase the virtual address bits to 68. But we do have platforms like p4 and p5 that can only do 65 bit VA. We support those platforms by limiting context bits on them to 16. The protovsid -> vsid conversion is verified to work

[PATCH V3 03/10] powerpc/mm/hash: Move kernel context to the starting of context range

With current kernel, we use the top 4 context for the kernel. Kernel VSIDs are built using these top context values and effective segemnt ID. In the following patches, we want to increase the max effective address to 512TB. We achieve that by increasing the effective segments IDs there by

[PATCH V3 02/10] powerpc/mm/slice: Update the function prototype

This avoid copying the slice_mask struct as function return value Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/slice.c | 62 ++--- 1 file changed, 28 insertions(+), 34 deletions(-) diff --git

[PATCH V3 01/10] powerpc/mm/slice: Convert slice_mask high slice to a bitmap

In followup patch we want to increase the va range which will result in us requiring high_slices to have more than 64 bits. To enable this convert high_slices to bitmap. We keep the number bits same in this patch and later change that to higher value Signed-off-by: Aneesh Kumar K.V

[PATCH V3 00/10] powerpc/mm/ppc64: Add 128TB support

This patch series increase the effective virtual address range of applications from 64TB to 128TB. We do that by supporting a 68 bit virtual address. On platforms that can only do 65 bit virtual address we limit the max contexts to a 16bit value instead of 19. The patch series also switch the

[PATCH V3 3/3] powerpc/mm/autonuma: Switch ppc64 to its own implementeation of saved write

With this our protnone becomes a present pte with READ/WRITE/EXEC bit cleared. By default we also set _PAGE_PRIVILEGED on such pte. This is now used to help us identify a protnone pte that as saved write bit. For such pte, we will clear the _PAGE_PRIVILEGED bit. The pte still remain non-accessible

[PATCH V3 2/3] mm/ksm: Handle protnone saved writes when making page write protect

Without this KSM will consider the page write protected, but a numa fault can later mark the page writable. This can result in memory corruption. Signed-off-by: Aneesh Kumar K.V --- include/asm-generic/pgtable.h | 8 mm/ksm.c | 9

[PATCH V3 1/3] mm/autonuma: Let architecture override how the write bit should be stashed in a protnone pte.

Autonuma preserves the write permission across numa fault to avoid taking a writefault after a numa fault (Commit: b191f9b106ea " mm: numa: preserve PTE write permissions across a NUMA hinting fault"). Architecture can implement protnone in different ways and some may choose to implement that by

[PATCH V3 0/3] Numabalancing preserve write fix

This patch series address an issue w.r.t THP migration and autonuma preserve write feature. migrate_misplaced_transhuge_page() cannot deal with concurrent modification of the page. It does a page copy without following the migration pte sequence. IIUC, this was done to keep the migration simpler