Re: [PATCH 00/14 v2] idle performance improvements

On Mon, 12 Jun 2017 14:25:24 +1000 Benjamin Herrenschmidt wrote: > On Sun, 2017-06-11 at 19:30 +1000, Nicholas Piggin wrote: > > I rebased this on the powerpc next tree. > > > > A couple of things are changed since last post: > > > > - Patch 1 now properly accounts for the

Re: [PATCH 00/14 v2] idle performance improvements

On Sun, 2017-06-11 at 19:30 +1000, Nicholas Piggin wrote: > I rebased this on the powerpc next tree. > > A couple of things are changed since last post: > > - Patch 1 now properly accounts for the fact the powernv idle > wakeups do not re-enable interrupts until the cpuidle driver > enables

[PATCH 14/14] powerpc/64s: idle runlatch switch is done with MSR[EE]=0

2*mfmsr and 2*mtmsr can be avoided in the idle sleep/wake code because we know the MSR[EE] is clear. Signed-off-by: Nicholas Piggin --- arch/powerpc/platforms/powernv/idle.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git

[PATCH 13/14] powerpc/64: runlatch CTRL[RUN] set optimisation

The CTRL register is read-only except bit 63 which is the run latch control. This means it can be updated with a mtspr rather than mfspr/mtspr. Signed-off-by: Nicholas Piggin --- arch/powerpc/kernel/process.c | 12 ++-- 1 file changed, 2 insertions(+), 10 deletions(-)

[PATCH 12/14] powerpc/64s: cpuidle no memory barrier after break from idle

A memory barrier is not required after the task wakes up, only if we clear the polling flag before waking. The case where we have work to do is the important one, so optimise for it. Signed-off-by: Nicholas Piggin --- drivers/cpuidle/cpuidle-powernv.c | 11 +--

[PATCH 11/14] powerpc/64s: cpuidle read mostly for common globals

Ensure these don't get put into bouncing cachelines. Signed-off-by: Nicholas Piggin --- drivers/cpuidle/cpuidle-powernv.c | 10 +- drivers/cpuidle/cpuidle-pseries.c | 8 2 files changed, 9 insertions(+), 9 deletions(-) diff --git

[PATCH 10/14] powerpc/64s: cpuidle set polling before enabling irqs

local_irq_enable can cause interrupts to be taken which could take significant amount of processing time. The idle process should set its polling flag before this, so another process that wakes it during this time will not have to send an IPI. Expand the TIF_POLLING_NRFLAG coverage to as large as

[PATCH 09/14] powerpc/64s: idle hmi wakeup is unlikely

In a busy system, idle wakeups can be expected from IPIs and device interrupts. Signed-off-by: Nicholas Piggin --- arch/powerpc/kernel/idle_book3s.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/idle_book3s.S

[PATCH 08/14] powerpc/64s: idle avoid SRR usage in idle sleep/wake paths

Idle code now always runs at the 0xc... effective address whether in real or virtual mode. This means rfid can be ditched, along with a lot of SRR manipulations. In the wakeup path, carry SRR1 around in r12. Use mtmsrd to change MSR states as required. This also balances the return prediction

[PATCH 07/14] powerpc/64s: idle branch to handler with virtual mode offset

Have the system reset idle wakeup handlers branched to in real mode with the 0xc... kernel address applied. This allows simplifications of avoiding rfid when switching to virtual mode in the wakeup handler. Signed-off-by: Nicholas Piggin ---

[PATCH 06/14] powerpc/64s: interrupt replay balance the return branch predictor

The __replay_interrupt code is branched to with bl, but the caller is returned to directly with rfid from the interrupt. Instead return to a return stub that returns to the caller with blr, which should do better with the return predictor. Signed-off-by: Nicholas Piggin ---

[PATCH 05/14] powerpc/64s: msgclr when handling doorbell exceptions

msgsnd doorbell exceptions are cleared when the doorbell interrupt is taken. However if a doorbell exception causes a system reset interrupt wake from power saving state, the message is not cleared. Processing the doorbell from the system reset interrupt requires msgclr to avoid taking the

[PATCH 04/14] powerpc/64s: idle process interrupts from system reset wakeup

When the CPU wakes from low power state, it begins at the system reset interrupt with the exception that caused the wakeup encoded in SRR1. Today, powernv idle wakeup ignores the wakeup reason (except a special case for HMI), and the regular interrupt corresponding to the exception will fire

[PATCH 03/14] powerpc/64s: idle provide a default idle for POWER9

Before the cpuidle driver is enabled, provide a default idle function similarly to POWER7/8. This should not have much effect, because the cpuidle driver for powernv is mandatory, but if that changes we should have a fallback. Signed-off-by: Nicholas Piggin ---

[PATCH 02/14] powerpc/64s: idle hotplug lazy-irq simplification

Rather than concern ourselves with any soft-mask logic in the CPU hotplug handler, just hard disable interrupts. This ensures there are no lazy-irqs pending, which means we can call directly to idle instruction in order to sleep. Signed-off-by: Nicholas Piggin ---

[PATCH 01/14] powerpc/64s: idle move soft interrupt mask logic into C code

This simplifies the asm and fixes irq-off tracing over sleep instructions. Also move powersave_nap check for POWER8 into C code, and move PSSCR register value calculation for POWER9 into C. Signed-off-by: Nicholas Piggin --- arch/powerpc/include/asm/hw_irq.h| 3 ++

[PATCH 00/14 v2] idle performance improvements

I rebased this on the powerpc next tree. A couple of things are changed since last post: - Patch 1 now properly accounts for the fact the powernv idle wakeups do not re-enable interrupts until the cpuidle driver enables them. This was not quite right in the previous patch (and

[PATCH 00/14 v2] idle performance improvements

I rebased this on the powerpc next tree. A couple of things are changed since last post: - Patch 1 now properly accounts for the fact the powernv idle wakeups do not re-enable interrupts until the cpuidle driver enables them. This was not quite right in the previous patch (and