[PATCH] powerpc/perf: Update raw-event code encoding comment for power8

Comment explanning the raw event code encoding for Power8 was moved to isa207_common.h file when re-factoring the code to support power9. But then Power9 pmu branched out due to changes specific to power9. So move the encoding comment back to power8-pmu.c Just comment movement and no logic change.

Re: [PATCH v2 6/7] ocxl: Add an IOCTL so userspace knows what CPU features are available

On Tue, 2018-05-08 at 13:50 +1000, Nicholas Piggin wrote: > On Tue, 08 May 2018 10:41:55 +1000 > "Alastair D'Silva" wrote: > > > On Mon, 2018-05-07 at 20:14 +0200, Frederic Barrat wrote: > > > > > > Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : > > > > From: Alastair

Re: [PATCH v2 6/7] ocxl: Add an IOCTL so userspace knows what CPU features are available

On Tue, 08 May 2018 10:41:55 +1000 "Alastair D'Silva" wrote: > On Mon, 2018-05-07 at 20:14 +0200, Frederic Barrat wrote: > > > > Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : > > > From: Alastair D'Silva > > > > > > In order for a userspace

Re: [PATCH 04/15] powerpc/powernv: opal-kmsg use flush fallback from console code

On Mon, 07 May 2018 20:36:39 +1000 Michael Ellerman wrote: > Nicholas Piggin writes: > > On Fri, 04 May 2018 15:16:37 +1000 > > Michael Ellerman wrote: > >> Nicholas Piggin writes: > >> > Use the more refined

Re: [PATCH 08/15] powerpc/powernv: implement opal_put_chars_atomic

On Mon, 07 May 2018 20:35:42 +1000 Michael Ellerman wrote: > Nicholas Piggin writes: > > > On Tue, 01 May 2018 19:48:58 +1000 > > Benjamin Herrenschmidt wrote: > > > >> On Tue, 2018-05-01 at 00:55 +1000, Nicholas Piggin

Re: [PATCH v2 1/7] powerpc: Add TIDR CPU feature for Power9

On Mon, 2018-05-07 at 19:17 +0200, Frederic Barrat wrote: > > Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : > > From: Alastair D'Silva > > > > This patch adds a CPU feature bit to show whether the CPU has > > the TIDR register available, enabling as_notify/wait in

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

On Mon, May 7, 2018 at 2:48 AM Florian Weimer wrote: > On 05/03/2018 06:05 AM, Andy Lutomirski wrote: > > On Wed, May 2, 2018 at 7:11 PM Ram Pai wrote: > > > >> On Wed, May 02, 2018 at 09:23:49PM +, Andy Lutomirski wrote: > >>> > If I recall

Re: [PATCH 11/13] powerpc/eeh: Introduce eeh_set_irq_state()

On Fri, May 04, 2018 at 01:02:32PM +1000, Michael Ellerman wrote: > Sam Bobroff writes: > > > diff --git a/arch/powerpc/kernel/eeh_driver.c > > b/arch/powerpc/kernel/eeh_driver.c > > index f63a01d336ee..b3edd0df04b8 100644 > > --- a/arch/powerpc/kernel/eeh_driver.c > >

Re: [PATCH 07/13] powerpc/eeh: Clean up pci_ers_result handling

On Fri, May 04, 2018 at 04:58:01PM +1000, Russell Currey wrote: > On Wed, 2018-05-02 at 16:36 +1000, Sam Bobroff wrote: > > As EEH event handling progresses, a cumulative result of type > > pci_ers_result is built up by (some of) the eeh_report_*() functions > > using either: > > if (rc ==

Re: [PATCH v2 6/7] ocxl: Add an IOCTL so userspace knows what CPU features are available

On Mon, 2018-05-07 at 20:14 +0200, Frederic Barrat wrote: > > Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : > > From: Alastair D'Silva > > > > In order for a userspace AFU driver to call the Power9 specific > > OCXL_IOCTL_ENABLE_P9_WAIT, it needs to verify that it can

Re: [PATCH v2 3/7] powerpc: use task_pid_nr() for TID allocation

On Mon, 2018-05-07 at 19:37 +0200, Frederic Barrat wrote: > > Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : > > From: Alastair D'Silva > > > > The current implementation of TID allocation, using a global IDR, > > may > > result in an errant process starving the system

Re: [PATCH] cxl: disable the lazy approach for irqs in POWERVM environment.

On Mon, 2018-05-07 at 18:02 +0200, christophe lombard wrote: > > To answer to your questions, here is the timeline in the cxl driver > >1. call disable_irq() > >2. call plpar_hcall9() to attach a process element > During this phase, phyp (as described in CAPI PAPR document) >

Re: [PATCH v2 7/7] ocxl: Document new OCXL IOCTLs

Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : From: Alastair D'Silva Signed-off-by: Alastair D'Silva --- Acked-by: Frederic Barrat Fred Documentation/accelerators/ocxl.rst | 11 +++ 1 file

Re: [PATCH v2 6/7] ocxl: Add an IOCTL so userspace knows what CPU features are available

Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : From: Alastair D'Silva In order for a userspace AFU driver to call the Power9 specific OCXL_IOCTL_ENABLE_P9_WAIT, it needs to verify that it can actually make that call. Signed-off-by: Alastair D'Silva

Re: [PATCH v2 5/7] ocxl: Expose the thread_id needed for wait on p9

Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : From: Alastair D'Silva In order to successfully issue as_notify, an AFU needs to know the TID to notify, which in turn means that this information should be available in userspace so it can be communicated to the AFU.

Re: [PATCH v2 0/4] powerpc: wii_defconfig updates

I forgot to CC the right set of people/mailing lists on the cover letter. Sorry. Here it is: On Mon, May 07, 2018 at 04:20:15PM +0200, Jonathan Neuschäfer wrote: > v1: https://www.spinics.net/lists/kernel/msg2790389.html > https://www.spinics.net/lists/kernel/msg2790385.html > > In the

Re: [PATCH v2 4/7] ocxl: Rename pnv_ocxl_spa_remove_pe to clarify it's action

Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : From: Alastair D'Silva The function removes the process element from NPU cache. Signed-off-by: Alastair D'Silva --- Acked-by: Frederic Barrat

Re: [PATCH v2 3/7] powerpc: use task_pid_nr() for TID allocation

Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : From: Alastair D'Silva The current implementation of TID allocation, using a global IDR, may result in an errant process starving the system of available TIDs. Instead, use task_pid_nr(), as mentioned by the original

Re: [PATCH v2 2/7] powerpc: Use TIDR CPU feature to control TIDR allocation

Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : From: Alastair D'Silva Switch the use of TIDR on it's CPU feature, rather than assuming it is available based on architecture. Signed-off-by: Alastair D'Silva --- Reviewed-by: Frederic Barrat

Re: [PATCH v2 1/7] powerpc: Add TIDR CPU feature for Power9

Le 18/04/2018 à 03:08, Alastair D'Silva a écrit : From: Alastair D'Silva This patch adds a CPU feature bit to show whether the CPU has the TIDR register available, enabling as_notify/wait in userspace. Signed-off-by: Alastair D'Silva ---

Re: [PATCH] cxl: disable the lazy approach for irqs in POWERVM environment.

Le 24/03/2018 à 09:14, Benjamin Herrenschmidt a écrit : On Fri, 2018-03-23 at 17:17 +0100, christophe lombard wrote: Le 23/03/2018 à 03:14, Benjamin Herrenschmidt a écrit : On Thu, 2018-03-22 at 17:37 +0100, Christophe Lombard wrote: The cxl driver cannot disable the interrupt at the device

Re: [PATCH] cxl: Configure PSL to not use APC virtual machines

Le 17/04/2018 à 07:11, Vaibhav Jain a écrit : APC virtual machines arent used on POWER-9 chips and are already disabled in on-chip CAPP. They also need to be disabled on the PSL via 'PSL Data Send Control Register' by setting bit(47). This forces the PSL to send commands to CAPP with queue.id ==

Re: [PATCH v3] On ppc64le we HAVE_RELIABLE_STACKTRACE

On Fri, May 04, 2018 at 02:38:34PM +0200, Torsten Duwe wrote: > > The "Power Architecture 64-Bit ELF V2 ABI" says in section 2.3.2.3: > > [...] There are several rules that must be adhered to in order to ensure > reliable and consistent call chain backtracing: > > * Before a function calls any

[PATCH v2 3/4] powerpc: wii_defconfig: Enable Wii SDHCI driver

This allows access to the SD card and the BCM4318 Wifi module. Signed-off-by: Jonathan Neuschäfer --- Note that until some fixes in the interrupt controller drivers used on the Wii, the SDHCI controllers will not be usable. v2: - Patch added to the series ---

[PATCH v2 4/4] powerpc: wii_defconfig: Disable BCMA support

The B43 driver only needs CONFIG_SSB to support the WLAN card found in the Wii. Configure it accordingly, and disable BCMA bus support to save a bit of space. Signed-off-by: Jonathan Neuschäfer --- v2: - Patch added to the series --- arch/powerpc/configs/wii_defconfig |

[PATCH v2 2/4] powerpc: wii_defconfig: Enable GPIO-related options

Now that there's a GPIO driver for the Wii, let's enable the following drivers: - the GPIO driver itself - gpio-keys - gpio-poweroff - gpio-leds and a few LED triggers Signed-off-by: Jonathan Neuschäfer --- v2: - Set CONFIG_NEW_LEDS=y and CONFIG_LEDS_TRIGGERS=y, without

[PATCH v2 1/4] powerpc: wii_defconfig: Disable Ethernet driver support code

The Wii doesn't have built-in Ethernet and USB Ethernet adapters are in a different menu. Disable CONFIG_ETHERNET to save some space in support code for Ethernet drivers. Note that this patch doesn't disable any Ethernet drivers, because they are not enabled by default. Signed-off-by: Jonathan

[PATCH v2 0/4] powerpc: wii_defconfig updates

v1: https://www.spinics.net/lists/kernel/msg2790389.html https://www.spinics.net/lists/kernel/msg2790385.html In the previous version of patch 2, I forgot to set CONFIG_NEW_LEDS and CONFIG_LEDS_TRIGGERS, so the more specific LED-related options weren't actually enabled, due to Kconfig

[PATCH] powerpc/pseries: hcall_exit tracepoint retval should be signed

The hcall_exit() tracepoint has retval defined as unsigned long. That leads to humours results like: bash-3686 [009] d..2 854.134094: hcall_entry: opcode=24 bash-3686 [009] d..2 854.134095: hcall_exit: opcode=24 retval=18446744073709551609 It's normal for some hcalls to return

Re: [PATCH v3] powerpc, pkey: make protection key 0 less special

On Sun, 6 May 2018 13:10:43 -0700 Ram Pai wrote: > On Sat, May 05, 2018 at 02:39:56PM +0200, Michal Suchánek wrote: > > On Fri, 4 May 2018 14:45:07 -0700 > > Ram Pai wrote: > > > > > On Fri, May 04, 2018 at 02:31:10PM -0700, Dave Hansen wrote: > >

Re: [PATCH 2/2] powerpc: wii_defconfig: Enable GPIO-related options

On Mon, Apr 30, 2018 at 03:42:47PM +0200, Jonathan Neuschäfer wrote: > Now that there's a GPIO driver for the Wii, let's enable the following > drivers: > > - the GPIO driver itself > - gpio-keys > - gpio-poweroff > - gpio-leds and a few LED triggers > > Signed-off-by: Jonathan Neuschäfer

Re: [PATCH 04/15] powerpc/powernv: opal-kmsg use flush fallback from console code

Nicholas Piggin writes: > On Fri, 04 May 2018 15:16:37 +1000 > Michael Ellerman wrote: >> Nicholas Piggin writes: >> > Use the more refined and tested event polling loop from opal_put_chars >> > as the fallback console flush in the

Re: [PATCH 08/15] powerpc/powernv: implement opal_put_chars_atomic

Nicholas Piggin writes: > On Tue, 01 May 2018 19:48:58 +1000 > Benjamin Herrenschmidt wrote: > >> On Tue, 2018-05-01 at 00:55 +1000, Nicholas Piggin wrote: >> > The RAW console does not need writes to be atomic, so relax >> > opal_put_chars to be

[PATCH 3/3] hwmon: (ibmpowernv) Add energy sensors

This patch exports the accumulated power numbers of each power sensor maintained by OCC. Signed-off-by: Shilpasri G Bhat --- drivers/hwmon/ibmpowernv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwmon/ibmpowernv.c b/drivers/hwmon/ibmpowernv.c

[PATCH 2/3] hwmon: (ibmpowernv): Add support to read 64 bit sensors

The firmware has supported for reading sensor values of size u32. This patch adds support to use newer firmware functions which allows to read the sensors of size u64. Signed-off-by: Shilpasri G Bhat --- drivers/hwmon/ibmpowernv.c | 7 --- 1 file changed, 4

[PATCH 1/3] powernv: opal-sensor: Add support to read 64bit sensor values

This patch adds support to read 64-bit sensor values. This method is used to read energy sensors and counters which are of type u64. Signed-off-by: Shilpasri G Bhat --- arch/powerpc/include/asm/opal-api.h| 1 + arch/powerpc/include/asm/opal.h

[PATCH 0/3] Add support for energy sensors

This patch series provides support for adding energy sensors to ibmpowernv-hwmon driver. This patch adds support to read 64bit sensor values. Shilpasri G Bhat (3): powernv: opal-sensor: Add support to read 64bit sensor values hwmon: (ibmpowernv): Add support to read 64 bit sensors hwmon:

Re: [PATCH 4/4] powerpc: Allow LD_DEAD_CODE_DATA_ELIMINATION to be selected

On Mon, 7 May 2018 09:46:43 +0900 Masahiro Yamada wrote: > Hi Nicholas, > > 2018-04-20 19:41 GMT+09:00 Nicholas Piggin : > > On Fri, 20 Apr 2018 12:00:49 +0200 > > Mathieu Malaterre wrote: > > > >> On Fri, Apr 20, 2018 at

Re: [RFC PATCH 1/2] powerpc/kbuild: Use flags variables rather than overriding LD/CC/AS

On Mon, 7 May 2018 14:25:12 +0900 Masahiro Yamada wrote: > Hi. > > > 2018-04-30 10:23 GMT+09:00 Nicholas Piggin : > > The powerpc toolchain can compile combinations of 32/64 bit and > > big/little endian, so it's convenient to consider, e.g., >

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

On 05/03/2018 01:38 AM, Ram Pai wrote: This is a new requirement that I was not aware off. Its not documented anywhere AFAICT. Correct. All inheritance behavior was deliberately left unspecified. I'm surprised about the reluctance to fix the x86 behavior. Are there any applications at all

Re: [PATCH 06/10] powerpc/mm/radix: implement LPID based TLB flushes to be used by KVM

On Mon, 7 May 2018 15:15:26 +1000 Paul Mackerras wrote: > On Sun, May 06, 2018 at 05:37:27PM +1000, Nicholas Piggin wrote: > > Implement a local TLB flush for invalidating an LPID with variants for > > process or partition scope. And a global TLB flush for invalidating > > a

Re: [PATCH 4/4] powerpc/xive: prepare all hcalls to support long busy delays

On 05/07/2018 04:30 AM, Michael Ellerman wrote: > Benjamin Herrenschmidt writes: >> On Fri, 2018-05-04 at 20:42 +1000, Michael Ellerman wrote: >>> Cédric Le Goater writes: >>> This is not the case for the moment, but future releases of pHyp might

[PATCH v2 10/10] KVM: PPC: reimplements LOAD_VMX/STORE_VMX instruction mmio emulation with analyse_intr() input

From: Simon Guo This patch reimplements LOAD_VMX/STORE_VMX MMIO emulation with analyse_intr() input. When emulating the store, the VMX reg will need to be flushed so that the right reg val can be retrieved before writing to IO MEM. This patch also adds support for

[PATCH v2 09/10] KVM: PPC: expand mmio_vsx_copy_type to mmio_copy_type to cover VMX load/store elem types

From: Simon Guo VSX MMIO emulation uses mmio_vsx_copy_type to represent VSX emulated element size/type, such as KVMPPC_VSX_COPY_DWORD_LOAD, etc. This patch expands mmio_vsx_copy_type to cover VMX copy type, such as KVMPPC_VMX_COPY_BYTE(stvebx/lvebx), etc. As a result,

[PATCH v2 08/10] KVM: PPC: reimplements LOAD_VSX/STORE_VSX instruction mmio emulation with analyse_intr() input

From: Simon Guo This patch reimplements LOAD_VSX/STORE_VSX instruction MMIO emulation with analyse_intr() input. It utilizes VSX_FPCONV/VSX_SPLAT/SIGNEXT exported by analyse_instr() and handle accordingly. When emulating VSX store, the VSX reg will need to be flushed so

[PATCH v2 06/10] KVM: PPC: add giveup_ext() hook for PPC KVM ops

From: Simon Guo Currently HV will save math regs(FP/VEC/VSX) when trap into host. But PR KVM will only save math regs when qemu task switch out of CPU, or when returning from qemu code. To emulate FP/VEC/VSX mmio load, PR KVM need to make sure that math regs were

[PATCH v2 07/10] KVM: PPC: reimplement LOAD_FP/STORE_FP instruction mmio emulation with analyse_intr() input

From: Simon Guo This patch reimplements LOAD_FP/STORE_FP instruction MMIO emulation with analyse_intr() input. It utilizes the FPCONV/UPDATE properties exported by analyse_instr() and invokes kvmppc_handle_load(s)/kvmppc_handle_store() accordingly. For FP store MMIO

[PATCH v2 05/10] KVM: PPC: reimplement non-SIMD LOAD/STORE instruction mmio emulation with analyse_intr() input

From: Simon Guo This patch reimplements non-SIMD LOAD/STORE instruction MMIO emulation with analyse_intr() input. It utilizes the BYTEREV/UPDATE/SIGNEXT properties exported by analyse_instr() and invokes kvmppc_handle_load(s)/kvmppc_handle_store() accordingly. It also

[PATCH v2 04/10] KVM: PPC: add KVMPPC_VSX_COPY_WORD_LOAD_DUMP type support for mmio emulation

From: Simon Guo Some VSX instruction like lxvwsx will splat word into VSR. This patch adds VSX copy type KVMPPC_VSX_COPY_WORD_LOAD_DUMP to support this. Signed-off-by: Simon Guo Reviewed-by: Paul Mackerras ---

[PATCH v2 03/10] KVM: PPC: Fix a mmio_host_swabbed uninitialized usage issue when VMX store

From: Simon Guo When KVM emulates VMX store, it will invoke kvmppc_get_vmx_data() to retrieve VMX reg val. kvmppc_get_vmx_data() will check mmio_host_swabbed to decide which double word of vr[] to be used. But the mmio_host_swabbed can be uninitiazed during VMX store

[PATCH v2 02/10] KVM: PPC: mov nip/ctr/lr/xer registers to pt_regs in kvm_vcpu_arch

From: Simon Guo This patch moves nip/ctr/lr/xer registers from scattered places in kvm_vcpu_arch to pt_regs structure. cr register is "unsigned long" in pt_regs and u32 in vcpu->arch. It will need more consideration and may move in later patches. Signed-off-by: Simon

[PATCH v2 01/10] KVM: PPC: add pt_regs into kvm_vcpu_arch and move vcpu->arch.gpr[] into it

From: Simon Guo Current regs are scattered at kvm_vcpu_arch structure and it will be more neat to organize them into pt_regs structure. Also it will enable reimplementation of MMIO emulation code with analyse_instr() later. Signed-off-by: Simon Guo

[PATCH v2 00/10] KVM: PPC: reimplement mmio emulation with analyse_instr()

From: Simon Guo We already have analyse_instr() which analyzes instructions for the instruction type, size, addtional flags, etc. What kvmppc_emulate_loadstore() did is somehow duplicated and it will be good to utilize analyse_instr() to reimplement the code. The