Re: [PATCH] cpuidle/powernv : init all present cpus for deep states

Yes this needs to be sent to stable. Fixes: d405a98c ("powerpc/powernv: Move cpuidle related code from setup.c to new file")

[PATCH 1/2] powerpc/ptrace: Fix enforcement of DAWR contraints

Back when we first introduced the DAWR in this commit: 4ae7ebe952 powerpc: Change hardware breakpoint to allow longer ranges We screwed up the constraint making it a 1024 byte boundary rather than a 512. This makes the check overly permissive. Fortunately GDB is the only real user and it always

[PATCH 2/2] powerpc/ptrace: Fix setting 512B aligned breakpoints with PTRACE_SET_DEBUGREG

In this change: e2a800beac powerpc/hw_brk: Fix off by one error when validating DAWR region end We fixed setting the DAWR end point to its max value via PPC_PTRACE_SETHWDEBUG. Unfortunately we broke PTRACE_SET_DEBUGREG when setting a 512 byte aligned breakpoint. PTRACE_SET_DEBUGREG currently

[powerpc:merge 138/143] arch/powerpc/include/asm/ftrace.h:2:0: error: unterminated #ifndef

tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git merge head: 46cf23553743d51ea53be61efce633061fa47f17 commit: 900be8ab1549359ba980cfb042a043128204a963 [138/143] Automatic merge of branches 'master', 'next' and 'fixes' into merge config: powerpc-kilauea_defconfig

Re: [PATCH 2/2] KVM: PPC: Book3S HV: lockless tlbie for HPT hcalls

On Mon, May 14, 2018 at 02:04:10PM +1000, Michael Ellerman wrote: [snip] > OK good, in commit: > > c17b98cf6028 ("KVM: PPC: Book3S HV: Remove code for PPC970 processors") (Dec > 2014) > > So we should be able to do the patch below. > > cheers > > > diff --git

[PATCH] powerpc: Ensure gcc doesn't move around cache flushing in __patch_instruction

The current asm statement in __patch_instruction() for the cache flushes doesn't have a "volatile" statement and no memory clobber. That means gcc can potentially move it around (or move the store done by put_user past the flush). Add both to ensure gcc doesn't play games. Found by code

Re: [PATCH v2 05/10] KVM: PPC: reimplement non-SIMD LOAD/STORE instruction mmio emulation with analyse_intr() input

Hi Paul, On Thu, May 17, 2018 at 09:49:18AM +1000, Paul Mackerras wrote: > On Mon, May 07, 2018 at 02:20:11PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo > > > > This patch reimplements non-SIMD LOAD/STORE instruction MMIO emulation > > with analyse_intr()

Re: [PATCH v2 07/10] KVM: PPC: reimplement LOAD_FP/STORE_FP instruction mmio emulation with analyse_intr() input

On Thu, May 17, 2018 at 09:52:07AM +1000, Paul Mackerras wrote: > On Mon, May 07, 2018 at 02:20:13PM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo > > > > This patch reimplements LOAD_FP/STORE_FP instruction MMIO emulation with > > analyse_intr() input. It

Re: administrivia: mails containing HTML attachments

On 16/05/18 14:48, Stephen Rothwell wrote: Hi all, I have decided that any email sent to the linuxppc-dev mailing list that contains an HTML attachment (or is just an HTML email) will be rejected. The vast majority of such mail are spam (and I have to spend time dropping them manually at the

Re: [PATCH 07/14] powerpc: Add support for restartable sequences

On Wed, May 16, 2018 at 04:13:16PM -0400, Mathieu Desnoyers wrote: > - On May 16, 2018, at 12:18 PM, Peter Zijlstra pet...@infradead.org wrote: > > > On Mon, Apr 30, 2018 at 06:44:26PM -0400, Mathieu Desnoyers wrote: > >> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig > >> index

Re: [PATCH] selftests/powerpc: add test to verify rfi flush across a system call

"Naveen N. Rao" writes: > diff --git a/tools/testing/selftests/powerpc/utils.c > b/tools/testing/selftests/powerpc/utils.c > index d46916867a6f..c6b1d20ed3ba 100644 > --- a/tools/testing/selftests/powerpc/utils.c > +++ b/tools/testing/selftests/powerpc/utils.c >

Re: [PATCH v2 00/10] KVM: PPC: reimplement mmio emulation with analyse_instr()

On Mon, May 07, 2018 at 02:20:06PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > We already have analyse_instr() which analyzes instructions for the > instruction > type, size, addtional flags, etc. What kvmppc_emulate_loadstore() did is > somehow >

Re: [PATCH v2 07/10] KVM: PPC: reimplement LOAD_FP/STORE_FP instruction mmio emulation with analyse_intr() input

On Mon, May 07, 2018 at 02:20:13PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > This patch reimplements LOAD_FP/STORE_FP instruction MMIO emulation with > analyse_intr() input. It utilizes the FPCONV/UPDATE properties exported by > analyse_instr() and

Re: [PATCH v2 05/10] KVM: PPC: reimplement non-SIMD LOAD/STORE instruction mmio emulation with analyse_intr() input

On Mon, May 07, 2018 at 02:20:11PM +0800, wei.guo.si...@gmail.com wrote: > From: Simon Guo > > This patch reimplements non-SIMD LOAD/STORE instruction MMIO emulation > with analyse_intr() input. It utilizes the BYTEREV/UPDATE/SIGNEXT > properties exported by

Re: [PATCH] Revert "powerpc/64: Fix checksum folding in csum_add()"

On Tue, Apr 10, 2018 at 08:34:37AM +0200, Christophe Leroy wrote: > This reverts commit 6ad966d7303b70165228dba1ee8da1a05c10eefe. > > That commit was pointless, because csum_add() sums two 32 bits > values, so the sum is 0x1fffe at the maximum. > And then when adding upper part (1) and lower

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

On Wed, May 16, 2018 at 01:37:46PM -0700, Andy Lutomirski wrote: > On Wed, May 16, 2018 at 1:35 PM Ram Pai wrote: > > > On Tue, May 08, 2018 at 02:40:46PM +0200, Florian Weimer wrote: > > > On 05/08/2018 04:49 AM, Andy Lutomirski wrote: > > > >On Mon, May 7, 2018 at 2:48 AM

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

On Wed, May 16, 2018 at 1:52 PM Ram Pai wrote: > On Mon, May 14, 2018 at 02:01:23PM +0200, Florian Weimer wrote: > > On 05/09/2018 04:41 PM, Andy Lutomirski wrote: > > >Hmm. I can get on board with the idea that fork() / clone() / > > >pthread_create() are all just special

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

On Mon, May 14, 2018 at 02:01:23PM +0200, Florian Weimer wrote: > On 05/09/2018 04:41 PM, Andy Lutomirski wrote: > >Hmm. I can get on board with the idea that fork() / clone() / > >pthread_create() are all just special cases of the idea that the thread > >that*calls* them should have the right

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

On Wed, May 16, 2018 at 1:35 PM Ram Pai wrote: > On Tue, May 08, 2018 at 02:40:46PM +0200, Florian Weimer wrote: > > On 05/08/2018 04:49 AM, Andy Lutomirski wrote: > > >On Mon, May 7, 2018 at 2:48 AM Florian Weimer wrote: > > > > > >>On 05/03/2018 06:05

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

On Tue, May 08, 2018 at 02:40:46PM +0200, Florian Weimer wrote: > On 05/08/2018 04:49 AM, Andy Lutomirski wrote: > >On Mon, May 7, 2018 at 2:48 AM Florian Weimer wrote: > > > >>On 05/03/2018 06:05 AM, Andy Lutomirski wrote: > >>>On Wed, May 2, 2018 at 7:11 PM Ram Pai

Re: [PATCH 07/14] powerpc: Add support for restartable sequences

- On May 16, 2018, at 12:18 PM, Peter Zijlstra pet...@infradead.org wrote: > On Mon, Apr 30, 2018 at 06:44:26PM -0400, Mathieu Desnoyers wrote: >> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig >> index c32a181a7cbb..ed21a777e8c6 100644 >> --- a/arch/powerpc/Kconfig >> +++

Re: [PATCH 07/14] powerpc: Add support for restartable sequences

On Mon, Apr 30, 2018 at 06:44:26PM -0400, Mathieu Desnoyers wrote: > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig > index c32a181a7cbb..ed21a777e8c6 100644 > --- a/arch/powerpc/Kconfig > +++ b/arch/powerpc/Kconfig > @@ -223,6 +223,7 @@ config PPC > select HAVE_SYSCALL_TRACEPOINTS

Re: [PATCH] pkeys: Introduce PKEY_ALLOC_SIGNALINHERIT and change signal semantics

On 05/14/2018 08:34 AM, Florian Weimer wrote: >>> The initial PKRU value can currently be configured by the system >>> administrator.  I fear this approach has too many moving parts to be >>> viable. >> >> Honestly, I think we should drop that option. I don’t see how we can >> expect an

Re: [PATCH v4 2/2] cxl: Report the tunneled operations status

Le 14/05/2018 à 10:27, Philippe Bergheaud a écrit : Failure to synchronize the tunneled operations does not prevent the initialization of the cxl card. This patch reports the tunneled operations status via /sys. Signed-off-by: Philippe Bergheaud --- Thanks for adding

Re: [PATCH 7/7] cxlflash: Isolate external module dependencies

On Fri, May 11, 2018 at 02:06:19PM -0500, Uma Krishnan wrote: > Depending on the underlying transport, cxlflash has a dependency on either > the CXL or OCXL drivers, which are enabled via their Kconfig option. > Instead of having a module wide dependency on these config options, it is > better to

Re: [PATCH 6/7] cxlflash: Abstract hardware dependent assignments

On Fri, May 11, 2018 at 02:06:05PM -0500, Uma Krishnan wrote: > As a staging cleanup to support transport specific builds of the cxlflash > module, relocate device dependent assignments to header files. This will > avoid littering the core driver with conditional compilation logic. > >

Re: [PATCH 5/7] cxlflash: Add include guards to backend.h

On Fri, May 11, 2018 at 02:05:51PM -0500, Uma Krishnan wrote: > The new header file, backend.h, that was recently added is missing > the include guards. This commit adds the guards. > > Signed-off-by: Uma Krishnan Acked-by: Matthew R. Ochs

Re: [PATCH 3/7] cxlflash: Acquire semaphore before invoking ioctl services

On Fri, May 11, 2018 at 02:05:22PM -0500, Uma Krishnan wrote: > When a superpipe process that makes use of virtual LUNs is terminated or > killed abruptly, there is a possibility that the cxlflash driver could > hang and deprive other operations on the adapter. > > The release fop registered to

Re: [PATCH 2/7] cxlflash: Limit the debug logs in the IO path

On Fri, May 11, 2018 at 02:05:08PM -0500, Uma Krishnan wrote: > The kernel log can get filled with debug messages from send_cmd_ioarrin() > when dynamic debug is enabled for the cxlflash module and there is a lot > of legacy I/O traffic. > > While these messages are necessary to debug issues that

Re: [PATCH] cpuidle/powernv : init all present cpus for deep states

Akshay Adiga writes: > Init all present cpus for deep states instead of "all possible" cpus. > Init fails if the possible cpu is gaurded. Resulting in making only > non-deep states available for cpuidle/hotplug. Should this also head to stable? It means that for

Re: [PATCH 1/7] cxlflash: Yield to active send threads

On Fri, May 11, 2018 at 02:04:46PM -0500, Uma Krishnan wrote: > The following Oops may be encountered if the device is reset, i.e. EEH > recovery, while there is heavy I/O traffic: > > 59:mon> t > [c000200db64bb680] c00809264c40 cxlflash_queuecommand+0x3b8/0x500 >

Re: administrivia: mails containing HTML attachments

Stephen Rothwell writes: > I have decided that any email sent to the linuxppc-dev mailing list > that contains an HTML attachment (or is just an HTML email) will be > rejected. The vast majority of such mail are spam (and I have to spend > time dropping them manually at

[PATCH v4 4/4] powerpc/kbuild: move -mprofile-kernel check to Kconfig

This eliminates the workaround that requires disabling -mprofile-kernel by default in Kconfig. [ Note: this depends on https://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git kconfig-shell-v3 ] Signed-off-by: Nicholas Piggin --- Since v3: - Moved a stray

[PATCH v4 3/4] powerpc/kbuild: Use flags variables rather than overriding LD/CC/AS

The powerpc toolchain can compile combinations of 32/64 bit and big/little endian, so it's convenient to consider, e.g., `CC -m64 -mbig-endian` To be the C compiler for the purpose of invoking it to build target artifacts. So overriding the the CC variable to include these flags works for this

[PATCH v4 2/4] powerpc/kbuild: remove CROSS32 defines from top level powerpc Makefile

Switch VDSO32 build over to use CROSS32_COMPILE directly, and have it pass in -m32 after the standard c_flags. This allows endianness overrides to be removed and the endian and bitness flags moved into standard flags variables. Signed-off-by: Nicholas Piggin ---

[PATCH v4 1/4] powerpc/kbuild: set default generic machine type for 32-bit compile

Some 64-bit toolchains uses the wrong ISA variant for compiling 32-bit kernels, even with -m32. Debian's powerpc64le is one such case, and that is because it is built with --with-cpu=power8. So when cross compiling a 32-bit kernel with a 64-bit toolchain, set -mcpu=powerpc initially, which is the

[PATCH v4 0/4] powerpc patches for new Kconfig language

This series of patches improves th powerpc kbuild system. The motivation was to to be compatible with the new Kconfig scripting language that Yamada-san has proposed here: https://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git/?h=kconfig-shell-v3 I have tested on top of that

Re: [kernel, v3] powerpc/ioda: Use ibm, supported-tce-sizes for IOMMU page size mask

On Mon, 2018-05-14 at 09:39:22 UTC, Alexey Kardashevskiy wrote: > At the moment we assume that IODA2 and newer PHBs can always do 4K/64K/16M > IOMMU pages, however this is not the case for POWER9 and now skiboot > advertises the supported sizes via the device so we use that instead > of hard

Re: selftests/powerpc: fix exec benchmark

On Sat, 2018-05-12 at 03:35:24 UTC, Nicholas Piggin wrote: > The exec_target binary could segfault calling _exit(2) because r13 > is not set up properly (and libc looks at that when performing a > syscall). Call SYS_exit using syscall(2) which doesn't seem to > have this problem. > >

Re: macintosh/windfarm: fix spelling mistake: "ttarged" -> "ttarget"

On Thu, 2018-05-10 at 15:54:39 UTC, Colin King wrote: > From: Colin Ian King > > Trivial fix to spelling mistake in debug messages of a structure > field name > > Signed-off-by: Colin Ian King Applied to powerpc next, thanks.

Re: powerpc/powernv: Fix memtrace build when NUMA=n

On Thu, 2018-05-10 at 13:09:13 UTC, Michael Ellerman wrote: > Currently memtrace doesn't build if NUMA=n: > > In function ‘memtrace_alloc_node’: > arch/powerpc/platforms/powernv/memtrace.c:134:6: > error: the address of ‘contig_page_data’ will always evaluate as > ‘true’ >

Re: [1/3] powerpc/prom: Drop support for old FDT versions

On Wed, 2018-05-09 at 13:42:27 UTC, Michael Ellerman wrote: > In commit e6a6928c3ea1 ("of/fdt: Convert FDT functions to use > libfdt") (Apr 2014), the generic flat device tree code dropped support > for flat device tree's older than version 0x10 (16). > > We still have code in our CPU scanning to

Re: [v2] powerpc: platform: cell: spufs: Change return type to vm_fault_t

On Fri, 2018-04-20 at 17:32:39 UTC, Souptick Joarder wrote: > Use new return type vm_fault_t for fault handler. For > now, this is just documenting that the function returns > a VM_FAULT value rather than an errno. Once all instances > are converted, vm_fault_t will become a distinct type. > >

Re: [2/5] powerpc/lib: Fix feature fixup test of external branch

On Mon, 2018-04-16 at 14:39:02 UTC, Michael Ellerman wrote: > The expected case for this test was wrong, the source of the alternate > code sequence is: > > FTR_SECTION_ELSE > 2: or 2,2,2 > PPC_LCMPI r3,1 > beq 3f > blt 2b > b 3f > b

Re: [V1, 01/11] powerpc/mm/book3s64: Move book3s64 code to pgtable-book3s64

On Mon, 2018-04-16 at 11:27:14 UTC, "Aneesh Kumar K.V" wrote: > From: "Aneesh Kumar K.V" > > Only code movement and avoid #ifdef. > > Signed-off-by: Aneesh Kumar K.V Series applied to powerpc next, thanks.

Re: [PATCH v2] powerpc/powernv: Add queue mechanism for early messages

Deb McLemore writes: > Problem being solved is when issuing a BMC soft poweroff during IPL, > the poweroff was being lost so the machine would not poweroff. > > Opal messages were being received before the opal-power code > registered its notifiers. > > Alternatives

[PATCH] cpuidle/powernv : init all present cpus for deep states

Init all present cpus for deep states instead of "all possible" cpus. Init fails if the possible cpu is gaurded. Resulting in making only non-deep states available for cpuidle/hotplug. Signed-off-by: Akshay Adiga --- arch/powerpc/platforms/powernv/idle.c | 4

Re: [PATCH 00/17] Implement use of HW assistance on TLB table walk on 8xx

Le 11/05/2018 à 08:48, Michael Ellerman a écrit : Christophe Leroy writes: The purpose of this serie is to implement hardware assistance for TLB table walk on the 8xx. First part is to make L1 entries and L2 entries independant. For that, we need to alter ioremap

Re: [PATCH 05/17] powerpc: move io mapping functions into ioremap.c

Le 11/05/2018 à 08:01, Michael Ellerman a écrit : Christophe Leroy writes: [...] +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include I needed:

[PATCH v2 14/14] powerpc/8xx: Move SW perf counters in first 32kb of memory

In order to simplify time critical exceptions handling 8xx specific SW perf counters, this patch moves the counters into the begining of memory. This is possible because .text is readable and the counters are never modified outside of the handlers. By doing this, we avoid having to set a second

[PATCH v2 13/14] powerpc/mm: Use pte_fragment_alloc() on 8xx

In 16k page size mode, the 8xx need only 4k for a page table. This patch makes use of the pte_fragment functions in order to avoid wasting memory space Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/mmu-8xx.h | 4 +++

[PATCH v2 12/14] powerpc/mm: Make pte_fragment_alloc() common to PPC32 and PPC64

In order to allow the 8xx to handle pte_fragments, this patch makes it common to PPC32 and PPC64 by moving the related code to common files and by defining a new config item called CONFIG_NEED_PTE_FRAG Signed-off-by: Christophe Leroy ---

[PATCH v2 11/14] powerpc/8xx: Free up SPRN_SPRG_SCRATCH2

We can now use SPRN_M_TW in the DAR Fixup code, freeing SPRN_SPRG_SCRATCH2 Then SPRN_SPRG_SCRATCH2 may be used for something else in the future. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/head_8xx.S | 8 1 file changed, 4 insertions(+), 4

[PATCH v2 10/14] powerpc/8xx: reunify TLB handler routines

Each handler must not exceed 64 instructions to fit into the main exception area. Following the significant size reduction of TLB handler routines, the side handlers can be brought back close to the main part. In the worst case: Main part of ITLB handler is 45 insn, side part is 9 insn ==> total

[PATCH v2 09/14] powerpc/mm: Use hardware assistance in TLB handlers on the 8xx

Today, on the 8xx the TLB handlers do SW tablewalk by doing all the calculation in ASM, in order to match with the Linux page table structure. The 8xx offers hardware assistance which allows significant size reduction of the TLB handlers, hence also reduces the time spent in the handlers.

[PATCH v2 08/14] powerpc/8xx: Remove PTE_ATOMIC_UPDATES

commit 1bc54c03117b9 ("powerpc: rework 4xx PTE access and TLB miss") introduced non atomic PTE updates and started the work of removing PTE updates in TLB miss handlers, but kept PTE_ATOMIC_UPDATES for the 8xx with the following comment: /* Until my rework is finished, 8xx still needs atomic PTE

[PATCH v2 07/14] powerpc/8xx: set GUARDED attribute in the PMD directly

On the 8xx, the GUARDED attribute of the pages is managed in the L1 entry, therefore to avoid having to copy it into L1 entry at each TLB miss, we set it in the PMD. Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/nohash/32/pte-8xx.h | 3 ++-

[PATCH v2 06/14] powerpc/nohash32: allow setting GUARDED attribute in the PMD directly

On the 8xx, the GUARDED attribute of the pages is managed in the L1 entry, therefore to avoid having to copy it into L1 entry at each TLB miss, we have to set it in the PMD In order to allow this, this patch splits the VM alloc space in two parts, one for VM alloc and non Guarded IO, and one for

[PATCH v2 05/14] powerpc: use _ALIGN_DOWN macro for VMALLOC_BASE

Use _ALIGN_DOWN macro instead of open coding in define of VMALLOC_BASE Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/nohash/32/pgtable.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h

[PATCH v2 04/14] powerpc: common ioremap functions.

__ioremap(), ioremap(), ioremap_wc() et ioremap_prot() are very similar between PPC32 and PPC64, they can easily be made common. _PAGE_WRITE equals to _PAGE_RW on PPC32 _PAGE_RO and _PAGE_HWWRITE are 0 on PPC64 iounmap() can also be made common by renaming the PPC32 iounmap() as __iounmap() then

[PATCH v2 03/14] powerpc: make ioremap_bot common to PPC32 and PPC64

Today, early ioremap maps from IOREMAP_BASE down to up on PPC64 and from IOREMAP_TOP up to down on PPC32 This patchs modifies PPC32 behaviour to get same behaviour as PPC64 Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/pgtable.h | 29

[PATCH v2 02/14] powerpc: move io mapping functions into ioremap.c

This patch is the first of a serie that intends to make io mappings common to PPC32 and PPC64. It moves ioremap/unmap fonctions into a new file called ioremap.c with no other modification to the functions. For the time being, the PPC32 and PPC64 parts get enclosed into #ifdef. Following patches

[PATCH v2 01/14] Revert "powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED for CONFIG_SWAP"

This reverts commit 4f94b2c7462d9720b2afa7e8e8d4c19446bb31ce. That commit was buggy, as it used rlwinm instead of rlwimi. Instead of fixing that bug, we revert the previous commit in order to reduce the dependency between L1 entries and L2 entries Signed-off-by: Christophe Leroy

[PATCH v2 00/14] Implement use of HW assistance on TLB table walk on 8xx

The purpose of this serie is to implement hardware assistance for TLB table walk on the 8xx. First part is to make L1 entries and L2 entries independant. For that, we need to alter ioremap functions in order to handle GUARD attribute at the PGD/PMD level. Last part is to reuse PTE fragment

Re: [PATCH 09/17] powerpc: make __ioremap_caller() common to PPC32 and PPC64

Le 08/05/2018 à 11:56, Aneesh Kumar K.V a écrit : Christophe Leroy writes: Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/64/pgtable.h | 1 + arch/powerpc/mm/ioremap.c| 126

RE: [PATCH 5/6 v3] bus: fsl-mc: supoprt dma configure for devices on fsl-mc bus

> -Original Message- > From: Laurentiu Tudor > Sent: Monday, May 14, 2018 7:10 PM > To: Nipun Gupta ; robin.mur...@arm.com; > will.dea...@arm.com; mark.rutl...@arm.com; catalin.mari...@arm.com > Cc: h...@lst.de; gre...@linuxfoundation.org; j...@8bytes.org; >

[PATCH v4 4/4] powerpc:selftest update memcmp_64 selftest for VMX implementation

From: Simon Guo This patch reworked selftest memcmp_64 so that memcmp selftest can cover more test cases. It adds testcases for: - memcmp over 4K bytes size. - s1/s2 with different/random offset on 16 bytes boundary. - enter/exit_vmx_ops pairness. Signed-off-by: Simon

[PATCH v4 3/4] powerpc/64: add 32 bytes prechecking before using VMX optimization on memcmp()

From: Simon Guo This patch is based on the previous VMX patch on memcmp(). To optimize ppc64 memcmp() with VMX instruction, we need to think about the VMX penalty brought with: If kernel uses VMX instruction, it needs to save/restore current thread's VMX registers.

[PATCH v4 2/4] powerpc/64: enhance memcmp() with VMX instruction for long bytes comparision

From: Simon Guo This patch add VMX primitives to do memcmp() in case the compare size exceeds 4K bytes. KSM feature can benefit from this. Test result with following test program(replace the "^>" with ""): -- ># cat

[PATCH v4 1/4] powerpc/64: Align bytes before fall back to .Lshort in powerpc64 memcmp()

From: Simon Guo Currently memcmp() 64bytes version in powerpc will fall back to .Lshort (compare per byte mode) if either src or dst address is not 8 bytes aligned. It can be opmitized in 2 situations: 1) if both addresses are with the same offset with 8 bytes boundary:

[PATCH v4 0/4] powerpc/64: memcmp() optimization

From: Simon Guo There is some room to optimize memcmp() in powerpc 64 bits version for following 2 cases: (1) Even src/dst addresses are not aligned with 8 bytes at the beginning, memcmp() can align them and go with .Llong comparision mode without fallback to .Lshort

Re: [PATCH v2] powerpc: kvm: Change return type to vm_fault_t

On Wed, May 16, 2018 at 12:38 PM, Paul Mackerras wrote: > On Wed, May 16, 2018 at 10:11:11AM +0530, Souptick Joarder wrote: >> On Thu, May 10, 2018 at 11:57 PM, Souptick Joarder >> wrote: >> > Use new return type vm_fault_t for fault handler >> > in

Re: [PATCH v2 2/2] i2c: busses: make use of i2c_8bit_addr_from_msg

Hello Peter, On Wed, May 16, 2018 at 09:16:47AM +0200, Peter Rosin wrote: > Acked-by: Uwe Kleine-König [emf32 and imx] s/emf/efm/ Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König| Industrial Linux Solutions

Re: administrivia: mails containing HTML attachments

On Wed, May 16, 2018 at 02:48:29PM +1000, Stephen Rothwell wrote: > Hi all, > > I have decided that any email sent to the linuxppc-dev mailing list > that contains an HTML attachment (or is just an HTML email) will be > rejected. The vast majority of such mail are spam (and I have to spend >

[PATCH v2 2/2] i2c: busses: make use of i2c_8bit_addr_from_msg

Because it looks neater. For diolan, this allows factoring out some code that is now common between if and else. For eg20t, pch_i2c_writebytes is always called with a write in msgs->flags, and pch_i2c_readbytes with a read. For imx, i2c_imx_dma_write and i2c_imx_write are always called with a

[PATCH v2 1/2] i2c: algos: make use of i2c_8bit_addr_from_msg

Because it looks neater. Signed-off-by: Peter Rosin --- drivers/i2c/algos/i2c-algo-bit.c | 4 +--- drivers/i2c/algos/i2c-algo-pca.c | 5 + drivers/i2c/algos/i2c-algo-pcf.c | 8 ++-- 3 files changed, 4 insertions(+), 13 deletions(-) diff --git

[PATCH v2 0/2] i2c: make use of i2c_8bit_addr_from_msg

Hi! The nice little inline i2c_8bit_addr_from_msg is not getting enough use. This series improves the situation and drops a bunch of lines in the process. I have only compile-tested (that part fine, at least over here). Changes since v1 https://lkml.org/lkml/2018/5/14/919 - Squashed

Re: [RFC] powerpc/emulate_step: Fix kernel crash when VSX is not present

[Adding Mikey] Ravi Bangoria wrote: emulate_step() is not checking runtime VSX feature flag before emulating an instruction. This can cause kernel oops when kernel is compiled with CONFIG_VSX=y but running on machine where VSX is not supported or disabled. Ex, while running emulate_step tests

Re: [PATCH v2] powerpc: kvm: Change return type to vm_fault_t

On Wed, May 16, 2018 at 10:11:11AM +0530, Souptick Joarder wrote: > On Thu, May 10, 2018 at 11:57 PM, Souptick Joarder > wrote: > > Use new return type vm_fault_t for fault handler > > in struct vm_operations_struct. For now, this is > > just documenting that the function

[PATCH] powerpc: get rid of PMD_PAGE_SIZE() and _PMD_SIZE

PMD_PAGE_SIZE() is nowhere used and _PMD_SIZE is only used by PMD_PAGE_SIZE(). This patch removes them. Signed-off-by: Christophe Leroy --- Superseeds "powerpc: get rid of PMD_PAGE_SIZE()" sent a few minutes ago. arch/powerpc/include/asm/nohash/32/pte-40x.h | 3 ---

Re: [PATCH v2] powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()

On Wednesday 16 May 2018 12:18 PM, ppaidipe wrote: On 2018-05-16 12:05, Anju T Sudhakar wrote: Currently memory is allocated for core-imc based on cpu_present_mask, which has bit 'cpu' set iff cpu is populated. We use (cpu number / threads per core) as the array index to access the memory.

[PATCH] powerpc: get rid of PMD_PAGE_SIZE()

PMD_PAGE_SIZE() is nowhere used, this patch removes it Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/nohash/32/pte-40x.h | 2 -- arch/powerpc/include/asm/pte-common.h| 5 - 2 files changed, 7 deletions(-) diff --git

Re: [PATCH v2] powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()

On 2018-05-16 12:05, Anju T Sudhakar wrote: Currently memory is allocated for core-imc based on cpu_present_mask, which has bit 'cpu' set iff cpu is populated. We use (cpu number / threads per core) as the array index to access the memory. Under some circumstances firmware marks a CPU as

Re: [PATCH v10 23/25] mm: add speculative page fault vmstats

On 16/05/2018 04:50, Ganesh Mahendran wrote: > 2018-04-17 22:33 GMT+08:00 Laurent Dufour : >> Add speculative_pgfault vmstat counter to count successful speculative page >> fault handling. >> >> Also fixing a minor typo in include/linux/vm_event_item.h. >> >>

[PATCH v2] powerpc/perf: Fix memory allocation for core-imc based on num_possible_cpus()

Currently memory is allocated for core-imc based on cpu_present_mask, which has bit 'cpu' set iff cpu is populated. We use (cpu number / threads per core) as the array index to access the memory. Under some circumstances firmware marks a CPU as GUARDed CPU and boot the system, until cleared of