linux-next: manual merge of the powerpc tree with Linus' tree

Hi all, Today's linux-next merge of the powerpc tree got a conflict in: Documentation/admin-guide/kernel-parameters.txt between commits: 05736e4ac13c ("cpu/hotplug: Provide knobs to control SMT") 506a66f37489 ("Revert "x86/apic: Ignore secondary threads if nosmt=force"") from Linus' tree

Re: [PATCH 0/2] Use ARRAY_SIZE to replace its implementation

> "Use ARRAY_SIZE to replace its implementation" Um, the subject line doesn't make sense. David

[PATCH v2 4/4] powerpc/mm: remove unnecessary test in pgtable_cache_init()

pgtable_cache_add() gracefully handles the case when a cache that size already exists by returning early with the following test: if (PGT_CACHE(shift)) return; /* Already have a cache of this size */ It is then not needed to test the existence of the cache before. Signed-

[PATCH v2 3/4] powerpc/mm: fix a warning when a cache is common to PGD and hugepages

While implementing TLB miss HW assistance on the 8xx, the following warning was encountered: [ 423.732965] WARNING: CPU: 0 PID: 345 at mm/slub.c:2412 ___slab_alloc.constprop.30+0x26c/0x46c [ 423.733033] CPU: 0 PID: 345 Comm: mmap Not tainted 4.18.0-rc8-00664-g2dfff9121c55 #671 [ 423.733075] N

[PATCH v2 2/4] powerpc/mm: replace hugetlb_cache by PGT_CACHE(PTE_T_ORDER)

Instead of opencoding cache handling for the special case of hugepage tables having a single pte_t element, this patch makes use of the common pgtable_cache helpers Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/hugetlb.h | 2 -- arch/powerpc/mm/hugetlbpage.c | 26 +++

[PATCH v2 1/4] powerpc/mm: enable the use of page table cache of order 0

hugepages uses a cache of order 0. Lets allow page tables of order 0 in the common part in order to avoid open coding in hugetlb Signed-off-by: Christophe Leroy --- arch/powerpc/include/asm/book3s/32/pgalloc.h | 5 + arch/powerpc/include/asm/book3s/64/pgalloc.h | 5 + arch/powerpc/includ

Re: [PATCH] powerpc/perf: Update perf_regs structure to include SIER

Hi arnaldo, Any comments or ack for this patch. With regards Maddy On Tuesday 10 July 2018 03:59 PM, Madhavan Srinivasan wrote: On each sample, Sample Instruction Event Register (SIER) content is saved in pt_regs. SIER does not have a entry as-is in the pt_regs but instead, SIER content is sav

Re: [PATCH] powerpc/perf: Update perf_regs structure to include SIER

On 08/14/2018 03:46 PM, Madhavan Srinivasan wrote: > Hi arnaldo, > > Any comments or ack for this patch. Tested-by: Ravi Bangoria Thanks, Ravi

Re: [PATCH v7 7/9] powerpc/pseries: Dump the SLB contents on SLB MCE errors.

On 08/14/2018 04:27 PM, Mahesh Jagannath Salgaonkar wrote: On 08/13/2018 07:57 PM, Nicholas Piggin wrote: On Mon, 13 Aug 2018 09:47:04 +0530 Mahesh Jagannath Salgaonkar wrote: On 08/11/2018 10:03 AM, Nicholas Piggin wrote: On Tue, 07 Aug 2018 19:47:39 +0530 Mahesh J Salgaonkar wrote: F

[PATCH V3] ocxl: Fix access to the AFU Descriptor Data

The AFU Information DVSEC capability is a means to extract common, general information about all of the AFUs associated with a Function independent of the specific functionality that each AFU provides. Write in the AFU Index field allows to access to the descriptor data for each AFU. With the curr

Re: [PATCH V2] ocxl: Fix access to the AFU Descriptor Data

Le 14/08/2018 à 05:26, Michael Ellerman a écrit : Hi Christophe, The patch looks fine, just a nit about the change log: Christophe Lombard writes: The AFU Information DVSEC capability is a means to extract common, general information about all of the AFUs associated with a Function independen

Re: [PATCH v7 7/9] powerpc/pseries: Dump the SLB contents on SLB MCE errors.

On 08/13/2018 07:57 PM, Nicholas Piggin wrote: > On Mon, 13 Aug 2018 09:47:04 +0530 > Mahesh Jagannath Salgaonkar wrote: > >> On 08/11/2018 10:03 AM, Nicholas Piggin wrote: >>> On Tue, 07 Aug 2018 19:47:39 +0530 >>> Mahesh J Salgaonkar wrote: >>> From: Mahesh Salgaonkar If we

Re: [PATCH 2/2] powerpc: Use ARRAY_SIZE to replace its implementation

On 2018/8/14 17:28, Michael Ellerman wrote: > zhong jiang writes: >> Use ARRAY_SIZE instead of dividing sizeof array with sizeof an element. >> So just replace it. >> >> Signed-off-by: zhong jiang >> --- >> arch/powerpc/xmon/ppc-opc.c | 12 >> 1 file changed, 4 insertions(+), 8 dele

Re: [PATCH 1/3] powerpc/mm: fix a warning when a cache is common to PGD and hugepages

Le 13/08/2018 à 15:44, Aneesh Kumar K.V a écrit : On 08/13/2018 06:57 PM, Christophe Leroy wrote: While implementing TLB miss HW assistance on the 8xx, the following warning was encountered: [  423.732965] WARNING: CPU: 0 PID: 345 at mm/slub.c:2412 ___slab_alloc.constprop.30+0x26c/0x46c [ 

Re: [PATCH 2/2] powerpc: Use ARRAY_SIZE to replace its implementation

zhong jiang writes: > Use ARRAY_SIZE instead of dividing sizeof array with sizeof an element. > So just replace it. > > Signed-off-by: zhong jiang > --- > arch/powerpc/xmon/ppc-opc.c | 12 > 1 file changed, 4 insertions(+), 8 deletions(-) This code is copied from binutils and we do

[PATCH 1/2] powerpc/process: fix nested output in show_user_instructions()

When two processes crash at the same time, we sometimes encounter nesting in the middle of a line: [4.365317] init[1]: segfault (11) at 0 nip 0 lr 0 code 1 [4.370452] init[1]: code: [4.372042] init[74]: segfault (11) at 10a74 nip 1000c198 lr 100078c8

[PATCH 2/2] powerpc/process: Constify the number of insns printed by show instructions functions.

instructions_to_print var is assigned value 16 and there is no way to change it. This patch replaces it by a constant. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/process.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/kernel/process.c