Le 21/02/2019 à 07:31, Christophe Leroy a écrit :
Le 21/02/2019 à 02:47, Michael Ellerman a écrit :
Christophe Leroy writes:
The purpose of this serie is to:
- use BATs with STRICT_KERNEL_RWX on book3s (See patch 13 for details.)
- use LTLBs with STRICT_KERNEL_RWX on 8xx (See patch 15
Yeah that's known, just forgot to send out the updated series. Will
do later today.
kbuild test robot's on February 21, 2019 3:40 am:
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
> next-test
> head: 9a065d2e3633d2f443ec01427265098ebe3a0e1f
> commit:
Le 21/02/2019 à 02:47, Michael Ellerman a écrit :
Christophe Leroy writes:
The purpose of this serie is to:
- use BATs with STRICT_KERNEL_RWX on book3s (See patch 13 for details.)
- use LTLBs with STRICT_KERNEL_RWX on 8xx (See patch 15 for a few details.)
This doesn't boot qemu-mac99 for
Alexey Kardashevskiy writes:
> The anon fd's ops releases the KVM reference in the release hook.
> However we reference the KVM object after we create the fd so there is
> small window when the release function can be called and
> dereferenced the KVM object which potentially may free it.
On Thu, 2019-02-21 at 10:55 +1100, Paul Mackerras wrote:
> On Wed, Feb 20, 2019 at 03:59:58PM +1100, Russell Currey wrote:
> > Using the hash MMU on P7+, the AMR is used for pkeys. It's
> > important
>
> This needs a bit of rewording. The "Using" ... "used" construct is a
> bit confusing on the
The anon fd's ops releases the KVM reference in the release hook.
However we reference the KVM object after we create the fd so there is
small window when the release function can be called and
dereferenced the KVM object which potentially may free it.
It is not a problem at the moment as the
Currently trying to build without IOMMU support will fail:
(.text+0x1380): undefined reference to `kvmppc_h_get_tce'
(.text+0x1384): undefined reference to `kvmppc_rm_h_put_tce'
(.text+0x149c): undefined reference to `kvmppc_rm_h_stuff_tce'
(.text+0x14a0): undefined reference to
Add the layerscape EP device support in pci_endpoint_test driver.
Signed-off-by: Xiaowei Bao
Reviewed-by: Minghuan Lian
Reviewed-by: Zhiqiang Hou
Reviewed-by: Greg KH
---
v2:
- no change
v3:
- no change
v4:
- delate the comments.
v5:
- no change.
v6:
- no change.
v7:
- no change.
Add the PCIe EP mode support for layerscape platform.
Signed-off-by: Xiaowei Bao
Reviewed-by: Minghuan Lian
Reviewed-by: Zhiqiang Hou
Reviewed-by: Kishon Vijay Abraham I
---
depends on: https://patchwork.kernel.org/project/linux-pci/list/?series=66177
v2:
- remove the EP mode check
Add the documentation for the Device Tree binding for the layerscape PCIe
controller with EP mode.
Signed-off-by: Xiaowei Bao
Reviewed-by: Minghuan Lian
Reviewed-by: Zhiqiang Hou
Reviewed-by: Rob Herring
---
v2:
- Add the SoC specific compatibles.
v3:
- modify the commit message.
v4:
- no
Add the PCIE EP node in dts for ls1046a.
Signed-off-by: Xiaowei Bao
Reviewed-by: Minghuan Lian
Reviewed-by: Zhiqiang Hou
Reviewed-by: Rob Herring
---
v2:
- Add the SoC specific compatibles.
v3:
- no change
v4:
- no change
v5:
- change the OB win number due to the RM update.
v6:
- no
-Original Message-
From: Lorenzo Pieralisi
Sent: 2019年2月20日 18:06
To: Xiaowei Bao
Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
shawn...@kernel.org; Leo Li ; kis...@ti.com; a...@arndb.de;
gre...@linuxfoundation.org; M.h. Lian ; Mingkai Hu
; Roy Zang ;
Hi Ira,
On Wed, Feb 20, 2019 at 11:01 AM wrote:
>
> From: Ira Weiny
>
> To facilitate additional options to get_user_pages_fast() change the
> singular write parameter to be gup_flags.
>
> This patch does not change any functionality. New functionality will
> follow in subsequent patches.
>
>
This adds an "in_guest" parameter to machine_check_print_event_info()
so that we can avoid trying to translate guest NIP values into
symbolic form using the host kernel's symbol table.
Reviewed-by: Aravinda Prasad
Reviewed-by: Mahesh Salgaonkar
Signed-off-by: Paul Mackerras
---
v2: add 'level'
This makes the handling of machine check interrupts that occur inside
a guest simpler and more robust, with less done in assembler code and
in real mode.
Now, when a machine check occurs inside a guest, we always get the
machine check event struct and put a copy in the vcpu struct for the
vcpu
Christophe Leroy writes:
> The purpose of this serie is to:
> - use BATs with STRICT_KERNEL_RWX on book3s (See patch 13 for details.)
> - use LTLBs with STRICT_KERNEL_RWX on 8xx (See patch 15 for a few details.)
This doesn't boot qemu-mac99 for me:
spawn
On Wed, Feb 20, 2019 at 04:41:54PM +, Jonathan Cameron wrote:
> On Mon, 18 Feb 2019 15:03:18 +0100
> Patrick Havelange wrote:
>
> > This driver exposes the counter for the quadrature decoder of the
> > FlexTimer Module, present in the LS1021A soc.
> >
> > Signed-off-by: Patrick Havelange
>
Hi Masahiro,
> It is fragile to rely on the compiler's optimization to avoid the
> section mismatch. Some functions may not be necessarily inlined
> when the compiler's inlining heuristic changes.
>
> Add __init markers consistently.
>
Are you doing this with some sort of static analysis, or
On Wed, Feb 20, 2019 at 03:59:58PM +1100, Russell Currey wrote:
> Using the hash MMU on P7+, the AMR is used for pkeys. It's important
This needs a bit of rewording. The "Using" ... "used" construct is a
bit confusing on the first read. Also, there was a processor called
P7+, but I think
Hello,
as documented in the top-level Makefile, "make modules_prepare" is
supposed to get a pristine kernel tree into a state that's suitable to
build out-of-tree modules. However, this is not the case for the
powerpc arch, since all modules are linked against
arch/powerpc/lib/crtsavres.o on
Hi Ira
Martin and I looked at your patch and agree that it doesn't change
functionality for Orangefs.
Reviewed-by: Mike Marshall
On Wed, Feb 20, 2019 at 12:32 AM wrote:
>
> From: Ira Weiny
>
> To facilitate additional options to get_user_pages_fast() change the
> singular write parameter
On 2/19/19 2:03 PM, Tyrel Datwyler wrote:
> On 02/19/2019 07:46 AM, Michael Bringmann wrote:
>> powerpc/pseries: Fix dn reference error in dlpar_cpu_remove_by_index()
>>
>> A reference to the device node of the CPU to be removed is released
>> upon successful removal of the associated CPU device.
On Wed, Feb 20, 2019 at 07:19:30AM -0800, Christoph Hellwig wrote:
> On Tue, Feb 19, 2019 at 09:30:33PM -0800, ira.we...@intel.com wrote:
> > From: Ira Weiny
> >
> > Resending these as I had only 1 minor comment which I believe we have
> > covered
> > in this series. I was anticipating these
On 20/02/2019 18:08, Peter Zijlstra wrote:
> On Wed, Feb 20, 2019 at 05:55:20PM +0100, Laurent Vivier wrote:
>> index 3f35ba1d8fde..372278605f0d 100644
>> --- a/kernel/sched/topology.c
>> +++ b/kernel/sched/topology.c
>> @@ -1651,6 +1651,7 @@ void sched_init_numa(void)
>> */
>> tl[i++]
Le 19/02/2019 à 18:23, Christophe Leroy a écrit :
This patch adds KASAN support for PPC32.
The KASAN shadow area is located between the vmalloc area and the
fixmap area.
KASAN_SHADOW_OFFSET is calculated in asm/kasan.h and extracted
by Makefile prepare rule via asm-offsets.h
For modules,
tree: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
next-test
head: 9a065d2e3633d2f443ec01427265098ebe3a0e1f
commit: 9a065d2e3633d2f443ec01427265098ebe3a0e1f [77/77] powerpc/64s: Fix data
interrupts vs d-side MCE reentrancy
config: powerpc-defconfig (attached as .config)
Le 25/01/2019 à 13:34, Christophe Leroy a écrit :
Use SPRN_SPRG5 to store the current thread PGDIR and
avoid reading thread_struct->pgdir at every TLB miss.
I'll send out v2 with an additional patch getting rid of SPRN_SPRG_RTAS
hence freeing SPRN_SPRG2 which I will use here instead of
We added runtime allocation of 16G pages in
commit 4ae279c2c96a ("powerpc/mm/hugetlb: Allow runtime allocation of 16G.")
That was done to enable 16G allocation on PowerNV and KVM config. In case of KVM
config, we mostly would have the entire guest RAM backed by 16G hugetlb pages
for
this to work.
On 8xx, large pages (512kb or 8M) are used to map kernel linear
memory. Aligning to 8M reduces TLB misses as only 8M pages are used
in that case. We make 8M the default for data.
This patchs allows the user to do it via Kconfig.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig
This patch implements handling of STRICT_KERNEL_RWX with
large TLBs directly in the TLB miss handlers.
To do so, etext and sinittext are aligned on 512kB boundaries
and the miss handlers use 512kB pages instead of 8Mb pages for
addresses close to the boundaries.
It sets RO PP flags for addresses
Depending on the number of available BATs for mapping the different
kernel areas, it might be needed to increase the alignment of _etext
and/or of data areas.
This patchs allows the user to do it via Kconfig.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 32
setibat() and clearibat() allows to manipulate IBATs independently
of DBATs.
update_bats() allows to update bats after init. This is done
with MMU off.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/32/mmu-hash.h | 2 ++
arch/powerpc/kernel/head_32.S | 35
Today, STRICT_KERNEL_RWX is based on the use of regular pages
to map kernel pages.
On Book3s 32, it has three consequences:
- Using pages instead of BAT for mapping kernel linear memory severely
impacts performance.
- Exec protection is not effective because no-execute cannot be set at
page level
This patch defined CONFIG_PPC_PAGE_SHIFT in order
to be able to use PAGE_SHIFT value inside Kconfig.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig| 7 +++
arch/powerpc/include/asm/page.h | 13 ++---
2 files changed, 9 insertions(+), 11 deletions(-)
diff
CONFIG_STRICT_KERNEL_RWX requires a special alignment
for DATA for some subarches. Today it is just defined
as an #ifdef in vmlinux.lds.S
In order to get more flexibility, this patch moves the
definition of this alignment in Kconfig
On some subarches, CONFIG_STRICT_KERNEL_RWX will
require a
Add a helper to know whether STRICT_KERNEL_RWX is enabled.
This is based on rodata_enabled flag which is defined only
when CONFIG_STRICT_KERNEL_RWX is selected.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/mmu.h | 11 +++
arch/powerpc/mm/init_32.c | 4 +---
2
wii_mmu_mapin_mem2() is not used anymore, remove it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/platforms/embedded6xx/wii.c | 28
1 file changed, 28 deletions(-)
diff --git a/arch/powerpc/platforms/embedded6xx/wii.c
b/arch/powerpc/platforms/embedded6xx/wii.c
When CONFIG_BDI_SWITCH is set, the page tables have to be populated
allthough large TLBs are used, because the BDI switch knows nothing
about those large TLBs which are handled directly in TLB miss logic.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/pgtable_32.c | 5 -
1 file
Do not set IBAT when setbat() is called without _PAGE_EXEC
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/ppc_mmu_32.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index 5fc59b195fef..ff8580c6ab11
This patch add an helper which wraps 'mtsrin' instruction
to write into segment registers.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index
At the time being, mmu_mapin_ram() always maps RAM from the beginning.
But some platforms like the WII have to map a second block of RAM.
This patch adds to mmu_mapin_ram() the base address of the block.
At the moment, only base address 0 is supported.
Signed-off-by: Christophe Leroy
---
This patch reworks mmu_mapin_ram() to be more generic and map as much
blocks as possible. It now supports blocks not starting at address 0.
It scans DBATs array to find free ones instead of forcing the use of
BAT2 and BAT3.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/ppc_mmu_32.c | 63
'nobats' kernel parameter or some options like CONFIG_DEBUG_PAGEALLOC
deny the use of BATS for mapping memory.
This patch makes sure that the specific wii RAM mapping function
takes it into account as well.
Fixes: de32400dd26e ("wii: use both mem1 and mem2 as ram")
Cc: sta...@vger.kernel.org
The purpose of this serie is to:
- use BATs with STRICT_KERNEL_RWX on book3s (See patch 13 for details.)
- use LTLBs with STRICT_KERNEL_RWX on 8xx (See patch 15 for a few details.)
v3:
- Reordered to avoid build failure due to setibat() not being used for several
steps in the serie.
Now the
Now that mmu_mapin_ram() is able to handle other blocks
than the one starting at 0, the WII can use it for all
its blocks.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/pgtable_32.c | 25 +++--
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git
On Wed, Feb 20, 2019 at 05:55:20PM +0100, Laurent Vivier wrote:
> index 3f35ba1d8fde..372278605f0d 100644
> --- a/kernel/sched/topology.c
> +++ b/kernel/sched/topology.c
> @@ -1651,6 +1651,7 @@ void sched_init_numa(void)
>*/
> tl[i++] = (struct sched_domain_topology_level){
>
When we hotplug a CPU in a memoryless/cpuless node, the kernel crashes when it
rebuilds the sched_domains data.
I reproduce this problem on POWER and with a pseries VM, with the following
QEMU parameters:
-machine pseries -enable-kvm -m 8192 \
-smp 2,maxcpus=8,sockets=4,cores=2,threads=1 \
On Mon, 18 Feb 2019 15:03:21 +0100
Patrick Havelange wrote:
> This is implemented by polling the counter value. A new parameter
> "poll-interval" can be set in the device tree, or can be changed
> at runtime. The reason for the polling is to avoid interrupts flooding.
> If the quadrature input
On Mon, 18 Feb 2019 15:03:18 +0100
Patrick Havelange wrote:
> This driver exposes the counter for the quadrature decoder of the
> FlexTimer Module, present in the LS1021A soc.
>
> Signed-off-by: Patrick Havelange
> Reviewed-by: Esben Haabendal
Given you cc'd William, I'm guessing you know
When we hotplug a CPU in a memoryless/cpuless node, the kernel crashes when it
rebuilds the sched_domains data.
I reproduce this problem on POWER and with a pseries VM, with the following
QEMU parameters:
-machine pseries -enable-kvm -m 8192 \
-smp 2,maxcpus=8,sockets=4,cores=2,threads=1 \
Le 20/02/2019 à 14:23, Michael Ellerman a écrit :
Christophe Leroy writes:
Le 15/01/2019 à 11:22, Michael Ellerman a écrit :
Christophe Leroy writes:
Le 15/01/2019 à 01:33, Jonathan Neuschäfer a écrit :
...
- patches 7 to 11 fail to build with this error (really a warning, but
On Tue, Feb 19, 2019 at 09:30:33PM -0800, ira.we...@intel.com wrote:
> From: Ira Weiny
>
> Resending these as I had only 1 minor comment which I believe we have covered
> in this series. I was anticipating these going through the mm tree as they
> depend on a cleanup patch there and the IB
On Wed, Feb 20, 2019 at 10:18:38PM +1100, Michael Ellerman wrote:
> Segher Boessenkool writes:
> > On Mon, Feb 18, 2019 at 11:49:18AM +1100, Michael Ellerman wrote:
> >> Balbir Singh writes:
> >> > Fair enough, my point was that the compiler can help out. I'll see what
> >> > -Wconversion finds
On Wed, Feb 13, 2019 at 05:00:15PM -0500, Waiman Long wrote:
> As the generic rwsem-xadd code is using the appropriate acquire and
> release versions of the atomic operations, the arch specific rwsem.h
> files will not be that much faster than the generic code as long as the
> atomic functions are
On Wed, Feb 13, 2019 at 05:00:16PM -0500, Waiman Long wrote:
> Currently, we have two different implementation of rwsem:
> 1) CONFIG_RWSEM_GENERIC_SPINLOCK (rwsem-spinlock.c)
> 2) CONFIG_RWSEM_XCHGADD_ALGORITHM (rwsem-xadd.c)
>
> As we are going to use a single generic implementation for
Nicholas Piggin's on January 22, 2019 4:46 pm:
> HV interrupts that use HSRR registers do not clear MSR[RI], but
> NMI entry code is not recoverable early on due to both using HSPRG
> for a scratch register.
>
> This bug means that a system reset or machine check can cause silent
> data
Hi powerpc maintainers,
what is the plan for this serries? I've not received any comments,
and although the series briefly appeared in the powerpc next-test
branch it disappeared again..
Le 20/02/2019 à 14:37, Michael Ellerman a écrit :
Christophe Leroy writes:
This patch moves the files related to page table dump in a
dedicated subdirectory.
The purpose is to clean a bit arch/powerpc/mm by regrouping
multiple files handling a dedicated function.
Signed-off-by:
> >> > > + * Order the stores above in vsnprintf() vs the store
> >> > > of the
> >> > > + * space below which joins the two strings. Note this
> >> > > doesn't
> >> > > + * make the code truly race free because there is no
> >> > > barrier on
> >> > >
Christophe Leroy writes:
> This patch moves the files related to page table dump in a
> dedicated subdirectory.
>
> The purpose is to clean a bit arch/powerpc/mm by regrouping
> multiple files handling a dedicated function.
>
> Signed-off-by: Christophe Leroy
> ---
> arch/powerpc/Kconfig.debug
Christophe Leroy writes:
> Le 15/01/2019 à 11:22, Michael Ellerman a écrit :
>> Christophe Leroy writes:
>>> Le 15/01/2019 à 01:33, Jonathan Neuschäfer a écrit :
>> ...
- patches 7 to 11 fail to build with this error (really a warning, but
arch/powerpc doesn't allow warnings
Nicholas Piggin writes:
> Aneesh Kumar K.V's on February 19, 2019 4:00 pm:
>> On 2/19/19 11:28 AM, Nicholas Piggin wrote:
>>> Aneesh Kumar K.V's on February 17, 2019 3:16 pm:
This patch maps vmap, IO and vmemap regions in the 0xc address range
instead of the current 0xd and 0xf range.
Mark Cave-Ayland writes:
> On 19/02/2019 04:20, Michael Ellerman wrote:
>> Mark Cave-Ayland writes:
> unexpectedly removed the MSR_FE0 and MSR_FE1 bits from the bitmask used to
> update the MSR of the previous thread in __giveup_fpu() causing a KVM-PR
> MacOS
> guest to lockup
On Fri, 2019-01-25 at 12:45 +0100, Christophe Leroy wrote:
> Hi Russel,
>
> Le 17/12/2018 à 08:09, Christophe Leroy a écrit :
> > Hi Russel,
> >
> > Le 10/12/2018 à 08:00, Russell Currey a écrit :
> > > __patch_instruction() is called in early boot, and uses
> > > __put_user_size(), which
On Wed, 2019-02-20 at 19:55 +1100, Michael Ellerman wrote:
> kvmhv_p9_guest_entry() implements a fast-path guest entry for Power9
> when guest and host are both running with the Radix MMU.
>
> Currently in that path we don't save the host AMR (Authority Mask
> Register) value, and we always
On Wed, 2019-02-20 at 12:45 +0530, Akshay Adiga wrote:
> On Wed, Feb 06, 2019 at 05:28:37PM +1100, Russell Currey wrote:
> > Without restoring the IAMR after idle, execution prevention on
> > POWER9
> > with Radix MMU is overwritten and the kernel can freely execute
> > userspace without
> >
On Wed, 2019-02-20 at 14:28 +0530, Akshay Adiga wrote:
> On Wed, Feb 06, 2019 at 05:28:37PM +1100, Russell Currey wrote:
> > Without restoring the IAMR after idle, execution prevention on
> > POWER9
> > with Radix MMU is overwritten and the kernel can freely execute
> > userspace without
> >
On Wed, 2019-02-20 at 11:34 +0530, Akshay Adiga wrote:
> On Tue, Feb 19, 2019 at 02:21:04PM +1000, Nicholas Piggin wrote:
> > Michael Ellerman's on February 8, 2019 11:04 am:
> > > Nicholas Piggin writes:
> > > > Russell Currey's on February 6, 2019 4:28 pm:
> > > > > Without restoring the IAMR
Segher Boessenkool writes:
> On Mon, Feb 18, 2019 at 11:49:18AM +1100, Michael Ellerman wrote:
>> Balbir Singh writes:
>> > Fair enough, my point was that the compiler can help out. I'll see what
>> > -Wconversion finds on my local build :)
>>
>> I get about 43MB of warnings here :)
>
> Yes,
On Wed, Feb 20, 2019 at 03:09:01AM +, Xiaowei Bao wrote:
>
>
> -Original Message-
> From: Lorenzo Pieralisi
> Sent: 2019年2月19日 19:27
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
>
Hi Michael,
On 20/02/19 6:20 AM, Michael Ellerman wrote:
> Sandipan Das writes:
>
>> This adds emulation support for the following integer instructions:
>> * Deliver A Random Number (darn)
>
> This doesn't build with old binutils. We need to support old binutils.
>
> {standard
Andrea Parri writes:
> On Mon, Feb 11, 2019 at 03:38:59PM +0100, Petr Mladek wrote:
>> On Mon 2019-02-11 13:50:35, Andrea Parri wrote:
>> > On Thu, Feb 07, 2019 at 11:46:29PM +1100, Michael Ellerman wrote:
>> > > Arch code can set a "dump stack arch description string" which is
>> > > displayed
On 2019-02-20 12:05:50 Wed, Paul Mackerras wrote:
> This makes the handling of machine check interrupts that occur inside
> a guest simpler and more robust, with less done in assembler code and
> in real mode.
>
> Now, when a machine check occurs inside a guest, we always get the
> machine check
On 2019-02-20 12:06:23 Wed, Paul Mackerras wrote:
> This adds an "in_guest" parameter to machine_check_print_event_info()
> so that we can avoid trying to translate guest NIP values into
> symbolic form using the host kernel's symbol table.
>
> Signed-off-by: Paul Mackerras
> ---
>
Scott Wood writes:
> On Wed, 2019-02-20 at 01:14 +1100, Michael Ellerman wrote:
>> Christophe Leroy writes:
>>
>> > On 02/08/2019 12:34 PM, Michael Ellerman wrote:
>> > > In commit 7820856a4fcd ("powerpc/mm/book3e/64: Remove unsupported
>> > > 64Kpage size from 64bit booke") we dropped the 64K
On Wednesday 20 February 2019 06:36 AM, Paul Mackerras wrote:
> This adds an "in_guest" parameter to machine_check_print_event_info()
> so that we can avoid trying to translate guest NIP values into
> symbolic form using the host kernel's symbol table.
Reviewed-by: Aravinda Prasad
Regards,
On Wednesday 20 February 2019 06:35 AM, Paul Mackerras wrote:
> This makes the handling of machine check interrupts that occur inside
> a guest simpler and more robust, with less done in assembler code and
> in real mode.
>
> Now, when a machine check occurs inside a guest, we always get the
>
On Wed, Feb 06, 2019 at 05:28:37PM +1100, Russell Currey wrote:
> Without restoring the IAMR after idle, execution prevention on POWER9
> with Radix MMU is overwritten and the kernel can freely execute userspace
> without
> faulting.
>
> This is necessary when returning from any stop state that
kvmhv_p9_guest_entry() implements a fast-path guest entry for Power9
when guest and host are both running with the Radix MMU.
Currently in that path we don't save the host AMR (Authority Mask
Register) value, and we always restore 0 on return to the host. That
is OK at the moment because the AMR
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