Hi
>
> Hi Shengjiu,
>
> On Fri, Mar 01, 2019 at 02:32:38AM +, S.j. Wang wrote:
> > There is a constraint for the channel number setting on the asrc of
> > older version (e.g. imx35), the channel number should be even, odd
> > number isn't valid.
> >
> > So add protection when the asrc of
Suraj Jitindar Singh writes:
> Add KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST &
> KVM_PPC_CPU_BEHAV_FLUSH_COUNT_CACHE to the characteristics returned from
> the H_GET_CPU_CHARACTERISTICS H-CALL, as queried from either the
> hypervisor or the device tree.
>
> Signed-off-by: Suraj Jitindar Singh
> ---
>
>
> It would be a mistake to remove S32_LE from the format list.
>
> If you removed that, then we wouldn't be able to do 32 bit native playback
> - it would force users to go through an ALSA plugin.
>
> If you look at the cs42448 data sheet for example, the I2S and TDM bus
> uses a 32 bit
In POWER9, OCC(On-Chip-Controller) provides for hard and soft system
powercapping range. The hard powercap range is guaranteed while soft
powercap may or may not be enforced by OCC due to various power-thermal
reasons based on system configuration and workloads. This patch adds
a sysfs file to
It would be a mistake to remove S32_LE from the format list.
If you removed that, then we wouldn't be able to do 32 bit native
playback - it would force users to go through an ALSA plugin.
If you look at the cs42448 data sheet for example, the I2S and TDM bus
uses a 32 bit word size. For
Hi Shengjiu,
On Thu, Feb 28, 2019 at 05:56:31AM +, S.j. Wang wrote:
> cs42xx8 is a 24-bit A/D and 24-bit D/A device, so the S32_LE
> should not be in the supported format list.
>
> Signed-off-by: Shengjiu Wang
> ---
> sound/soc/codecs/cs42xx8.c | 3 +--
This is for cs42xx8 codec driver,
Ignore this as I forgot to change v2 to v3 so I reposted this.
On 01/03/2019 15:34, Alexey Kardashevskiy wrote:
> We already allocate hardware TCE tables in multiple levels and skip
> intermediate levels when we can, now it is a turn of the KVM TCE tables.
> Thankfully these are allocated
We already allocate hardware TCE tables in multiple levels and skip
intermediate levels when we can, now it is a turn of the KVM TCE tables.
Thankfully these are allocated already in 2 levels.
This moves the table's last level allocation from the creating helper to
kvmppc_tce_put() and
We already allocate hardware TCE tables in multiple levels and skip
intermediate levels when we can, now it is a turn of the KVM TCE tables.
Thankfully these are allocated already in 2 levels.
This moves the table's last level allocation from the creating helper to
kvmppc_tce_put() and
Hi
> > cs42xx8 is a 24-bit A/D and 24-bit D/A device, so the S32_LE should
> > not be in the supported format list.
> >
> > Signed-off-by: Shengjiu Wang
>
> Is the device capable of accepting 32-bit samples, even if it downgrades it to
> 24-bit internally? If so, then maybe
Add KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST &
KVM_PPC_CPU_BEHAV_FLUSH_COUNT_CACHE to the characteristics returned from
the H_GET_CPU_CHARACTERISTICS H-CALL, as queried from either the
hypervisor or the device tree.
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/uapi/asm/kvm.h | 2 ++
Qian Cai writes:
> arch/powerpc/mm/hugetlbpage-hash64.c: In function '__hash_page_huge':
> arch/powerpc/mm/hugetlbpage-hash64.c:29:28: warning: variable 'sz' set
> but not used [-Wunused-but-set-variable]
It's always nice to know *why* it's not used.
It's unlikely, but not impossible, that it's
On 27/2/19 3:57 pm, Alastair D'Silva wrote:
From: Alastair D'Silva
Remove some unused exported symbols.
Signed-off-by: Alastair D'Silva > ---
drivers/misc/ocxl/config.c| 2 --
drivers/misc/ocxl/ocxl_internal.h | 26 +-
include/misc/ocxl.h |
On 01/03/2019 12:38, Alexey Kardashevskiy wrote:
> We already allocate hardware TCE tables in multiple levels and skip
> intermediate levels when we can, now it is a turn of the KVM TCE tables.
> Thankfully these are allocated already in 2 levels.
>
> This moves the table's last level
Hi Shengjiu,
On Fri, Mar 01, 2019 at 02:32:38AM +, S.j. Wang wrote:
> There is a constraint for the channel number setting on the
> asrc of older version (e.g. imx35), the channel number should
> be even, odd number isn't valid.
>
> So add protection when the asrc of older version is used.
>
There is a constraint for the channel number setting on the
asrc of older version (e.g. imx35), the channel number should
be even, odd number isn't valid.
So add protection when the asrc of older version is used.
Signed-off-by: Shengjiu Wang
---
sound/soc/fsl/fsl_asrc.c | 3 ++-
1 file
On Wed, 2019-02-27 at 12:40 +0800, Wen Yang wrote:
> The call to of_get_next_child returns a node pointer with refcount
> incremented thus it must be explicitly decremented after the last
> usage.
> irq_domain_add_linear also calls of_node_get to increase refcount,
> so irq_domain will not be
We already allocate hardware TCE tables in multiple levels and skip
intermediate levels when we can, now it is a turn of the KVM TCE tables.
Thankfully these are allocated already in 2 levels.
This moves the table's last level allocation from the creating helper to
kvmppc_tce_put() and
On Wed, Feb 27, 2019 at 08:17:58AM -0800, Paul E. McKenney wrote:
> On Wed, Feb 27, 2019 at 08:05:13AM -0800, Ricardo Neri wrote:
> > CPU architectures that have an NMI watchdog use arch_touch_nmi_watchdog()
> > to briefly ignore the hardlockup detector. If the architecture does not
> > have an
On Mon, 18 Feb 2019 15:03:20 +0100, Patrick Havelange wrote:
> New optional parameter supported by updated driver.
>
> Signed-off-by: Patrick Havelange
> Reviewed-by: Esben Haabendal
> ---
> .../devicetree/bindings/iio/counter/ftm-quaddec.txt | 8 +++-
> 1 file changed, 7
syscall_get_error() is required to be implemented on this
architecture in addition to already implemented syscall_get_nr(),
syscall_get_arguments(), syscall_get_return_value(), and
syscall_get_arch() functions in order to extend the generic
ptrace API with PTRACE_GET_SYSCALL_INFO request.
Cc:
Hi Russell,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[cannot apply to v5.0-rc8 next-20190228]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Michael
On Wed, 27 Feb 2019 14:28:43 +0530 "Aneesh Kumar K.V"
wrote:
> Andrew Morton writes:
>
> > [patch 1/5]: unreviewed and has unaddressed comments from mpe.
> > [patch 2/5]: ditto
> > [patch 3/5]: ditto
> > [patch 4/5]: seems ready
> > [patch 5/5]: reviewed by mpe, but appears to need more work
Add PTRACE_SYSEMU and PTRACE_SYSEMU_SINGLESTEP support on arm64.
We can just make sure of the generic ptrace_syscall_enter hook to
support PTRACE_SYSEMU. We don't need any special handling for
PTRACE_SYSEMU_SINGLESTEP.
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Sudeep Holla
---
x86 and um use 31 and 32 for PTRACE_SYSEMU and PTRACE_SYSEMU_SINGLESTEP
while powerpc uses different value maybe for legacy reasons.
Though handling of PTRACE_SYSEMU can be made architecture independent,
it's hard to make these definations generic. To add to this existing
mess few architectures
Now that we have a new hook ptrace_syscall_enter that can be called from
syscall entry code and it handles PTRACE_SYSEMU in generic code, we
can do some cleanup using the same in do_syscall_trace_enter.
Cc: Oleg Nesterov
Cc: Paul Mackerras
Cc: Michael Ellerman
Signed-off-by: Sudeep Holla
---
While the TIF_SYSCALL_EMU is set in ptrace_resume independent of any
architecture, currently only powerpc and x86 unset the TIF_SYSCALL_EMU
flag in ptrace_disable which gets called from ptrace_detach.
Let's move the clearing of TIF_SYSCALL_EMU flag to ptrace_detach after
we return from
Hi,
This patchset evolved from the discussion in the thread[0][1]. When we
wanted to add PTRACE_SYSEMU support to ARM64, we thought instead of
duplicating what other architectures like x86 and powerpc have done,
let consolidate the existing support and move it to the core as there's
nothing arch
Now that we have a new hook ptrace_syscall_enter that can be called from
syscall entry code and it handles PTRACE_SYSEMU in generic code, we
can do some cleanup using the same in syscall_trace_enter.
Further the extra logic to find single stepping PTRACE_SYSEMU_SINGLESTEP
in
Currently each architecture handles PTRACE_SYSEMU in very similar way.
It's completely arch independent and can be handled in the code helping
to consolidate PTRACE_SYSEMU handling.
Let's introduce a hook 'ptrace_syscall_enter' that arch specific syscall
entry code can call.
Cc: Oleg Nesterov
On Thu, Feb 28, 2019 at 1:40 AM Oliver wrote:
>
> On Thu, Feb 28, 2019 at 7:35 PM Aneesh Kumar K.V
> wrote:
> >
> > Add a flag to indicate the ability to do huge page dax mapping. On
> > architecture
> > like ppc64, the hypervisor can disable huge page support in the guest. In
> > such a case,
From: Madalin Bucur
[ Upstream commit 89857a8a5c89a406b967ab2be7bd2ccdbe75e73d ]
By clearing all interrupt sources, not only those that
already occurred, the existing code may acknowledge by
mistake interrupts that occurred after the code checks
for them.
Signed-off-by: Madalin Bucur
From: Madalin Bucur
[ Upstream commit 89857a8a5c89a406b967ab2be7bd2ccdbe75e73d ]
By clearing all interrupt sources, not only those that
already occurred, the existing code may acknowledge by
mistake interrupts that occurred after the code checks
for them.
Signed-off-by: Madalin Bucur
From: Madalin Bucur
[ Upstream commit 89857a8a5c89a406b967ab2be7bd2ccdbe75e73d ]
By clearing all interrupt sources, not only those that
already occurred, the existing code may acknowledge by
mistake interrupts that occurred after the code checks
for them.
Signed-off-by: Madalin Bucur
From: Madalin Bucur
[ Upstream commit 89857a8a5c89a406b967ab2be7bd2ccdbe75e73d ]
By clearing all interrupt sources, not only those that
already occurred, the existing code may acknowledge by
mistake interrupts that occurred after the code checks
for them.
Signed-off-by: Madalin Bucur
From: Russell Currey
Kernel Userspace Access Prevention utilises a feature of the Radix MMU
which disallows read and write access to userspace addresses. By
utilising this, the kernel is prevented from accessing user data from
outside of trusted paths that perform proper safety checks, such as
From: Russell Currey
__patch_instruction() is called in early boot, and uses
__put_user_size(), which includes the allow/prevent calls to enforce
KUAP, which could either be called too early, or in the Radix case,
forced to use "early_" versions of functions just to safely handle
this one case.
From: Russell Currey
Execution protection already exists on radix, this just refactors
the radix init to provide the KUEP setup function instead.
Thus, the only functional change is that it can now be disabled.
Signed-off-by: Russell Currey
Signed-off-by: Michael Ellerman
---
From: Russell Currey
Some platforms (i.e. Radix MMU) need per-CPU initialisation for KUP.
Any platforms that only want to do KUP initialisation once
globally can just check to see if they're running on the boot CPU, or
check if whatever setup they need has already been performed.
Note that
From: Christophe Leroy
This patch implements a framework for Kernel Userspace Access
Protection.
Then subarches will have the possibility to provide their own
implementation by providing setup_kuap() and
allow/prevent_user_access().
Some platforms will need to know the area accessed and
From: Christophe Leroy
This patch adds a skeleton for Kernel Userspace Execution Prevention.
Then subarches implementing it have to define CONFIG_PPC_HAVE_KUEP
and provide setup_kuep() function.
Signed-off-by: Christophe Leroy
[mpe: Don't split strings, use pr_crit_ratelimited()]
From: Christophe Leroy
This patch adds a skeleton for Kernel Userspace Protection
functionnalities like Kernel Userspace Access Protection and Kernel
Userspace Execution Prevention
The subsequent implementation of KUAP for radix makes use of a MMU
feature in order to patch out assembly when
In order to implement KUAP (Kernel Userspace Access Protection) on
Power9 we will be using the AMR, and therefore indirectly the
UAMOR/AMOR.
So save/restore these regs in the idle code.
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/idle_book3s.S | 27 +++
1
From: Russell Currey
Without restoring the IAMR after idle, execution prevention on POWER9
with Radix MMU is overwritten and the kernel can freely execute
userspace without faulting.
This is necessary when returning from any stop state that modifies
user state, as well as hypervisor state.
To
On 2/27/19 11:56 PM, S.j. Wang wrote:
cs42xx8 is a 24-bit A/D and 24-bit D/A device, so the S32_LE
should not be in the supported format list.
Signed-off-by: Shengjiu Wang
Is the device capable of accepting 32-bit samples, even if it downgrades
it to 24-bit internally? If so, then maybe
On Thu 28-02-19 13:20:03, Vlastimil Babka wrote:
> On 2/27/19 3:47 PM, Aneesh Kumar K.V wrote:
> > This patch adds PF_MEMALLOC_NOCMA which make sure any allocation in that
> > context
> > is marked non-movable and hence cannot be satisfied by CMA region.
> >
> > This is useful with
Le 28/02/2019 à 10:47, Andrey Ryabinin a écrit :
On 2/28/19 12:27 PM, Dmitry Vyukov wrote:
On Thu, Feb 28, 2019 at 10:22 AM Andrey Ryabinin
wrote:
On 2/27/19 4:11 PM, Christophe Leroy wrote:
Le 27/02/2019 à 10:19, Andrey Ryabinin a écrit :
On 2/27/19 11:25 AM, Christophe Leroy
Le 28/02/2019 à 09:31, Jason Yan a écrit :
This code is dead. Just remove it.
Signed-off-by: Jason Yan
Reviewed-by: Christophe Leroy
This review was easy :)
Christophe
---
arch/powerpc/kernel/head_fsl_booke.S | 7 ---
1 file changed, 7 deletions(-)
diff --git
On 2/28/19 3:10 PM, Oliver wrote:
On Thu, Feb 28, 2019 at 7:35 PM Aneesh Kumar K.V
wrote:
Add a flag to indicate the ability to do huge page dax mapping. On architecture
like ppc64, the hypervisor can disable huge page support in the guest. In
such a case, we should not enable huge page dax
On 2/28/19 2:51 PM, Jan Kara wrote:
On Thu 28-02-19 14:05:21, Aneesh Kumar K.V wrote:
Architectures like ppc64 use the deposited page table to store hardware
page table slot information. Make sure we deposit a page table when
using zero page at the pmd level for hash.
Without this we hit
On 2/28/19 3:10 PM, Jan Kara wrote:
On Thu 28-02-19 14:05:22, Aneesh Kumar K.V wrote:
Add a flag to indicate the ability to do huge page dax mapping. On architecture
like ppc64, the hypervisor can disable huge page support in the guest. In
such a case, we should not enable huge page dax
On 2/27/19 3:47 PM, Aneesh Kumar K.V wrote:
> This patch adds PF_MEMALLOC_NOCMA which make sure any allocation in that
> context
> is marked non-movable and hence cannot be satisfied by CMA region.
>
> This is useful with get_user_pages_longterm where we want to take a page pin
> by
> migrating
Mathieu Malaterre writes:
> On Tue, Feb 26, 2019 at 9:36 PM Jakub Drnec wrote:
>>
>> Hi all,
>>
>> I think I observed a potential problem, is this the correct place to report
>> it? (CC me, not on list)
>>
>> [1.] One line summary: monotonic clock can be made to decrease on ppc64
>> [2.] Full
Hello Russell,
On Fri, Feb 08, 2019 at 10:11:03PM +1100, Russell Currey wrote:
> Without restoring the IAMR after idle, execution prevention on POWER9
> with Radix MMU is overwritten and the kernel can freely execute userspace
> without
> faulting.
>
> This is necessary when returning from any
Hi Shilpa,
On Thu, Feb 28, 2019 at 11:25:25AM +0530, Shilpasri G Bhat wrote:
> Hi,
>
> On 02/28/2019 10:14 AM, Daniel Axtens wrote:
> > Shilpasri G Bhat writes:
> >
> >> In POWER9, OCC(On-Chip-Controller) provides for hard and soft system
> >> powercapping range. The hard powercap range is
Hello Thiago,
On Fri, Feb 22, 2019 at 07:57:52PM -0300, Thiago Jung Bauermann wrote:
> When testing DLPAR CPU add/remove on a system under stress,
> pseries_cpu_die() doesn't wait long enough for a CPU to die:
>
> [ 446.983944] cpu 148 (hwid 148) Ready to die...
> [ 446.984062] cpu 149 (hwid
On 2/28/19 12:27 PM, Dmitry Vyukov wrote:
> On Thu, Feb 28, 2019 at 10:22 AM Andrey Ryabinin
> wrote:
>>
>>
>>
>> On 2/27/19 4:11 PM, Christophe Leroy wrote:
>>>
>>>
>>> Le 27/02/2019 à 10:19, Andrey Ryabinin a écrit :
On 2/27/19 11:25 AM, Christophe Leroy wrote:
> With
On Thu, Feb 28, 2019 at 7:35 PM Aneesh Kumar K.V
wrote:
>
> Add a flag to indicate the ability to do huge page dax mapping. On
> architecture
> like ppc64, the hypervisor can disable huge page support in the guest. In
> such a case, we should not enable huge page dax mapping. This patch adds
> a
On Thu 28-02-19 14:05:22, Aneesh Kumar K.V wrote:
> Add a flag to indicate the ability to do huge page dax mapping. On
> architecture
> like ppc64, the hypervisor can disable huge page support in the guest. In
> such a case, we should not enable huge page dax mapping. This patch adds
> a flag
On Thu, Feb 28, 2019 at 10:22 AM Andrey Ryabinin
wrote:
>
>
>
> On 2/27/19 4:11 PM, Christophe Leroy wrote:
> >
> >
> > Le 27/02/2019 à 10:19, Andrey Ryabinin a écrit :
> >>
> >>
> >> On 2/27/19 11:25 AM, Christophe Leroy wrote:
> >>> With version v8 of the series implementing KASAN on 32 bits
On 2/27/19 4:11 PM, Christophe Leroy wrote:
>
>
> Le 27/02/2019 à 10:19, Andrey Ryabinin a écrit :
>>
>>
>> On 2/27/19 11:25 AM, Christophe Leroy wrote:
>>> With version v8 of the series implementing KASAN on 32 bits powerpc
>>>
On Wed, 2019-02-27 at 03:02:29 UTC, Jordan Niethe wrote:
> Currently the opal log is globally readable. It is kernel policy to limit
> the visibility of physical addresses / kernel pointers to root.
> Given this and the fact the opal log may contain this information it would
> be better to limit
On Tue, 2019-02-26 at 09:30:35 UTC, Nicholas Piggin wrote:
> The OPAL call wrapper gets interrupt disabling wrong. It disables
> interrupts just by clearing MSR[EE], which has two problems:
>
> - It doesn't call into the IRQ tracing subsystem, which means tracing
> across OPAL calls does not
On Tue, 2019-02-26 at 08:51:07 UTC, Nicholas Piggin wrote:
> HV interrupts that use HSRR registers do not enter with MSR[RI] clear,
> but their entry code is not recoverable vs NMI, due to shared use of
> HSPRG1 as a scratch register to save r13.
>
> This means that a system reset or machine
On Tue, 2019-02-26 at 05:38:55 UTC, Nathan Chancellor wrote:
> When building with -Wsometimes-uninitialized, Clang warns:
>
> arch/powerpc/xmon/ppc-dis.c:157:7: warning: variable 'opcode' is used
> uninitialized whenever 'if' condition is false
> [-Wsometimes-uninitialized]
> if
On Thu 28-02-19 14:05:21, Aneesh Kumar K.V wrote:
> Architectures like ppc64 use the deposited page table to store hardware
> page table slot information. Make sure we deposit a page table when
> using zero page at the pmd level for hash.
>
> Without this we hit
>
> Unable to handle kernel
On Tue, 2019-02-26 at 04:39:34 UTC, "Aneesh Kumar K.V" wrote:
> After we ALIGN up the address we need to make sure we didn't overflow
> and resulted in zero address. In that case, we need to make sure that
> the returned address is greater than mmap_min_addr.
>
> This fixes selftest
On Fri, 2019-02-22 at 06:53:27 UTC, Sandipan Das wrote:
> This adds emulation support for the following integer instructions:
> * Multiply-Add High Doubleword (maddhd)
> * Multiply-Add High Doubleword Unsigned (maddhdu)
> * Multiply-Add Low Doubleword (maddld)
>
> As suggested by Michael,
On Wed, 2019-02-13 at 03:38:18 UTC, Alexey Kardashevskiy wrote:
> We store 2 multilevel tables in iommu_table - one for the hardware and
> one with the corresponding userspace addresses. Before allocating
> the tables, the iommu_table_group_ops::get_table_size() hook returns
> the combined size of
This code is dead. Just remove it.
Signed-off-by: Jason Yan
---
arch/powerpc/kernel/head_fsl_booke.S | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/powerpc/kernel/head_fsl_booke.S
b/arch/powerpc/kernel/head_fsl_booke.S
index 2386ce2a9c6e..b8450f017d85 100644
---
Add a flag to indicate the ability to do huge page dax mapping. On architecture
like ppc64, the hypervisor can disable huge page support in the guest. In
such a case, we should not enable huge page dax mapping. This patch adds
a flag which the architecture code will update to indicate huge page
Architectures like ppc64 use the deposited page table to store hardware
page table slot information. Make sure we deposit a page table when
using zero page at the pmd level for hash.
Without this we hit
Unable to handle kernel paging request for data at address 0x
Faulting instruction
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