Christophe Leroy writes:
> In arch/powerpc/mm/highmem.c, BUG_ON() is called only when
> CONFIG_DEBUG_HIGHMEM is selected, this means the BUG_ON() is
> not vital and can be replaced by a a WARN_ON
>
> At the sametime, use IS_ENABLED() instead of #ifdef to clean a bit.
>
> Signed-off-by: Christophe
Catalin Marinas writes:
> On Thu, Mar 21, 2019 at 12:15:46AM +1100, Michael Ellerman wrote:
>> Catalin Marinas writes:
>> > On Wed, Mar 13, 2019 at 10:57:17AM -0400, Qian Cai wrote:
>> >> @@ -1531,7 +1547,14 @@ static void kmemleak_scan(void)
>> >>
>> >> /* data/bss scanning */
>> >>
On 21/03/2019 05:39, Fabiano Rosas wrote:
> When calling the KVM_SET_GUEST_DEBUG ioctl, userspace might request
> the next instruction to be single stepped via the
> KVM_GUESTDBG_SINGLESTEP control bit of the kvm_guest_debug structure.
>
> We currently don't have support for guest single
Tyrel,
> For each ibmvscsi host created during a probe or destroyed during a
> remove we either add or remove that host to/from the global
> ibmvscsi_head list. This runs the risk of concurrent modification.
>
> This patch adds a simple spinlock around the list modification calls
> to prevent
When I updated the spectre_v2 reporting to handle software count cache
flush I got the logic wrong when there's no software count cache
enabled at all.
The result is that on systems with the software count cache flush
disabled we print:
Mitigation: Indirect branch cache disabled, Software
On Wed, 20 Mar 2019 16:23:28 -0700 Daniel Walker wrote:
> On Wed, Mar 20, 2019 at 03:53:19PM -0700, Andrew Morton wrote:
> > On Tue, 19 Mar 2019 16:24:45 -0700 Daniel Walker wrote:
> >
> > > This code allows architectures to use a generic builtin command line.
> >
> > I wasn't cc'ed on [2/4].
On Wed, Mar 20, 2019 at 8:09 PM Oliver wrote:
>
> On Thu, Mar 21, 2019 at 7:57 AM Dan Williams wrote:
> >
> > On Wed, Mar 20, 2019 at 8:34 AM Dan Williams
> > wrote:
> > >
> > > On Wed, Mar 20, 2019 at 1:09 AM Aneesh Kumar K.V
> > > wrote:
> > > >
> > > > Aneesh Kumar K.V writes:
> > > >
> >
On Thu, Mar 21, 2019 at 7:57 AM Dan Williams wrote:
>
> On Wed, Mar 20, 2019 at 8:34 AM Dan Williams wrote:
> >
> > On Wed, Mar 20, 2019 at 1:09 AM Aneesh Kumar K.V
> > wrote:
> > >
> > > Aneesh Kumar K.V writes:
> > >
> > > > Dan Williams writes:
> > > >
> > > >>
> > > >>> Now what will be
On Sun, Mar 17, 2019 at 7:30 PM Dmitry V. Levin wrote:
>
> This argument is required to extend the generic ptrace API with
> PTRACE_GET_SYSCALL_INFO request: syscall_get_arch() is going
> to be called from ptrace_request() along with syscall_get_nr(),
> syscall_get_arguments(),
Tyrel,
> The event pool used for queueing commands is destroyed fairly early in
> the ibmvscsi_remove() code path. Since, this happens prior to the call
> so scsi_remove_host() it is possible for further calls to queuecommand
> to be processed which manifest as a panic due to a NULL pointer
>
No change to functionality. Simply make transport event messages a litle
clearer, and rework CRQ format enums such that we have separate enums
for INIT messages and XPORT events.
Signed-off-by: Tyrel Datwyler
---
drivers/scsi/ibmvscsi/ibmvfc.c | 8 +---
drivers/scsi/ibmvscsi/ibmvfc.h | 7
Status and error codes are returned in big endian from the VIOS. The
values are translated into a human readable format when logged, but
the values are also logged. This patch byte swaps those values so
that they are consistent between BE and LE platforms.
Signed-off-by: Tyrel Datwyler
---
The VIOS uses the SCSI_ERROR class to report PRLI failures. These
errors are indicated with the combination of a IBMVFC_FC_SCSI_ERROR
return status and 0x8000 error code. Add these codes to cmd_status[]
with appropriate human readable error message.
Signed-off-by: Tyrel Datwyler
---
The text of messages logged with ibmvfc_log_error() always contain
the term "failed". In the case of cancelled commands during EH they
are reported back by the VIOS using error codes. This can be
confusing to somebody looking at these log messages as to whether
a command was successfully
Segher added some workarounds for GCC 4.2 and bintuils 2.18. We now set
4.6 and 2.20 as the minimum, so they can be dropped.
This is mostly a revert of c6995fe4 ("powerpc: Fix build bug with
binutils < 2.18 and GCC < 4.2").
Signed-off-by: Joel Stanley
---
arch/powerpc/kernel/vmlinux.lds.S
On Wed, Mar 20, 2019 at 01:09:08PM -0600, Alex Williamson wrote:
> On Wed, 20 Mar 2019 15:38:24 +1100
> David Gibson wrote:
>
> > On Tue, Mar 19, 2019 at 10:36:19AM -0600, Alex Williamson wrote:
> > > On Fri, 15 Mar 2019 19:18:35 +1100
> > > Alexey Kardashevskiy wrote:
> > >
> > > > The
The event pool used for queueing commands is destroyed fairly early in
the ibmvscsi_remove() code path. Since, this happens prior to the call
so scsi_remove_host() it is possible for further calls to queuecommand
to be processed which manifest as a panic due to a NULL pointer
dereference as seen
For each ibmvscsi host created during a probe or destroyed during a
remove we either add or remove that host to/from the global ibmvscsi_head
list. This runs the risk of concurrent modification.
This patch adds a simple spinlock around the list modification calls to
prevent concurrent updates as
On Wed, Mar 20, 2019 at 03:53:19PM -0700, Andrew Morton wrote:
> On Tue, 19 Mar 2019 16:24:45 -0700 Daniel Walker wrote:
>
> > This code allows architectures to use a generic builtin command line.
>
> I wasn't cc'ed on [2/4]. No mailing lists were cc'ed on [0/4] but it
> didn't say anything
On Wed, Mar 20, 2019 at 09:37:40AM +0100, Cédric Le Goater wrote:
> These controls will be used by the H_INT_SET_QUEUE_CONFIG and
> H_INT_GET_QUEUE_CONFIG hcalls from QEMU to configure the underlying
> Event Queue in the XIVE IC. They will also be used to restore the
> configuration of the XIVE
On Tue, 19 Mar 2019 16:24:45 -0700 Daniel Walker wrote:
> This code allows architectures to use a generic builtin command line.
I wasn't cc'ed on [2/4]. No mailing lists were cc'ed on [0/4] but it
didn't say anything useful anyway ;)
I'll queue them up for testing and shall await feedback
[+cc Michael B (original author)]
On Sat, Mar 16, 2019 at 09:40:16PM +, Colin King wrote:
> From: Colin Ian King
>
> Currently variable fndit is not initialized and contains a
> garbage value, later it is set to 1 if a drc entry is found.
> Ensure fndit is not containing garbage by
On Wed, Mar 20, 2019 at 01:13:41PM -0300, Thiago Jung Bauermann wrote:
> >> Another way of looking at this issue which also explains our reluctance
> >> is that the only difference between a secure guest and a regular guest
> >> (at least regarding virtio) is that the former uses swiotlb while the
On Wed, Mar 20, 2019 at 8:34 AM Dan Williams wrote:
>
> On Wed, Mar 20, 2019 at 1:09 AM Aneesh Kumar K.V
> wrote:
> >
> > Aneesh Kumar K.V writes:
> >
> > > Dan Williams writes:
> > >
> > >>
> > >>> Now what will be page size used for mapping vmemmap?
> > >>
> > >> That's up to the
When calling the KVM_SET_GUEST_DEBUG ioctl, userspace might request
the next instruction to be single stepped via the
KVM_GUESTDBG_SINGLESTEP control bit of the kvm_guest_debug structure.
We currently don't have support for guest single stepping implemented
in Book3S HV.
This patch adds the
I am looking for a way to inform userspace about the lack of an
implementation in KVM HV for single stepping of instructions
(KVM_GUESTDGB_SINGLESTEP bit from SET_GUEST_DEBUG ioctl).
This will be used by QEMU to decide whether to attempt a call to the
set_guest_debug ioctl (for BookE, KVM PR) or
On Wed, 2019-03-20 at 18:16 +, Catalin Marinas wrote:
> I think I have a simpler idea. Kmemleak allows punching holes in
> allocated objects, so just turn the data/bss sections into dedicated
> kmemleak objects. This happens when kmemleak is initialised, before the
> initcalls are invoked. The
On Wed, 20 Mar 2019 15:38:24 +1100
David Gibson wrote:
> On Tue, Mar 19, 2019 at 10:36:19AM -0600, Alex Williamson wrote:
> > On Fri, 15 Mar 2019 19:18:35 +1100
> > Alexey Kardashevskiy wrote:
> >
> > > The NVIDIA V100 SXM2 GPUs are connected to the CPU via PCIe links and
> > > (on POWER9)
On Thu, Mar 21, 2019 at 12:15:46AM +1100, Michael Ellerman wrote:
> Catalin Marinas writes:
> > On Wed, Mar 13, 2019 at 10:57:17AM -0400, Qian Cai wrote:
> >> @@ -1531,7 +1547,14 @@ static void kmemleak_scan(void)
> >>
> >>/* data/bss scanning */
> >>scan_large_block(_sdata, _edata);
>
On Wed, 2019-03-20 at 16:34 +1100, Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> Use %# instead of using a literal '0x'
I do not suggest this as reasonable.
There are 10's of thousands of uses of 0x%x in the kernel
and converting them to save a byte seems unnecessary.
$ git grep -P
Hello Michael,
Sorry for the delay in responding. We had some internal discussions on
this.
Michael S. Tsirkin writes:
> On Mon, Feb 04, 2019 at 04:14:20PM -0200, Thiago Jung Bauermann wrote:
>>
>> Hello Michael,
>>
>> Michael S. Tsirkin writes:
>>
>> > On Tue, Jan 29, 2019 at 03:42:44PM
On Wed, Mar 20, 2019 at 1:09 AM Aneesh Kumar K.V
wrote:
>
> Aneesh Kumar K.V writes:
>
> > Dan Williams writes:
> >
> >>
> >>> Now what will be page size used for mapping vmemmap?
> >>
> >> That's up to the architecture's vmemmap_populate() implementation.
> >>
> >>> Architectures
> >>>
On Wed, Mar 20, 2019 at 10:41 AM Arnd Bergmann wrote:
>
> I've added your patch to my randconfig test setup and will let you
> know if I see anything noticeable. I'm currently testing clang-arm32,
> clang-arm64 and gcc-x86.
This is the only additional bug that has come up so far:
`.exit.text'
Catalin Marinas writes:
> Hi Qian,
>
> On Wed, Mar 13, 2019 at 10:57:17AM -0400, Qian Cai wrote:
>> @@ -1531,7 +1547,14 @@ static void kmemleak_scan(void)
>>
>> /* data/bss scanning */
>> scan_large_block(_sdata, _edata);
>> -scan_large_block(__bss_start, __bss_stop);
>> +
>> +
On 20/03/2019 13:47, Michael Ellerman wrote:
> Laurent Vivier writes:
>> Hi Michael,
>>
>> as it seems good now, could you pick up this patch for merging?
>
> I'll start picking up patches for next starting after rc2, so next week.
>
> If you think it's a bug fix I can put it into fixes now,
On Wed, Mar 20, 2019 at 11:19 AM Masahiro Yamada
wrote:
> On Wed, Mar 20, 2019 at 6:39 PM Arnd Bergmann wrote:
> >
> > On Wed, Mar 20, 2019 at 7:41 AM Masahiro Yamada
> > wrote:
> >
> > > It is unclear to me how to fix it.
> > > That's why I ended up with "depends on !MIPS".
> > >
> > >
> > >
Le 20/03/2019 à 13:57, Michael Ellerman a écrit :
Christophe Leroy writes:
Le 08/03/2019 à 02:16, Michael Ellerman a écrit :
From: Christophe Leroy
This patch implements a framework for Kernel Userspace Access
Protection.
Then subarches will have the possibility to provide their own
On Wed, 2019-03-13 at 13:14:38 UTC, Michael Ellerman wrote:
> Jakub Drnec reported:
> Setting the realtime clock can sometimes make the monotonic clock go
> back by over a hundred years. Decreasing the realtime clock across
> the y2k38 threshold is one reliable way to reproduce. Allegedly
On Mon, 2019-03-11 at 08:30:27 UTC, Christophe Leroy wrote:
> Not only the 603 but all 6xx need SPRN_SPRG_PGDIR to be initialised at
> startup. This patch move it from __setup_cpu_603() to start_here()
> and __secondary_start(), close to the initialisation of SPRN_THREAD.
>
> Previously, virt
Akshay Adiga writes:
> On Fri, Mar 08, 2019 at 12:16:11PM +1100, Michael Ellerman wrote:
>> In order to implement KUAP (Kernel Userspace Access Protection) on
>> Power9 we will be using the AMR, and therefore indirectly the
>> UAMOR/AMOR.
>>
>> So save/restore these regs in the idle code.
>>
Christophe Leroy writes:
> Le 08/03/2019 à 02:16, Michael Ellerman a écrit :
>> From: Christophe Leroy
>>
>> This patch implements a framework for Kernel Userspace Access
>> Protection.
>>
>> Then subarches will have the possibility to provide their own
>> implementation by providing
crypto node alias is needed by U-boot to identify the node and
perform fix-ups, like adding "fsl,sec-era" property.
Signed-off-by: Horia Geantă
---
arch/powerpc/boot/dts/fsl/b4qds.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/boot/dts/fsl/b4qds.dtsi
Mathieu Malaterre writes:
> On Tue, Mar 12, 2019 at 10:14 PM Christophe Leroy
> wrote:
>>
>>
>>
>> Le 12/03/2019 à 21:31, Mathieu Malaterre a écrit :
>> > In commit cb9e4d10c448 ("[POWERPC] Add support for 750CL Holly board")
>> > new functions were added. Since these functions can be made
Mahesh Jagannath Salgaonkar writes:
> On 3/14/19 5:13 PM, Michael Ellerman wrote:
>> On Mon, 2019-03-04 at 08:25:51 UTC, Mahesh J Salgaonkar wrote:
>>> From: Mahesh Salgaonkar
>>>
>>> The kcov instrumentation inside SLB routines causes duplicate SLB entries
>>> to be added resulting into SLB
Laurent Vivier writes:
> Hi Michael,
>
> as it seems good now, could you pick up this patch for merging?
I'll start picking up patches for next starting after rc2, so next week.
If you think it's a bug fix I can put it into fixes now, but I don't
think it's a bug fix is it?
cheers
Mark Cave-Ayland writes:
> Hi all,
>
> Whilst building the latest git master on my G4 I noticed the following shift
> overflow
> warnings in the build log for arch/powerpc/boot/addnote.c:
>
>
> arch/powerpc/boot/addnote.c: In function ‘main’:
> arch/powerpc/boot/addnote.c:75:47: warning: right
Qian Cai writes:
> On 3/19/19 5:21 AM, Christophe Leroy wrote:
>> Is there a reason for resending ? AFAICS, both are identical and still marked
>> new in patchwork:
>> https://patchwork.ozlabs.org/project/linuxppc-dev/list/?submitter=76055
>>
>
> "RESEND" because of no maintainer response for
Hi Arnd,
On Wed, Mar 20, 2019 at 6:39 PM Arnd Bergmann wrote:
>
> On Wed, Mar 20, 2019 at 7:41 AM Masahiro Yamada
> wrote:
>
> > It is unclear to me how to fix it.
> > That's why I ended up with "depends on !MIPS".
> >
> >
> > MODPOST vmlinux.o
> > arch/mips/mm/sc-mips.o: In function
__find_linux_pte() is full of if/else which is hard to
follow allthough the handling is pretty simple.
Previous patches left a { } block. This patch removes it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/pgtable.c | 98 +++
1 file changed,
__find_linux_pte() is full of if/else which is hard to
follow allthough the handling is pretty simple.
Previous patch left { } blocks. This patch removes the first one
by shifting its content to the left.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/pgtable.c | 62
__find_linux_pte() is full of if/else which is hard to
follow allthough the handling is pretty simple.
This patch flattens the function by getting rid of as much if/else
as possible. In order to ease the review, this is done in two steps.
Signed-off-by: Christophe Leroy
---
This patch defines a subarch specific SLB_ADDR_LIMIT_DEFAULT
to remove the #ifdefs around the setup of mm->context.slb_addr_limit
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/64/slice.h | 2 ++
arch/powerpc/include/asm/nohash/32/slice.h | 2 ++
This patch replaces a couple of #ifdef CONFIG_PPC_64K_PAGES
by IS_ENABLED(CONFIG_PPC_64K_PAGES) to improve code maintainability.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/slice.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/mm/slice.c
Move slice_mask_for_size() into subarch mmu.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/64/mmu.h | 22 +
arch/powerpc/include/asm/nohash/32/mmu-8xx.h | 18 ++
arch/powerpc/mm/slice.c | 36
slice_mask_for_size() only uses mm->context, so hand directly a
pointer to the context. This will help moving the function in
subarch mmu.h in the next patch by avoiding having to include
the definition of struct mm_struct
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/slice.c | 34
slice is now an improved functionnality. Drop the DEBUG stuff.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/slice.c | 62 -
1 file changed, 4 insertions(+), 58 deletions(-)
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
For PPC32 that's a noop, but gcc is smart enough ignore it.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/slice.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 99983dc4e484..f98b9e812c62 100644
---
Only 3 subarches support huge pages. So when it either 2 of them, it
is not the third one.
And mmu_has_feature() is known by all subarches so IS_ENABLED() can
be used instead of #ifdef
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/hugetlbpage.c | 12 +---
1 file changed, 5
Only book3s/64 may select default among several HPAGE_SHIFT at runtime.
8xx always defines 512K pages as default
FSL_BOOK3E always defines 4M pages as default
This patch limits HUGETLB_PAGE_SIZE_VARIABLE to book3s/64
moves the definitions in subarches files.
Signed-off-by: Christophe Leroy
---
No need to have this in asm/page.h, move it into asm/hugetlb.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/hugetlb.h | 2 ++
arch/powerpc/include/asm/page.h| 1 -
arch/powerpc/kernel/fadump.c | 1 +
arch/powerpc/mm/hash_utils_64.c| 1 +
4 files changed, 4
Introduce a subarch specific helper check_and_get_huge_psize()
to check the huge page sizes and cleanup the ifdef mess in
add_huge_page_size()
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/64/hugetlb.h | 27 +
Only nohash/32 and book3s/64 support mm slices.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/nohash/64/slice.h | 7 ---
arch/powerpc/include/asm/slice.h | 4 +---
arch/powerpc/platforms/Kconfig.cputype | 4
3 files changed, 5 insertions(+), 10 deletions(-)
get_slice_psize() can be defined regardless of CONFIG_PPC_MM_SLICES
to avoid ifdefs
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/slice.h | 4
arch/powerpc/mm/hugetlbpage.c| 4 +---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git
Three subarches support hugepages:
- fsl book3e
- book3s/64
- 8xx
This patch splits asm/hugetlb.h to reduce the #ifdef mess.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/64/hugetlb.h | 41 +++
arch/powerpc/include/asm/hugetlb.h | 89
This patchs adds a subarch helper to populate hugepd.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/64/hugetlb.h | 5 +
arch/powerpc/include/asm/nohash/32/hugetlb-8xx.h | 8
arch/powerpc/include/asm/nohash/hugetlb-book3e.h | 6 ++
gup_huge_pd() is the only user of gup_hugepte() and it is
located in the same file. This patch moves gup_huge_pd()
after gup_hugepte() and makes gup_hugepte() static.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pgtable.h | 3 ---
arch/powerpc/mm/hugetlbpage.c | 38
The only function in hugetlbpage.c which doesn't depend on
CONFIG_HUGETLB_PAGE is gup_hugepte(), and this function is
only called from gup_huge_pd() which depends on
CONFIG_HUGETLB_PAGE so all the content of hugetlbpage.c
depends on CONFIG_HUGETLB_PAGE.
This patch modifies Makefile to only
__find_linux_pte() is the only function in hugetlbpage.c
which is compiled in regardless on CONFIG_HUGETLBPAGE
This patch moves it in pgtable.c.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/hugetlbpage.c | 103 -
arch/powerpc/mm/pgtable.c |
As per Kconfig.cputype, only CONFIG_PPC_FSL_BOOK3E gets to
select SYS_SUPPORTS_HUGETLBFS so simplify accordingly.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/Makefile | 2 +-
arch/powerpc/mm/hugetlbpage-book3e.c | 47 +++-
2 files changed, 20
CONFIG_PPC_64K_PAGES cannot be selected by nohash/64
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig | 1 -
arch/powerpc/include/asm/nohash/64/pgalloc.h | 3 ---
arch/powerpc/include/asm/nohash/64/pgtable.h | 4
arch/powerpc/include/asm/nohash/64/slice.h
slice_set_user_psize() is not used anymore, drop it.
Fixes: 1753dd183036 ("powerpc/mm/slice: Simplify and optimise slice context
initialisation")
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/book3s/64/slice.h | 5 -
arch/powerpc/include/asm/nohash/64/slice.h | 1 -
2 files
No reason to BUG() in add_huge_page_size(). Just WARN and
reject the add.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/hugetlbpage.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index
The main purpose of this series is to reduce the amount of #ifdefs in
hugetlbpage.c and slice.c
At the same time, it does some cleanup by reducing the number of BUG_ON()
and dropping unused functions.
It also removes 64k pages related code in nohash/64 as 64k pages are
can only by selected on
Don't BUG(), just warn and return NULL.
If the NULL value is not handled, it will get catched anyway.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/hugetlb.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/hugetlb.h
This function is not used anymore, drop it.
Fixes: b42279f0165c ("powerpc/mm/nohash: MM_SLICE is only used by book3s 64")
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/hugetlbpage-book3e.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/arch/powerpc/mm/hugetlbpage-book3e.c
When no mask is found for the page size, WARN() and return NULL
instead of BUG()ing.
Signed-off-by: Christophe Leroy
---
arch/powerpc/mm/slice.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index
On Wed, Mar 20, 2019 at 7:21 AM Masahiro Yamada
wrote:
>
> Commit 60a3cdd06394 ("x86: add optimized inlining") introduced
> CONFIG_OPTIMIZE_INLINING, but it has been available only for x86.
>
> The idea is obviously arch-agnostic although we need some code fixups.
> This commit moves the config
On Wed, Mar 20, 2019 at 7:41 AM Masahiro Yamada
wrote:
> It is unclear to me how to fix it.
> That's why I ended up with "depends on !MIPS".
>
>
> MODPOST vmlinux.o
> arch/mips/mm/sc-mips.o: In function `mips_sc_prefetch_enable.part.2':
> sc-mips.c:(.text+0x98): undefined reference to
Some KVM devices will want to handle special mappings related to the
underlying HW. For instance, the XIVE interrupt controller of the
POWER9 processor has MMIO pages for thread interrupt management and
for interrupt source control that need to be exposed to the guest when
the OS has the required
Each source is associated with an Event State Buffer (ESB) with a
even/odd pair of pages which provides commands to manage the source:
to trigger, to EOI, to turn off the source for instance.
The custom VM fault handler will deduce the guest IRQ number from the
offset of the fault, and the ESB
The state of the thread interrupt management registers needs to be
collected for migration. These registers are cached under the
'xive_saved_state.w01' field of the VCPU when the VPCU context is
pulled from the HW thread. An OPAL call retrieves the backup of the
IPB register in the underlying XIVE
Each thread has an associated Thread Interrupt Management context
composed of a set of registers. These registers let the thread handle
priority management and interrupt acknowledgment. The most important
are :
- Interrupt Pending Buffer (IPB)
- Current Processor Priority (CPPR)
Full support for the XIVE native exploitation mode is now available,
advertise the capability KVM_CAP_PPC_IRQ_XIVE for guests running on
PowerNV KVM Hypervisors only. Support for nested guests (pseries KVM
Hypervisor) is not yet available. XIVE should also have been activated
which is default
This control will be used by the H_INT_SET_SOURCE_CONFIG hcall from
QEMU to configure the target of a source and also to restore the
configuration of a source when migrating the VM.
The XIVE source interrupt structure is extended with the value of the
Effective Interrupt Source Number. The EISN
When migration of a VM is initiated, a first copy of the RAM is
transferred to the destination before the VM is stopped, but there is
no guarantee that the EQ pages in which the event notifications are
queued have not been modified.
To make sure migration will capture a consistent memory state,
Hi Daniel,
pi 15. 3. 2019 o 3:09 Daniel Axtens napísal(a):
> The original assembly imported from OpenSSL has two copy-paste
> errors in handling CTR mode. When dealing with a 2 or 3 block tail,
> the code branches to the CBC decryption exit path, rather than to
> the CTR exit path.
>
> This
When the VM boots, the CAS negotiation process determines which
interrupt mode to use and invokes a machine reset. At that time, the
previous KVM interrupt device is 'destroyed' before the chosen one is
created. Upon destruction, the vCPU interrupt presenters using the KVM
device should be cleared
The 'destroy' method is currently used to destroy all devices when the
VM is destroyed after the vCPUs have been freed.
This new KVM ioctl exposes the same KVM device method. It acts as a
software reset of the VM to 'destroy' selected devices when necessary
and perform the required cleanups on
The KVM XICS-over-XIVE device and the proposed KVM XIVE native device
implement an IRQ space for the guest using the generic IPI interrupts
of the XIVE IC controller. These interrupts are allocated at the OPAL
level and "mapped" into the guest IRQ number space in the range 0-0x1FFF.
Interrupt
This control will be used by the H_INT_SYNC hcall from QEMU to flush
event notifications on the XIVE IC owning the source.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
Changes since v2 :
- fixed locking on source block
arch/powerpc/include/uapi/asm/kvm.h| 1 +
This control is to be used by the H_INT_RESET hcall from QEMU. Its
purpose is to clear all configuration of the sources and EQs. This is
necessary in case of a kexec (for a kdump kernel for instance) to make
sure that no remaining configuration is left from the previous boot
setup so that the new
These controls will be used by the H_INT_SET_QUEUE_CONFIG and
H_INT_GET_QUEUE_CONFIG hcalls from QEMU to configure the underlying
Event Queue in the XIVE IC. They will also be used to restore the
configuration of the XIVE EQs and to capture the internal run-time
state of the EQs. Both 'get' and
The XIVE KVM device maintains a list of interrupt sources for the VM
which are allocated in the pool of generic interrupts (IPIs) of the
main XIVE IC controller. These are used for the CPU IPIs as well as
for virtual device interrupts. The IRQ number space is defined by
QEMU.
The XIVE device
The user interface exposes a new capability KVM_CAP_PPC_IRQ_XIVE to
let QEMU connect the vCPU presenters to the XIVE KVM device if
required. The capability is not advertised for now as the full support
for the XIVE native exploitation mode is not yet available. When this
is case, the capability
This is the basic framework for the new KVM device supporting the XIVE
native exploitation mode. The user interface exposes a new KVM device
to be created by QEMU, only available when running on a L0 hypervisor.
Support for nested guests is not available yet.
The XIVE device reuses the device
The support for XIVE native exploitation mode in Linux/KVM needs a
couple more OPAL calls to get and set the state of the XIVE internal
structures being used by a sPAPR guest.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
Changes since v3:
- rebased on 5.1-rc1
Changes
Hello,
On the POWER9 processor, the XIVE interrupt controller can control
interrupt sources using MMIOs to trigger events, to EOI or to turn off
the sources. Priority management and interrupt acknowledgment is also
controlled by MMIO in the CPU presenter sub-engine.
PowerNV/baremetal Linux runs
Dan Williams writes:
>
>> Now what will be page size used for mapping vmemmap?
>
> That's up to the architecture's vmemmap_populate() implementation.
>
>> Architectures
>> possibly will use PMD_SIZE mapping if supported for vmemmap. Now a
>> device-dax with struct page in the device will have
Aneesh Kumar K.V writes:
> Dan Williams writes:
>
>>
>>> Now what will be page size used for mapping vmemmap?
>>
>> That's up to the architecture's vmemmap_populate() implementation.
>>
>>> Architectures
>>> possibly will use PMD_SIZE mapping if supported for vmemmap. Now a
>>> device-dax with
Reduce #ifdef mess by defining a helper to print
hash info at startup.
In the meantime, remove the display of hash table address
to reduce leak of non necessary information.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/setup-common.c | 19 +--
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