On Wed, Apr 10, 2019 at 07:04:38PM +0200, Cédric Le Goater wrote:
> These controls will be used by the H_INT_SET_QUEUE_CONFIG and
> H_INT_GET_QUEUE_CONFIG hcalls from QEMU to configure the underlying
> Event Queue in the XIVE IC. They will also be used to restore the
> configuration of the XIVE
On 12/04/2019 02:52, Alex Williamson wrote:
> On Thu, 11 Apr 2019 16:48:44 +1000
> Alexey Kardashevskiy wrote:
>
>> The NVIDIA V100 SXM2 GPUs are connected to the CPU via PCIe links and
>> (on POWER9) NVLinks. In addition to that, GPUs themselves have direct
>> peer-to-peer NVLinks in groups
Michael Ellerman's on April 11, 2019 12:49 am:
> On Fri, 2019-03-29 at 07:42:57 UTC, Nicholas Piggin wrote:
>> Commit 48e7b76957 ("powerpc/64s/hash: Convert SLB miss handlers to C")
>> broke the radix-mode segment exception handler. In radix mode, this is
>> exception is not an SLB miss, rather it
Align it with other architectures and none of the callers has
been interested its return
Signed-off-by: Li RongQing
---
v1->v2: change memcpy_flushcache declaration in
arch/powerpc/include/asm/string.h
arch/powerpc/include/asm/string.h | 2 +-
arch/powerpc/lib/pmem.c | 4 +---
2
Josh Poimboeuf writes:
> On Wed, Apr 10, 2019 at 02:10:01PM +0200, Thomas Gleixner wrote:
>> On Wed, 10 Apr 2019, Michael Ellerman wrote:
>> > Josh Poimboeuf writes:
>> >
>> > > On Fri, Apr 05, 2019 at 06:01:36PM +0200, Borislav Petkov wrote:
>> > >> Thinking about this more, we can shave off
Thomas Gleixner writes:
> On Wed, 10 Apr 2019, Michael Ellerman wrote:
>> Josh Poimboeuf writes:
>>
>> > On Fri, Apr 05, 2019 at 06:01:36PM +0200, Borislav Petkov wrote:
>> >> Thinking about this more, we can shave off the first 4 chars and have it
>> >> be:
>> >>
>> >> spec_mitigations=
>> >>
Sasha Levin writes:
> On Thu, Apr 11, 2019 at 09:45:55PM +1000, Michael Ellerman wrote:
>>-BEGIN PGP SIGNED MESSAGE-
>>Hash: SHA1
>>
>>Hi Greg,
>>
>>Please queue up these powerpc patches for 4.9 if you have no objections.
>>
>>There's one build fix for newer toolchains, and the rest are
CONFIG_DEBUG_KERNEL should not impact code generation. Use the newly
defined CONFIG_DEBUG_MISC instead to keep the current code.
Signed-off-by: Sinan Kaya
---
arch/powerpc/kernel/sysfs.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/sysfs.c
> On April 11, 2019 at 8:37 AM Michael Ellerman wrote:
>
>
> Christopher M Riedl writes:
> >> On April 8, 2019 at 1:34 AM Oliver wrote:
> >> On Mon, Apr 8, 2019 at 1:06 PM Christopher M. Riedl
> >> wrote:
> ...
> >> >
> >> > diff --git a/arch/powerpc/Kconfig.debug
On 03/19/2019 07:58 PM, Sam Bobroff wrote:
> Hi all,
>
> This patch set adds support for EEH recovery of hot plugged devices on pSeries
> machines. Specifically, devices discovered by PCI rescanning using
> /sys/bus/pci/rescan, which includes devices hotplugged by QEMU's device_add
> command.
On Thu, Apr 11, 2019 at 12:08 AM Waiman Long wrote:
>
> On 04/10/2019 04:15 AM, huang ying wrote:
> > Hi, Waiman,
> >
> > What's the status of this patchset? And its merging plan?
> >
> > Best Regards,
> > Huang, Ying
>
> I have broken the patch into 3 parts (0/1/2) and rewritten some of them.
>
Em Thu, 11 Apr 2019 14:07:31 -0700
Guenter Roeck escreveu:
> On Thu, Apr 11, 2019 at 05:43:57PM -0300, Mauro Carvalho Chehab wrote:
> > Em Thu, 11 Apr 2019 12:43:24 -0600
> > Jonathan Corbet escreveu:
> >
> > > On Wed, 10 Apr 2019 16:22:37 -0300
> > > Mauro Carvalho Chehab wrote:
> > >
>
On 04/11/2019 10:47 AM, Daniel Axtens wrote:
Eric Biggers writes:
Are you still planning to fix the remaining bug? I booted a ppc64le VM, and I
see the same test failure (I think) you were referring to:
alg: skcipher: p8_aes_ctr encryption test failed (wrong result) on test vector 3,
On Thu, Apr 11, 2019 at 05:43:57PM -0300, Mauro Carvalho Chehab wrote:
> Em Thu, 11 Apr 2019 12:43:24 -0600
> Jonathan Corbet escreveu:
>
> > On Wed, 10 Apr 2019 16:22:37 -0300
> > Mauro Carvalho Chehab wrote:
> >
> > > This series converts the contents of Documentation/hwmon to ReST
> > >
Em Thu, 11 Apr 2019 12:43:24 -0600
Jonathan Corbet escreveu:
> On Wed, 10 Apr 2019 16:22:37 -0300
> Mauro Carvalho Chehab wrote:
>
> > This series converts the contents of Documentation/hwmon to ReST
> > format.
> >
> > PS.: I opted to group the conversion files per groups of maintainer
> >
On Thu, Apr 11, 2019 at 10:55:43AM +0100, Mark Rutland wrote:
> On Thu, Apr 11, 2019 at 02:22:23PM +1000, Alexey Kardashevskiy wrote:
> > On 03/04/2019 07:41, Daniel Jordan wrote:
>
> > > - dev_dbg(dev, "[%d] RLIMIT_MEMLOCK %c%ld %ld/%ld%s\n", current->pid,
> > > + dev_dbg(dev, "[%d]
On Wed, Apr 10, 2019 at 11:06:39AM +, Viorel Suman wrote:
> There should be no trouble to understand dev = pdev->dev.
> This can save some space to have more print info or save
> some wrapped lines.
Change looks fine. Ack.
> Signed-off-by: Viorel Suman
> Suggested-by: Nicolin Chen
I think
On Thu, Apr 11, 2019 at 09:39:09AM +, S.j. Wang wrote:
> Unify the supported input and output rate, add the
We previously didn't support 5KHz->5KHz, but now we do? That'd be
great if so.
> static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
> @@ -626,14 +629,18 @@ static
On Thu, Apr 11, 2019 at 09:39:06AM +, S.j. Wang wrote:
> +/*
> + * Select the pre-processing and post-processing options
By aligning with other function comments:
/**
* Select the pre-processing and post-processing options
> + *
> + * Fsin: input sample rate
> + * Fsout: output sample
On Wed, 10 Apr 2019 16:22:37 -0300
Mauro Carvalho Chehab wrote:
> This series converts the contents of Documentation/hwmon to ReST
> format.
>
> PS.: I opted to group the conversion files per groups of maintainer
> set, as, if I were to generate one patch per file, it would give around
> 160
On Thu, 11 Apr 2019 16:48:44 +1000
Alexey Kardashevskiy wrote:
> The NVIDIA V100 SXM2 GPUs are connected to the CPU via PCIe links and
> (on POWER9) NVLinks. In addition to that, GPUs themselves have direct
> peer-to-peer NVLinks in groups of 2 to 4 GPUs with no buffers/latches
> between GPUs.
>
On 06/03/2019 12:12, Patrick Havelange wrote:
> Common #defines have been moved to "linux/fsl/ftm.h". Thus making use of
> this file.
> Also FTM_SC_CLK_SHIFT has been renamed to FTM_SC_CLK_MASK_SHIFT.
>
> Signed-off-by: Patrick Havelange
> Reviewed-by: Esben Haabendal
Acked-by: Daniel Lezcano
On Thu, Apr 11, 2019 at 09:45:55PM +1000, Michael Ellerman wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi Greg,
Please queue up these powerpc patches for 4.9 if you have no objections.
There's one build fix for newer toolchains, and the rest are spectre related.
I've queued it up,
Eric Biggers writes:
> Hi Daniel,
>
> On Fri, Mar 15, 2019 at 04:23:02PM +1100, Daniel Axtens wrote:
>> Eric Biggers writes:
>>
>> > Hi Daniel,
>> >
>> > On Fri, Mar 15, 2019 at 03:24:35PM +1100, Daniel Axtens wrote:
>> >> Hi Eric,
>> >>
>> >> >> The original assembly imported from OpenSSL
On Wed, Apr 10, 2019 at 02:10:01PM +0200, Thomas Gleixner wrote:
> On Wed, 10 Apr 2019, Michael Ellerman wrote:
> > Josh Poimboeuf writes:
> >
> > > On Fri, Apr 05, 2019 at 06:01:36PM +0200, Borislav Petkov wrote:
> > >> Thinking about this more, we can shave off the first 4 chars and have it
>
On Thu, Apr 11, 2019 at 05:27:31AM -0700, Joe Perches wrote:
> On Thu, 2019-04-11 at 22:07 +1000, Michael Ellerman wrote:
> > Joe Perches writes:
> > > On Thu, 2019-04-11 at 06:27 +0200, Lukas Bulwahn wrote:
> > > > Paul McKenney attempted to update all email addresses
> > > >
On Wed, Apr 10, 2019 at 04:22:58PM -0300, Mauro Carvalho Chehab wrote:
> Now that all files were converted to ReST format, rename them
> and add an index.
>
> Signed-off-by: Mauro Carvalho Chehab
> ---
> .../devicetree/bindings/hwmon/g762.txt| 2 +-
> Documentation/hwmon/{ab8500 =>
On 11/04/2019 08:07, Florian Weimer wrote:
> * Adhemerval Zanella:
>
>> This allows us to adjust the baud rates to non-standard values using termios
>> interfaces without to resorting to add new headers and use a different API
>> (ioctl).
>
> How much symbol versioning will be required for
Christopher M Riedl writes:
>> On April 8, 2019 at 1:34 AM Oliver wrote:
>> On Mon, Apr 8, 2019 at 1:06 PM Christopher M. Riedl
>> wrote:
...
>> >
>> > diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
>> > index 4e00cb0a5464..0c7f21476018 100644
>> > ---
On Thu, 2019-04-11 at 22:07 +1000, Michael Ellerman wrote:
> Joe Perches writes:
> > On Thu, 2019-04-11 at 06:27 +0200, Lukas Bulwahn wrote:
> > > Paul McKenney attempted to update all email addresses @linux.vnet.ibm.com
> > > to @linux.ibm.com in commit 1dfddcdb95c4
> > > ("MAINTAINERS: Update
Joe Perches writes:
> On Thu, 2019-04-11 at 06:27 +0200, Lukas Bulwahn wrote:
>> Paul McKenney attempted to update all email addresses @linux.vnet.ibm.com
>> to @linux.ibm.com in commit 1dfddcdb95c4
>> ("MAINTAINERS: Update from @linux.vnet.ibm.com to @linux.ibm.com"), but
>> some still remained.
On 4/11/19 12:27 PM, Paul Mackerras wrote:
> On Wed, Apr 10, 2019 at 07:04:48PM +0200, Cédric Le Goater wrote:
>> When a P9 sPAPR VM boots, the CAS negotiation process determines which
>> interrupt mode to use (XICS legacy or XIVE native) and invokes a
>> machine reset to activate the chosen mode.
commit 92edf8df0ff2ae86cc632eeca0e651fd8431d40d upstream.
When I updated the spectre_v2 reporting to handle software count cache
flush I got the logic wrong when there's no software count cache
enabled at all.
The result is that on systems with the software count cache flush
disabled we print:
From: Christophe Leroy
commit 27da80719ef132cf8c80eb406d5aeb37dddf78cc upstream.
The commit identified below adds MC_BTB_FLUSH macro only when
CONFIG_PPC_FSL_BOOK3E is defined. This results in the following error
on some configs (seen several times with kisskb randconfig_defconfig)
From: Diana Craciun
commit 039daac5526932ec731e4499613018d263af8b3e upstream.
Fixed the following build warning:
powerpc-linux-gnu-ld: warning: orphan section `__btb_flush_fixup' from
`arch/powerpc/kernel/head_44x.o' being placed in section
`__btb_flush_fixup'.
Signed-off-by: Diana Craciun
From: Diana Craciun
commit dfa88658fb0583abb92e062c7a9cd5a5b94f2a46 upstream.
Report branch predictor state flush as a mitigation for
Spectre variant 2.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/security.c | 5 -
1 file changed, 4
From: Diana Craciun
commit 3bc8ea8603ae4c1e09aca8de229ad38b8091fcb3 upstream.
If the user choses not to use the mitigations, replace
the code sequence with nops.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/setup-common.c | 1 +
1 file changed, 1
From: Diana Craciun
commit e7aa61f47b23afbec41031bc47ca8d6cb6516abc upstream.
Switching from the guest to host is another place
where the speculative accesses can be exploited.
Flush the branch predictor when entering KVM.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
From: Diana Craciun
commit 7fef436295bf6c05effe682c8797dfcb0deb112a upstream.
In order to protect against speculation attacks on
indirect branches, the branch predictor is flushed at
kernel entry to protect for the following situations:
- userspace process attacking another userspace process
-
From: Diana Craciun
commit 10c5e83afd4a3f01712d97d3bb1ae34d5b74a185 upstream.
In order to protect against speculation attacks on
indirect branches, the branch predictor is flushed at
kernel entry to protect for the following situations:
- userspace process attacking another userspace process
-
From: Diana Craciun
commit f633a8ad636efb5d4bba1a047d4a0f1ef719aa06 upstream.
When the command line argument is present, the Spectre variant 2
mitigations are disabled.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/setup.h | 5 +
From: Diana Craciun
commit 98518c4d8728656db349f875fcbbc7c126d4c973 upstream.
In order to flush the branch predictor the guest kernel performs
writes to the BUCSR register which is hypervisor privilleged. However,
the branch predictor is flushed at each KVM entry, so the branch
predictor has
From: Diana Craciun
commit 7d8bad99ba5a22892f0cad6881289fdc3875a930 upstream.
Currently for CONFIG_PPC_FSL_BOOK3E the spectre_v2 file is incorrect:
$ cat /sys/devices/system/cpu/vulnerabilities/spectre_v2
"Mitigation: Software count cache flush"
Which is wrong. Fix it to report vulnerable
From: Diana Craciun
commit 1cbf8990d79ff69da8ad09e8a3df014e1494462b upstream.
The BUCSR register can be used to invalidate the entries in the
branch prediction mechanisms.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/ppc_asm.h | 21
From: Diana Craciun
commit 76a5eaa38b15dda92cd6964248c39b5a6f3a4e9d upstream.
In order to protect against speculation attacks (Spectre
variant 2) on NXP PowerPC platforms, the branch predictor
should be flushed when the privillege level is changed.
This patch is adding the infrastructure to
commit 99d54754d3d5f896a8f616b0b6520662bc99d66b upstream.
Look for fw-features properties to determine the appropriate settings
for the count cache flush, and then call the generic powerpc code to
set it up based on the security feature flags.
Signed-off-by: Michael Ellerman
---
commit ba72dc171954b782a79d25e0f4b3ed91090c3b1e upstream.
Use the existing hypercall to determine the appropriate settings for
the count cache flush, and then call the generic powerpc code to set
it up based on the security feature flags.
Signed-off-by: Michael Ellerman
---
commit ee13cb249fabdff8b90aaff61add347749280087 upstream.
Some CPU revisions support a mode where the count cache needs to be
flushed by software on context switch. Additionally some revisions may
have a hardware accelerated flush, in which case the software flush
sequence can be shortened.
If
commit dc8c6cce9a26a51fc19961accb978217a3ba8c75 upstream.
Add security feature flags to indicate the need for software to flush
the count cache on context switch, and for the presence of a hardware
assisted count cache flush.
Signed-off-by: Michael Ellerman
---
commit 06d0bbc6d0f56dacac3a79900e9a9a0d5972d818 upstream.
Add a macro and some helper C functions for patching single asm
instructions.
The gas macro means we can do something like:
1:nop
patch_site 1b, patch__foo
Which is less visually distracting than defining a GLOBAL symbol
From: Diana Craciun
commit c28218d4abbf4f2035495334d8bfcba64bda4787 upstream.
Used barrier_nospec to sanitize the syscall table.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/entry_32.S | 10 ++
1 file changed, 10 insertions(+)
diff --git
From: Diana Craciun
commit ebcd1bfc33c7a90df941df68a6e5d4018c022fba upstream.
Implement the barrier_nospec as a isync;sync instruction sequence.
The implementation uses the infrastructure built for BOOK3S 64.
Signed-off-by: Diana Craciun
[mpe: Split out of larger patch]
Signed-off-by: Michael
From: Diana Craciun
commit 406d2b6ae3420f5bb2b3db6986dc6f0b6dbb637b upstream.
In a subsequent patch we will enable building security.c for Book3E.
However the NXP platforms are not vulnerable to Meltdown, so make the
Meltdown vulnerability reporting PPC_BOOK3S_64 specific.
Signed-off-by: Diana
commit af375eefbfb27cbb5b831984e66d724a40d26b5c upstream.
Currently we require platform code to call setup_barrier_nospec(). But
if we add an empty definition for the !CONFIG_PPC_BARRIER_NOSPEC case
then we can call it in setup_arch().
Signed-off-by: Diana Craciun
Signed-off-by: Michael
commit 179ab1cbf883575c3a585bcfc0f2160f1d22a149 upstream.
Add a config symbol to encode which platforms support the
barrier_nospec speculation barrier. Currently this is just Book3S 64
but we will add Book3E in a future patch.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
From: Diana Craciun
commit cf175dc315f90185128fb061dc05b6fbb211aa2f upstream.
The speculation barrier can be disabled from the command line
with the parameter: "nospectre_v1".
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/security.c | 12 +++-
From: Diana Craciun
commit 6453b532f2c8856a80381e6b9a1f5ea2f12294df upstream.
NXP Book3E platforms are not vulnerable to speculative store
bypass, so make the mitigations PPC_BOOK3S_64 specific.
Signed-off-by: Diana Craciun
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/security.c
commit 6d44acae1937b81cf8115ada8958e04f601f3f2e upstream.
When I added the spectre_v2 information in sysfs, I included the
availability of the ori31 speculation barrier.
Although the ori31 barrier can be used to mitigate v2, it's primarily
intended as a spectre v1 mitigation. Spectre v2 is
From: Michal Suchanek
commit a377514519b9a20fa1ea9adddbb4129573129cef upstream.
We now have barrier_nospec as mitigation so print it in
cpu_show_spectre_v1() when enabled.
Signed-off-by: Michal Suchanek
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/security.c | 3 +++
1 file
commit 51973a815c6b46d7b23b68d6af371ad1c9d503ca upstream.
Our syscall entry is done in assembly so patch in an explicit
barrier_nospec.
Based on a patch by Michal Suchanek.
Signed-off-by: Michal Suchanek
Signed-off-by: Michael Ellerman
---
arch/powerpc/kernel/entry_64.S | 10 ++
1
commit ddf35cf3764b5a182b178105f57515b42e2634f8 upstream.
Based on the x86 commit doing the same.
See commit 304ec1b05031 ("x86/uaccess: Use __uaccess_begin_nospec()
and uaccess_try_nospec") and b3bbfb3fb5d2 ("x86: Introduce
__uaccess_begin_nospec() and uaccess_try_nospec") for more detail.
In
From: Michal Suchanek
commit cb3d6759a93c6d0aea1c10deb6d00e111c29c19c upstream.
Check what firmware told us and enable/disable the barrier_nospec as
appropriate.
We err on the side of enabling the barrier, as it's no-op on older
systems, see the comment for more detail.
Signed-off-by: Michael
From: Michael Neuling
commit 51c3c62b58b357e8d35e4cc32f7b4ec907426fe3 upstream.
This stops us from doing code patching in init sections after they've
been freed.
In this chain:
kvm_guest_init() ->
kvm_use_magic_page() ->
fault_in_pages_readable() ->
__get_user() ->
From: Michal Suchanek
commit 815069ca57c142eb71d27439bc27f41a433a67b3 upstream.
Note that unlike RFI which is patched only in kernel the nospec state
reflects settings at the time the module was loaded.
Iterating all modules and re-patching every time the settings change
is not implemented.
From: Michal Suchanek
commit 2eea7f067f495e33b8b116b35b5988ab2b8aec55 upstream.
Based on the RFI patching. This is required to be able to disable the
speculation barrier.
Only one barrier type is supported and it does nothing when the
firmware does not enable it. Also re-patching modules is
From: Michal Suchanek
commit a6b3964ad71a61bb7c61d80a60bea7d42187b2eb upstream.
A no-op form of ori (or immediate of 0 into r31 and the result stored
in r31) has been re-tasked as a speculation barrier. The instruction
only acts as a barrier on newer machines with appropriate firmware
support.
From: Andreas Schwab
commit 8a583c0a8d316d8ea52ea78491174ab1a3e9ef9d upstream.
binutils >= 2.26 now warns about misuse of register expressions in
assembler operands that are actually literals, for example:
arch/powerpc/kernel/entry_64.S:535: Warning: invalid register expression
In practice
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hi Greg,
Please queue up these powerpc patches for 4.9 if you have no objections.
There's one build fix for newer toolchains, and the rest are spectre related.
cheers
Andreas Schwab (1):
powerpc: Fix invalid use of register expressions
On Thu, 2019-04-11 at 06:27 +0200, Lukas Bulwahn wrote:
> Paul McKenney attempted to update all email addresses @linux.vnet.ibm.com
> to @linux.ibm.com in commit 1dfddcdb95c4
> ("MAINTAINERS: Update from @linux.vnet.ibm.com to @linux.ibm.com"), but
> some still remained.
>
> We update the
On Thu, Apr 11, 2019 at 06:27:52AM +0200, Lukas Bulwahn wrote:
> Paul McKenney attempted to update all email addresses @linux.vnet.ibm.com
> to @linux.ibm.com in commit 1dfddcdb95c4
> ("MAINTAINERS: Update from @linux.vnet.ibm.com to @linux.ibm.com"), but
> some still remained.
>
> We update the
Hi Shengjiu,
Mostly looking good. See few comments inline:
> +/*
> + * Select the pre-processing and post-processing options
> + *
> + * Fsin: input sample rate
> + * Fsout: output sample rate
> + * pre_proc: return value for pre-processing option
> + * post_proc: return value for
* Adhemerval Zanella:
> This allows us to adjust the baud rates to non-standard values using termios
> interfaces without to resorting to add new headers and use a different API
> (ioctl).
How much symbol versioning will be required for this change?
> As Peter Anvin has indicated, he create a
On Tue, 9 Apr 2019 at 22:45, Michael Ellerman wrote:
>
> This can be helpful for debugging problems with the security feature
> flags, especially on guests where the flags come from the hypervisor
> via an hcall and so can't be observed in the device tree.
>
> Signed-off-by: Michael Ellerman
On Wed, Apr 10, 2019 at 07:04:48PM +0200, Cédric Le Goater wrote:
> When a P9 sPAPR VM boots, the CAS negotiation process determines which
> interrupt mode to use (XICS legacy or XIVE native) and invokes a
> machine reset to activate the chosen mode.
>
> To be able to switch from one mode to
On Thu, Apr 11, 2019 at 02:22:23PM +1000, Alexey Kardashevskiy wrote:
> On 03/04/2019 07:41, Daniel Jordan wrote:
> > - dev_dbg(dev, "[%d] RLIMIT_MEMLOCK %c%ld %ld/%ld%s\n", current->pid,
> > + dev_dbg(dev, "[%d] RLIMIT_MEMLOCK %c%ld %lld/%lu%s\n", current->pid,
> > incr ? '+' :
Unify the supported input and output rate, add the
12kHz/24kHz/128kHz to the support list
Signed-off-by: Shengjiu Wang
---
sound/soc/fsl/fsl_asrc.c | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/sound/soc/fsl/fsl_asrc.c
When we want to support more sample rate, for example 12kHz/24kHz
we need update the process_option table, if we want to support more
sample rate next time, the table need to be updated again. which
is not flexible.
We got a function fsl_asrc_sel_proc to replace the table, which can
give the
Support more sample rate in asrc
Shengjiu Wang (2):
ASoC: fsl_asrc: replace the process_option table with function
ASoC: fsl_asrc: Unify the supported input and output rate
Changes in v2
- add more comments in code
- add commit "Unify the supported input and output rate"
case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be
independent of each other, so replace fall-through with break.
Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
Signed-off-by: Shengjiu Wang
Acked-by: Nicolin Chen
Cc:
---
Changes in v5
- remove new line after Fixes
Align it with other architectures and none of the callers has
been interested its return
Signed-off-by: Li RongQing
---
arch/powerpc/lib/pmem.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc/lib/pmem.c
index
Hi Rob and Mark,
I am upgrading the kernel on a Freescale P2040 based system and have
struck an issue with LIODNs not being updated by uboot for an FMAN
ethernet port.
My system has an old uboot running which fails in its attempt to update
the fman rx port node with the required LIODN entry.
The NVIDIA V100 SXM2 GPUs are connected to the CPU via PCIe links and
(on POWER9) NVLinks. In addition to that, GPUs themselves have direct
peer-to-peer NVLinks in groups of 2 to 4 GPUs with no buffers/latches
between GPUs.
Because of these interconnected NVLinks, the POWERNV platform puts such
Hi Shengjiu,
On Thu, Apr 11, 2019 at 6:06 AM S.j. Wang wrote:
>
> case ESAI_HCKT_EXTAL and case ESAI_HCKR_EXTAL should be
> independent of each other, so replace fall-through with break.
>
> Fixes: 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
>
Since it is obvious that you will need
On 4/11/19 6:38 AM, David Gibson wrote:
> On Thu, Apr 11, 2019 at 01:16:25PM +1000, Paul Mackerras wrote:
>> On Wed, Apr 10, 2019 at 07:04:48PM +0200, Cédric Le Goater wrote:
>>> When a P9 sPAPR VM boots, the CAS negotiation process determines which
>>> interrupt mode to use (XICS legacy or XIVE
84 matches
Mail list logo
