Sachin Sant writes:
>> On 16-Nov-2019, at 12:25 AM, Aneesh Kumar K.V
>> wrote:
>>
>> On 11/15/19 11:36 AM, Sachin Sant wrote:
>>> Following Oops is seen on latest (commit 3b4852888d) powerpc merge branch
>>> code while running ndctl (test_namespace) tests
>>> 85c5b0984e was good.
>>
>>
>>
>
Le 29/11/2019 à 08:04, Lexi Shao a écrit :
CONFIG_RELOCATABLE and CONFIG_KASAN cannot be enabled at the same time
on ppce500 fsl_booke. All functions called before kasan_early_init()
should be disabled with kasan check. When CONFIG_RELOCATABLE is enabled
on ppce500 fsl_booke, relocate_init() i
The LS1028A SoC uses the same interrupt line for adjacent SAIs. Use
IRQF_SHARED to be able to use these SAIs simultaneously.
Signed-off-by: Michael Walle
---
sound/soc/fsl/fsl_sai.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_
From: Randy Dunlap
Indent a Kconfig continuation line to improve readability.
Signed-off-by: Randy Dunlap
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Michael Ellerman
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
-
Add documentation for TCR_EL1.T1SZ variable being added to
vmcoreinfo.
It indicates the size offset of the memory region addressed by TTBR1_EL1
and hence can be used for determining the vabits_actual value.
Cc: James Morse
Cc: Mark Rutland
Cc: Will Deacon
Cc: Steve Capper
Cc: Catalin Marinas
Add documentation for 'MAX_PHYSMEM_BITS' variable being added to
vmcoreinfo.
'MAX_PHYSMEM_BITS' defines the maximum supported physical address
space memory.
Cc: Boris Petkov
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: James Morse
Cc: Will Deacon
Cc: Michael Ellerman
Cc: Paul Mackerras
Cc: Benj
Fix a simple typo in arm64/memory.rst
Cc: Jonathan Corbet
Cc: James Morse
Cc: Mark Rutland
Cc: Will Deacon
Cc: Steve Capper
Cc: Catalin Marinas
Cc: Ard Biesheuvel
Cc: linux-...@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Signed-off-by: Bhupesh S
vabits_actual variable on arm64 indicates the actual VA space size,
and allows a single binary to support both 48-bit and 52-bit VA
spaces.
If the ARMv8.2-LVA optional feature is present, and we are running
with a 64KB page size; then it is possible to use 52-bits of address
space for both userspa
Right now user-space tools like 'makedumpfile' and 'crash' need to rely
on a best-guess method of determining value of 'MAX_PHYSMEM_BITS'
supported by underlying kernel.
This value is used in user-space code to calculate the bit-space
required to store a section for SPARESMEM (similar to the exist
Changes since v4:
- v4 can be seen here:
http://lists.infradead.org/pipermail/kexec/2019-November/023961.html
- Addressed comments from Dave and added patches for documenting
new variables appended to vmcoreinfo documentation.
- Added testing report shared by Akashi for PATCH 2
Hello Rasmus,
I have seen a lot of fsl soc patches from you.
Could you please post what you have modified? Did you test your patches on FSL
SoC machines?
Thanks,
Christian
Sent from my iPhone
> On 28. Nov 2019, at 16:00, linuxppc-dev-requ...@lists.ozlabs.org wrote:
>
> Send Linuxppc-dev mail
On Wed, 2019-11-27 at 17:40 +0100, Paolo Bonzini wrote:
> > diff --git a/arch/powerpc/kvm/book3s_64_vio.c
> > b/arch/powerpc/kvm/book3s_64_vio.c
> > index 5834db0a54c6..a402ead833b6 100644
> > --- a/arch/powerpc/kvm/book3s_64_vio.c
> > +++ b/arch/powerpc/kvm/book3s_64_vio.c
> > @@ -316,14 +316,13
On Thu, 2019-11-28 at 09:57 +1100, Paul Mackerras wrote:
> There isn't a potential use-after-free here. We are relying on the
> property that the release function (kvm_vm_release) cannot be called
> in parallel with this function. The reason is that this function
> (kvm_vm_ioctl_create_spapr_tce)
Currently, QUICC_ENGINE depends on PPC32, so this in itself does not
change anything. In order to allow removing the PPC32 dependency from
QUICC_ENGINE and avoid allmodconfig build failures, add this explicit
dependency.
Also, the QE Ethernet has never been integrated on any non-PowerPC SoC
and mo
There are also PPC64, ARM and ARM64 based SOCs with a QUICC Engine,
and the core QE code as well as net/wan/fsl_ucc_hdlc and
tty/serial/ucc_uart has now been modified to not rely on ppcisms.
So extend the architectures that can select QUICC_ENGINE, and add the
rather modest requirements of OF && H
Qiang Zhao points out that these offsets get written to 16-bit
registers, and there are some QE platforms with more than 64K
muram. So it is possible that qe_muram_alloc() gives us an allocation
that can't actually be used by the hardware, so detect and reject
that.
Reported-by: Qiang Zhao
Review
When allowing this driver to be built for ARM, the build fails (for
CONFIG_SMP=y) since ARM's asm/irq.h header is not self-contained:
In file included from drivers/soc/fsl/qe/ucc.c:18:0:
>> arch/arm/include/asm/irq.h:34:50: error: unknown type name 'cpumask_t'
extern void arch_trigger_cpumas
When building this on a 64-bit platform gcc rightly warns that the
error checking is broken (-ENOMEM stored in an u32 does not compare
greater than (unsigned long)-MAX_ERRNO). Instead, now that
qe_muram_alloc() returns s32, use that type to store the return value
and use standard kernel style "ret
When releasing the allocated muram resource, we rely on reading back
the offsets from the riptr/tiptr registers. But those registers are
__be16 (and we indeed write them using iowrite16be), so we can't just
read them back with a normal C dereference.
This is not currently a real problem, since for
When building this on a 64-bit platform gcc rightly warns that the
error checking is broken (-ENOMEM stored in an u32 does not compare
greater than (unsigned long)-MAX_ERRNO). Instead, change the
ucc_fast_[tr]x_virtual_fifo_base_offset members to s32 and use an
ordinary check-for-negative. Also, th
The sdma member of struct qe_immap is not at offset zero, so even if
qe_immr wasn't initialized yet (i.e. NULL), &qe_immr->sdma would not
be NULL.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/so
Now that qe_muram_alloc() returns s32, adapt qe_sdma_init() and avoid
another few IS_ERR_VALUE() uses.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/
When trying to build this for a 64-bit platform, one gets warnings
from using IS_ERR_VALUE on something which is not sizeof(long).
Instead, change the various *_offset fields to store a signed integer,
and simply check for a negative return from qe_muram_alloc(). Since
qe_muram_free() now accepts
If the kmalloc() fails, we try to undo the gen_pool allocation we've
just done. Unfortunately, start has already been modified to subtract
the GENPOOL_OFFSET bias, so we're freeing something that very likely
doesn't exist in the gen_pool, meaning we hit the
kernel BUG at lib/genalloc.c:399!
Inte
cpm_muram_alloc_common() tries to support a kind of lazy
initialization - if the muram_pool has not been created yet, it calls
cpm_muram_init(). Now, cpm_muram_alloc_common() is always called under
spin_lock_irqsave(&cpm_muram_lock, flags);
and cpm_muram_init() does gen_pool_create() (whi
This allows one to simplify callers since they can store a negative
value as a sentinel to indicate "this was never allocated" (or store
the -ENOMEM from an allocation failure) and then call cpm_muram_free()
unconditionally.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/so
Nobody uses the return value from cpm_muram_free, and functions that
free resources usually return void. One could imagine a use for a "how
much have I allocated" a la ksize(), but knowing how much one had
access to after the fact is useless.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoe
There are a number of problems with cpm_muram_alloc() and its
callers. Most callers assign the return value to some variable and
then use IS_ERR_VALUE to check for allocation failure. However, when
that variable is not sizeof(long), this leads to warnings - and it is
indeed broken to do e.g.
u32
The buf member of struct qe_bd is a __be32, so to make this work on
little-endian hosts, use be32_to_cpu when reading it.
Reviewed-by: Timur Tabi
Acked-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/tty/serial/ucc_uart.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
According to Timur Tabi
This bug in older U-Boots is definitely PowerPC-specific
So before allowing this driver to be built for platforms other than
PPC32, make sure that we don't accept malformed device trees on those
other platforms.
Suggested-by: Timur Tabi
Reviewed-by: Timur Tabi
Acked
For this to work correctly on little-endian hosts, don't access the
device-tree properties directly in native endianness, but use the
of_property_read_u32() helper.
Reviewed-by: Timur Tabi
Acked-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/tty/serial/ucc_uart.c | 36 +
The Soft UART hack is only needed for some PPC-based SOCs. To allow
building this driver for non-PPC, guard soft_uart_init() and its
helpers by CONFIG_PPC32, and use a no-op soft_uart_init() otherwise.
Reviewed-by: Timur Tabi
Acked-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/tty
The "soft uart" mechanism is a workaround for a silicon bug which (as
far as I know) only affects some PPC-based SOCs.
The code that determines which microcode blob to request relies on
some powerpc-specific bits (e.g. the mfspr(SPRN_SVR) and hence also
the asm/reg.h header). This makes it a littl
Some ARM-based SOCs (e.g. LS1021A) also have a QUICC engine. As
preparation for allowing this driver to build on ARM, replace the
ppc-specific in_be16() etc. by the qe_io* helpers. Done via
coccinelle.
Reviewed-by: Timur Tabi
Acked-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/tty
This driver uses #defines from soc/fsl/cpm.h, so instead of relying on
some other header pulling that in, do that explicitly. This is
preparation for allowing this driver to build on ARM.
Reviewed-by: Timur Tabi
Acked-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/tty/serial/ucc_ua
asm/cpm.h under arch/powerpc is now just a wrapper for including
soc/fsl/cpm.h. In order to make the qe.h header usable on other
architectures, use the latter path directly.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
include/soc/fsl/qe/qe.h | 2 +-
1 file changed, 1 insertion(+
Some drivers, e.g. ucc_uart, need definitions from cpm.h. In order to
allow building those drivers for non-ppc based SOCs, move the header
to include/soc/fsl. For now, leave a trivial wrapper at the old
location so drivers can be updated one by one.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus V
This is necessary for this to work on little-endian hosts.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_io.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index 61dd8eb8c0fe
We need to apply be32_to_cpu to make this work correctly on
little-endian hosts.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_io.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fs
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_io.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index f6b10f38b2f4..99aeb01586bd 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b
Instead of manually doing of_get_property/of_find_property and reading
the value by assigning to a u32* or u64* and dereferencing, use the
of_property_read_* functions.
This make the code more readable, and more importantly, is required
for this to work correctly on little-endian platforms.
Revie
The public qe_ic.h header is no longer included by anything but
qe_ic.c. Merge both headers into qe_ic.c, and drop the unused
constants.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 52 +++-
drivers/soc/fsl/qe/qe_ic.h | 99
This driver is currently PPC-only, and on powerpc, NO_IRQ is 0, so
this doesn't change functionality. However, not every architecture
defines NO_IRQ, and some define it as -1, so the detection of a failed
irq_of_parse_and_map() (which returns 0 on failure) would be wrong on
those. So to prepare for
These are only called from within qe_ic.c, so make them static.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 4 ++--
include/soc/fsl/qe/qe_ic.h | 10 --
2 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.
There are no current callers of these functions, and they use the
ppc-specific virq_to_hw(). So removing them gets us one step closer to
building QE support for ARM.
If the functionality is ever actually needed, the code can be dug out
of git and then adapted to work on all architectures, but for
qe_ic_init() takes a flags parameter, but all callers (including the
sole remaining one) have always passed 0. So remove that parameter and
simplify the body accordingly. We still explicitly initialize the
Interrupt Configuration Register (CICR) to its reset value of
all-zeroes, just in case the bo
The qe_ic_cascade_{low,high}_mpic functions are now used as handlers
both when the interrupt parent is mpic as well as ipic, so remove the
_mpic suffix.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 8
1 file changed, 4 insertions(+), 4 deleti
These functions are only ever called through a function pointer, and
therefore it makes no sense for them to be "static inline" - gcc has
no choice but to emit a copy in each translation unit that takes the
address of one of these. Since they are now only referenced from
qe_ic.c, just make them loc
Since commit 302c059f2e7b (QE: use subsys_initcall to init qe),
mpc85xx_qe_init() has done nothing apart from possibly emitting a
pr_err(). As part of reducing the amount of QE-related code in
arch/powerpc/ (and eventually support QE on other architectures),
remove this low-hanging fruit.
Acked-by
This is now exactly the same as mpc83xx_ipic_init_IRQ, so just use
that directly.
Acked-by: Scott Wood
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
arch/powerpc/platforms/83xx/km83xx.c | 2 +-
arch/powerpc/platforms/83xx/misc.c| 7 ---
arch/powerpc/platforms/83x
Having to call qe_ic_init() from platform-specific code makes it
awkward to allow building the QE drivers for ARM. It's also a needless
duplication of code, and slightly error-prone: Instead of the caller
needing to know the details of whether the QUICC Engine High and QUICC
Engine Low are actually
The *_ipic and *_mpic handlers are almost identical - the only
difference is that the latter end with an unconditional
chip->irq_eoi() call. Since IPIC does not have ->irq_eoi, we can
reduce some code duplication by calling irq_eoi conditionally.
This is similar to what is already done in mpc8xxx_
There's no point in registering with sysfs when that doesn't actually
allow any interaction with the device or driver (no uevents, no sysfs
files that provide information or allow configuration, no nothing).
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c
high_active is only assigned to but never used. Remove it.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe_ic.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 8c874372416b.
These includes are not actually needed, and asm/rheap.h and
sysdev/fsl_soc.h are PPC-specific, hence prevent compiling QE for
other architectures.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe.c| 5 -
drivers/soc/fsl/qe/qe_io.c | 2 --
2 files changed
Commit e5c5c8d23fef (soc/fsl/qe: only apply QE_General4 workaround on
affected SoCs) introduced use of pvr_version_is(), saying
The QE_General4 workaround is only valid for the MPC832x and MPC836x
SoCs. The other SoCs that embed a QUICC engine are not affected by this
hardware bug and
In preparation for allowing QE to be built for architectures other
than ppc, use the generic readx_poll_timeout_atomic() helper from
iopoll.h rather than the ppc-only spin_event_timeout().
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe.c | 13 +++--
1
In preparation for allowing to build QE support for architectures
other than PPC, replace the ppc-specific io accessors by the qe_io*
macros. Done via
$ spatch --sp-file io.cocci --in-place drivers/soc/fsl/qe/
where io.cocci is
@@
expression addr, val;
@@
- out_be32(addr, val)
+ qe_iowrite32be(v
The QUICC engine drivers use the powerpc-specific out_be32() etc. In
order to allow those drivers to build for other architectures, those
must be replaced by iowrite32be(). However, on powerpc, out_be32() is
a simple inline function while iowrite32be() is out-of-line. So in
order not to introduce a
Make it clear that these operate on big-endian registers (i.e. use the
iowrite*be primitives) before we introduce more uses of them and allow
the QE drivers to be built for platforms other than ppc32.
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/net/wan/fsl_ucc_hdlc.c |
The actual io accessors (e.g. in_be32) implicitly add a volatile
qualifier to their address argument. Remove volatile from the struct
definition and the qe_ic_(read/write) helpers, in preparation for
switching from the ppc-specific io accessors to generic ones.
Reviewed-by: Timur Tabi
Signed-off-
There have been several attempts in the past few years to allow
building the QUICC engine drivers for platforms other than PPC32. This
is yet another attempt.
v5 can be found here:
https://lore.kernel.org/lkml/20191118112324.22725-1-li...@rasmusvillemoes.dk/
Changes in v6:
- add various R-b, A-
Reviewed-by: Timur Tabi
Signed-off-by: Rasmus Villemoes
---
drivers/soc/fsl/qe/qe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 417df7e19281..2a0e6e642776 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fs
On Thu, Nov 28, 2019 at 1:16 PM Christophe Leroy
wrote:
> Since commit 0f0581b24bd0 ("spi: fsl: Convert to use CS GPIO
> descriptors"), the prefered way to define chipselect GPIOs is using
> 'cs-gpios' property instead of the legacy 'gpios' property.
>
> Signed-off-by: Christophe Leroy
Reviewed
Since commit 0f0581b24bd0 ("spi: fsl: Convert to use CS GPIO
descriptors"), the prefered way to define chipselect GPIOs is using
'cs-gpios' property instead of the legacy 'gpios' property.
Signed-off-by: Christophe Leroy
---
Documentation/devicetree/bindings/spi/fsl-spi.txt | 8
arch/po
"Anju T Sudhakar" wrote on 27/11/2019 12:50:35
PM:
> From: "Anju T Sudhakar"
> To: m...@ellerman.id.au
> Cc: linuxppc-dev@lists.ozlabs.org, a...@linux.vnet.ibm.com,
> Nageswara R Sastry/India/IBM@IBMIN
> Date: 27/11/2019 12:50 PM
> Subject: [PATCH v3] platforms/powernv: Avoid re-registration of
On 2019-11-26, Aleksa Sarai wrote:
> On 2019-11-25, Al Viro wrote:
> > On Sun, Nov 17, 2019 at 12:17:10PM +1100, Aleksa Sarai wrote:
> > > + if (unlikely(nd->flags & LOOKUP_IS_SCOPED)) {
> > > + /*
> > > + * If there was a racing rename or mount along our
Le 27/11/2019 à 15:43, Christophe Leroy a écrit :
Le 26/11/2019 à 02:13, Michael Ellerman a écrit :
On Thu, 2019-09-12 at 13:49:41 UTC, Christophe Leroy wrote:
fixmap is intended to map things permanently like the IMMR region on
FSL SOC (8xx, 83xx, ...), so don't clear it when initialising
Commit f2bb86937d86 ("powerpc/fixmap: don't clear fixmap area in
paging_init()") removed the clearing of fixmap area in order to
avoid clearing fixmapped areas set earlier.
However unlike all other users of fixmap which use __set_fixmap(),
HIGHMEM functions directly use __set_pte_at(). This means
69 matches
Mail list logo
