To check machine check handling, add support to inject slb
multihit errors.
Cc: Kees Cook
Reviewed-by: Michal Suchánek
Co-developed-by: Mahesh Salgaonkar
Signed-off-by: Mahesh Salgaonkar
Signed-off-by: Ganesh Goudar
---
drivers/misc/lkdtm/Makefile | 1 +
drivers/misc/lkdtm/core
Use of nmi_enter/exit in real mode handler causes the kernel to panic
and reboot on injecting slb mutihit on pseries machine running in hash
mmu mode, As these calls try to accesses memory outside RMO region in
real mode handler where translation is disabled.
Add check to not to use these calls on
This patch series fixes mce handling for pseries, Adds LKDTM test
for SLB multihit recovery and enables selftest for the same,
basically to test MCE handling on pseries/powernv machines running
in hash mmu mode.
v4:
* Use radix_enabled() to check if its in Hash or Radix mode.
* Use FW_FEATURE_LPAR
On 10/1/20 11:21 PM, Ganesh Goudar wrote:
Use of nmi_enter/exit in real mode handler causes the kernel to panic
and reboot on injecting slb mutihit on pseries machine running in hash
mmu mode, As these calls try to accesses memory outside RMO region in
real mode handler where translation is disa
On Mon, 14 Sep 2020 02:49:04 +0530, Vaibhav Jain wrote:
> Add NVDIMM_FAMILY_PAPR to the list of valid 'dimm_family_mask'
> acceptable by papr_scm. This is needed as since commit
> 92fe2aa859f5 ("libnvdimm: Validate command family indices") libnvdimm
> performs a validation of 'nd_cmd_pkg.nd_family'
On Tue, 22 Sep 2020 13:32:54 +0530, Srikar Dronamraju wrote:
> The patch avoids allocating cpufreq_policy on stack hence fixing frame
> size overflow in 'powernv_cpufreq_reboot_notifier'
>
> ./drivers/cpufreq/powernv-cpufreq.c: In function
> _powernv_cpufreq_reboot_notifier_:
> ./drivers/cpufreq/
On Wed, 7 Oct 2020 15:09:02 +1100, Oliver O'Halloran wrote:
> The eeh_pe->config_addr field was supposed to be removed in
> commit 35d64734b643 ("powerpc/eeh: Clean up PE addressing") which made it
> largely unused. Finish the job.
Applied to powerpc/next.
[1/2] powerpc/eeh: Delete eeh_pe->config
On Wed, 7 Oct 2020 18:06:05 +1000, Nicholas Piggin wrote:
> The inline execution path for the hardware assisted branch flush
> instruction failed to set CTR to the correct value before bcctr,
> causing a crash when the feature is enabled.
Applied to powerpc/next.
[1/1] powerpc/security: Fix link
On Sat, 3 Oct 2020 13:19:39 +0530, Kajol Jain wrote:
> Commit 9e9f60108423f ("powerpc/perf/{hv-gpci, hv-common}: generate
> requests with counters annotated") adds a framework for defining
> gpci counters.
> In this patch, they adds starting_index value as '0x'.
> which is wrong as
On Tue, 29 Sep 2020 06:48:31 + (UTC), Christophe Leroy wrote:
> SYNC is usefull for Powerpc 601 only. On everything else,
> SYNC is empty.
>
> Remove it from code that is not made to run on 6xx.
Applied to powerpc/next.
[1/8] powerpc: Remove SYNC on non 6xx
https://git.kernel.org/power
On Thu, 1 Oct 2020 10:59:19 + (UTC), Christophe Leroy wrote:
> Move SPRN_PIT definition in reg.h.
>
> This allows to remove ifdef in get_dec() and set_dec() and
> makes them more readable.
Applied to powerpc/next.
[1/1] powerpc/time: Remove ifdef in get_dec() and set_dec()
https://git.
On Thu, 1 Oct 2020 15:35:38 + (UTC), Christophe Leroy wrote:
> At the time being, an early hash table is set up when
> CONFIG_KASAN is selected.
>
> There is nothing wrong with setting such an early hash table
> all the time, even if it is not used. This is a statically
> allocated 256 kB tabl
On Thu, 1 Oct 2020 12:42:39 + (UTC), Christophe Leroy wrote:
> On PPC64, we have mftb().
> On PPC32, we have mftbl() and an #define mftb() mftbl().
>
> mftb() and mftbl() are equivalent, their purpose is to read the
> content of SPRN_TRBL, as returned by 'mftb' simplified instruction.
>
> bin
On Tue, 6 Oct 2020 09:05:26 + (UTC), Christophe Leroy wrote:
> Unlike PPC64 which had a single head_64.S, PPC32 are multiple ones.
> There is the head_32.S, selected by default based on the value of BITS
> and overridden based on some CONFIG_ values. This leads to thinking
> that it may be sele
On Wed, 7 Oct 2020 17:18:32 +0530, Aneesh Kumar K.V wrote:
> Changes from v2:
> * Don't use root addr and size cells during runtime. Walk up the
> device tree and use the first addr and size cells value (of_n_addr_cells()/
> of_n_size_cells())
>
> Aneesh Kumar K.V (4):
> powerpc/drmem: Make
When perf is enabled, r11 must also be restored when CONFIG_HUGETLBFS
is selected.
Fixes: a891c43b97d3 ("powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k
pages.")
Cc: sta...@vger.kernel.org
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 2 +-
1 file changed, 1 inserti
Vasant Hegde writes:
> diff --git a/arch/powerpc/platforms/powernv/opal-dump.c
> b/arch/powerpc/platforms/powernv/opal-dump.c
> index 543c816fa99e..7e6eeedec32b 100644
> --- a/arch/powerpc/platforms/powernv/opal-dump.c
> +++ b/arch/powerpc/platforms/powernv/opal-dump.c
> @@ -346,21 +345,39 @@ sta
Vasant Hegde writes:
> OPAL interrupts kernel whenever it has new error log. Kernel calls
> interrupt handler (elog_event()) to retrieve event. elog_event makes
> OPAL API call (opal_get_elog_size()) to retrieve elog info.
>
> In some case before kernel makes opal_get_elog_size() call, it gets int
Stephen Rothwell writes:
> Hi all,
>
> In commit
>
> a2d0230b91f7 ("cpufreq: powernv: Fix frame-size-overflow in
> powernv_cpufreq_reboot_notifier")
>
> Fixes tag
>
> Fixes: cf30af76 ("cpufreq: powernv: Set the cpus to nominal frequency
> during reboot/kexec")
Gah.
I've changed my scripts
Rob Herring writes:
> booting-without-of.rstt is an ancient document that first outlined
^
nit
> Flattened DeviceTree on PowerPC initially. The DT world has evolved a
> lot in the 15 years since and booting-without-of.rst is pretty stale.
> The name
allmodconfig
powerpc allnoconfig
x86_64 randconfig-a004-20201008
x86_64 randconfig-a003-20201008
x86_64 randconfig-a005-20201008
x86_64 randconfig-a001-20201008
x86_64 randconfig-a002
onfig
i386defconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a004-20201
The Linux kernel for powerpc has an issue with the Run-Time Abstraction
Services (RTAS) interface, allowing root (or CAP_SYS_ADMIN users) in a
VM to overwrite some parts of memory, including kernel memory.
This issue impacts guests running on top of PowerVM or KVM hypervisors
(pseries platform
Hi all,
In commit
a2d0230b91f7 ("cpufreq: powernv: Fix frame-size-overflow in
powernv_cpufreq_reboot_notifier")
Fixes tag
Fixes: cf30af76 ("cpufreq: powernv: Set the cpus to nominal frequency during
reboot/kexec")
has these problem(s):
- SHA1 should be at least 12 digits long
Can
On 10/8/20 10:32 PM, Linus Torvalds wrote:
On Thu, Oct 8, 2020 at 2:27 AM Aneesh Kumar K.V
wrote:
In copy_present_page, after we mark the pte non-writable, we should
check for previous dirty bit updates and make sure we don't lose the dirty
bit on reset.
No, we'll just remove that entirely.
On Thu, Oct 8, 2020 at 10:02 AM Linus Torvalds
wrote:
>
> Here's the first patch anyway. If you actually have a test-case where
> this matters, I guess I need to apply it now..
Actually, I removed the "__page_mapcount()" part of that patch, to
keep it minimal and _only_ do remove the wrprotect tr
Ahh, and I should learn to read all my emails before replying to some of them..
On Thu, Oct 8, 2020 at 2:26 AM Aneesh Kumar K.V
wrote:
>
> This avoids the below warning
> [..]
> WARNING: CPU: 0 PID: 30613 at arch/powerpc/mm/pgtable.c:185
set_pte_at+0x2a8/0x3a0 arch/powerpc/mm/pgtable.c:185
.. a
[ Just adding Leon to the participants ]
This patch (not attached again, Leon has seen it before) has been
tested for the last couple of weeks for the rdma case, so I have no
problems applying it now, just to keep everybody in the loop.
Linus
On Thu, Oct 8, 2020 at 10:02 AM Linus To
On Thu, Oct 8, 2020 at 2:27 AM Aneesh Kumar K.V
wrote:
>
> In copy_present_page, after we mark the pte non-writable, we should
> check for previous dirty bit updates and make sure we don't lose the dirty
> bit on reset.
No, we'll just remove that entirely.
Do you have a test-case that shows a pr
On Thu, Oct 08, 2020 at 09:24:20AM -0500, Rob Herring wrote:
> booting-without-of.rstt is an ancient document that first outlined
> Flattened DeviceTree on PowerPC initially. The DT world has evolved a
> lot in the 15 years since and booting-without-of.rst is pretty stale.
> The name of the documen
booting-without-of.rstt is an ancient document that first outlined
Flattened DeviceTree on PowerPC initially. The DT world has evolved a
lot in the 15 years since and booting-without-of.rst is pretty stale.
The name of the document itself is confusing if you don't understand the
evolution from real
Document the PowerPC specific 'sleep' property as a schema. It is
currently only documented in booting-without-of.rst which is getting
removed.
Cc: Michael Ellerman
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Rob Herring
---
.../devicetree/bi
suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Ravi-Bangoria/powerpc-sstep-VSX-32-byte-vector-paired-load-store-instructions/20201008-153614
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc
On Thu, Oct 08, 2020 at 09:34:26PM +1100, Michael Ellerman wrote:
> Jann Horn writes:
> > So while the mprotect() case
> > checks the flags and refuses unknown values, the mmap() code just lets
> > the architecture figure out which bits are actually valid to set (via
> > arch_calc_vm_prot_bits())
Srikar Dronamraju writes:
> * Michael Ellerman [2020-09-17 21:28:46]:
>
>> On Tue, 8 Sep 2020 22:58:50 +1000, Michael Ellerman wrote:
>> > When we added the VDSO32 kconfig symbol, which controls building of
>> > the 32-bit VDSO, we made it depend on CPU_BIG_ENDIAN (for 64-bit).
>> >
>> > That wa
By setting exclude_kernel for user space profiling, we set the
freeze bits in Monitor Mode Control Register. Due to hardware
limitation, sometimes, Sampled Instruction Address register (SIAR)
captures kernel address even when counter freeze bits are set in
Monitor Mode Control Register (MMCR2). Pat
On power10 DD1, there is an issue that causes the SIAR_VALID
bit of Sampled Instruction Event Register(SIER) not to be
set. But the SIAR_VALID bit is used for fetching the instruction
address from Sampled Instruction Address Register(SIAR), and
marked events are sampled only if the SIAR_VALID bit i
While setting the processor mode for any sample, `perf_get_misc_flags`
expects the privilege level to differentiate the userspace and kernel
address. On power10 DD1, there is an issue that causes [MSR_HV MSR_PR] bits
of Sampled Instruction Event Register (SIER) not to be set for marked
events. Henc
Add a new power PMU flag "PPMU_P10_DD1" which can be
used to conditionally add any code path for power10 DD1 processor
version. Also modify power10 PMU driver code to set this
flag only for DD1, based on the Processor Version Register (PVR)
value.
Signed-off-by: Athira Rajeev
---
arch/powerpc/in
The patch series addresses PMU fixes for power10 DD1
Patch1 introduces a new power pmu flag to include
conditional code changes for power10 DD1.
Patch2 and Patch3 includes fixes in core-book3s to address
issues with marked events during sampling.
Patch4 includes fix to drop kernel samples while
us
Jann Horn writes:
> On Wed, Oct 7, 2020 at 2:35 PM Christoph Hellwig wrote:
>> On Wed, Oct 07, 2020 at 09:39:31AM +0200, Jann Horn wrote:
>> > diff --git a/arch/powerpc/kernel/syscalls.c
>> > b/arch/powerpc/kernel/syscalls.c
>> > index 078608ec2e92..b1fabb97d138 100644
>> > --- a/arch/powerpc/ke
On Wed, Oct 07, 2020 at 09:39:31AM +0200, Jann Horn wrote:
> arch_validate_prot() is a hook that can validate whether a given set of
> protection flags is valid in an mprotect() operation. It is given the set
> of protection flags and the address being modified.
>
> However, the address being modi
Michael Ellerman writes:
> Andrew Donnellan writes:
>> On 26/8/20 11:53 pm, Sasha Levin wrote:
>>> How should we proceed with this patch?
>>
>> mpe: I believe we came to the conclusion that we shouldn't put this in
>> stable just yet?
>
> Yeah.
>
> Let's give it a little time to get some wider t
Andrew Donnellan writes:
> On 26/8/20 11:53 pm, Sasha Levin wrote:
>> How should we proceed with this patch?
>
> mpe: I believe we came to the conclusion that we shouldn't put this in
> stable just yet?
Yeah.
Let's give it a little time to get some wider testing before we backport
it.
cheers
Le 07/10/2020 à 08:50, Herbert Xu a écrit :
On Sat, Oct 03, 2020 at 07:15:53PM +0200, Christophe Leroy wrote:
The following changes fix the sparse warnings with less churn:
Yes that works too. Can you please submit this patch?
This fixed two independant commits from the past. I sent ou
In a 10 years old commit
(https://github.com/linuxppc/linux/commit/d069cb4373fe0d451357c4d3769623a7564dfa9f), powerpc 8xx has
made the handling of PTE accessed bit conditional to CONFIG_SWAP.
Since then, this has been extended to some other powerpc variants.
That commit means that when CONFIG_S
current_desc_hdr() returns a u32 but in fact this is a __be32,
leading to a lot of sparse warnings.
Change the return type to __be32 and ensure it is handled as
sure by the caller.
Fixes: 3e721aeb3df3 ("crypto: talitos - handle descriptor not found in error
path")
Signed-off-by: Christophe Leroy
current_desc_hdr() compares the value of the current descriptor
with the next_desc member of the talitos_desc struct.
While the current descriptor is obtained from in_be32() which
return CPU ordered bytes, next_desc member is in big endian order.
Convert the current descriptor into big endian bef
In copy_present_page, after we mark the pte non-writable, we should
check for previous dirty bit updates and make sure we don't lose the dirty
bit on reset.
Also, avoid marking the pte write-protected again if copy_present_page
already marked it write-protected.
Cc: Peter Xu
Cc: Jason Gunthorpe
This avoids the below warning
WARNING: CPU: 0 PID: 30613 at arch/powerpc/mm/pgtable.c:185
set_pte_at+0x2a8/0x3a0 arch/powerpc/mm/pgtable.c:185
Kernel panic - not syncing: panic_on_warn set ...
CPU: 0 PID: 30613 Comm: syz-executor.0 Not tainted
5.9.0-rc8-syzkaller-00156-gc85fb28b6f99 #0
Call Trac
From: Balamuruhan S
Add testcases for VSX vector paired load/store instructions.
Sample o/p:
emulate_step_test: lxvp : PASS
emulate_step_test: stxvp : PASS
emulate_step_test: lxvpx : PASS
emulate_step_test: stxvpx : PASS
emulate_step_test: plxvp
From: Balamuruhan S
Add instruction encodings, DQ, D0, D1 immediate, XTP, XSP operands as
macros for new VSX vector paired instructions,
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Prefixed Load VSX Vector Paired (plxvp)
* Store VSX Vector Paired (stxvp)
*
From: Balamuruhan S
VSX Vector Paired instructions loads/stores an octword (32 bytes)
from/to storage into two sequential VSRs. Add emulation support
for these new instructions:
* Load VSX Vector Paired (lxvp)
* Load VSX Vector Paired Indexed (lxvpx)
* Prefixed Load VSX Vector Paired (plxvp
VSX vector paired instructions operates with octword (32-byte)
operand for loads and stores between storage and a pair of two
sequential Vector-Scalar Registers (VSRs). There are 4 word
instructions and 2 prefixed instructions that provides this
32-byte storage access operations - lxvp, lxvpx, stxv
From: Balamuruhan S
Unconditional emulation of prefixed instructions will allow
emulation of them on Power10 predecessors which might cause
issues. Restrict that.
Signed-off-by: Balamuruhan S
Signed-off-by: Ravi Bangoria
---
arch/powerpc/lib/sstep.c | 6 ++
1 file changed, 6 insertions(+)
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