Le 09/03/2021 à 01:02, Daniel Walker a écrit :
This updates the powerpc code to use the CONFIG_GENERIC_CMDLINE
option.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan Ruslichenko
Signed-off-by: Ruslan Bilovol
Signed-off-by: Daniel Walker
---
arch/powerpc/Kconfig| 37
Le 09/03/2021 à 01:02, Daniel Walker a écrit :
This is a scripted mass convert of the config files to use
the new generic cmdline. There is a bit of a trim effect here.
It would seems that some of the config haven't been trimmed in
a while.
If you do that in a separate patch, you loose
Le 09/03/2021 à 01:02, Daniel Walker a écrit :
It looks like there's some seepage of cmdline stuff into
the generic device tree code. This conflicts with the
generic cmdline implementation so I remove it in the case
when that's enabled.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan
Le 09/03/2021 à 01:02, Daniel Walker a écrit :
This code allows architectures to use a generic builtin command line.
The state of the builtin command line options across architecture is
diverse. On x86 and mips they have pretty much the same code and the
code prepends the builtin command line
In ppc_function_entry() we look for a specific set of instructions by
masking the instructions and comparing with a known value. Currently
those known values are just literal hex values, and we recently
discovered one of them was wrong.
Instead construct the values using the existing constants we
On Tue, 9 Mar 2021 at 01:03, Daniel Walker wrote:
>
> This updates the x86 code to use the CONFIG_GENERIC_CMDLINE
> option.
>
> Cc: xe-linux-exter...@cisco.com
> Signed-off-by: Ruslan Ruslichenko
> Signed-off-by: Ruslan Bilovol
> Signed-off-by: Daniel Walker
> ---
> arch/x86/Kconfig
With some defconfig including CONFIG_CC_OPTIMIZE_FOR_SIZE,
(for instance mvme5100_defconfig and ps3_defconfig), gcc 5
generates a call to _restgpr_31_x.
Until recently it went unnoticed, but
commit 42ed6d56ade2 ("powerpc/vdso: Block R_PPC_REL24 relocations")
made it rise to the surface.
Provide
On 3/8/21 8:36 PM, Chris Packham wrote:
>
> On 9/03/21 11:10 am, Chris Packham wrote:
>>
>> On 8/03/21 5:59 pm, Guenter Roeck wrote:
>>> On 3/7/21 8:37 PM, Chris Packham wrote:
>>> [ ... ]
> That's from -ENXIO which is used in only one place in i2c-mpc.c. I'll
> enable some debug and see
This patch future-proofs the kernel against linker changes that might
put the toc pointer at some location other than .got+0x8000, by
replacing __toc_start+0x8000 with __toc_ptr throughout. __toc_ptr
is set from the symbol .TOC. emitted by ld on a final link, falling
back to .got+0x8000 for older
On 9/03/21 11:10 am, Chris Packham wrote:
>
> On 8/03/21 5:59 pm, Guenter Roeck wrote:
>> On 3/7/21 8:37 PM, Chris Packham wrote:
>> [ ... ]
That's from -ENXIO which is used in only one place in i2c-mpc.c. I'll
enable some debug and see what we get.
>>> For the errant readings there was
On 3/8/21 12:11 PM, Anshuman Khandual wrote:
> This series contains config cleanup patches which reduces code duplication
> across platforms and also improves maintainability. There is no functional
> change intended with this series. This has been boot tested on arm64 but
> only build tested on
49a7d46a06c3 (powerpc: Implement smp_cond_load_relaxed()) added
busy-waiting pausing with a preferred SMT priority pattern, lowering
the priority (reducing decode cycles) during the whole loop slowpath.
However, data shows that while this pattern works well with simple
spinlocks, queued spinlocks
c6f5d02b6a0f (locking/spinlocks/arm64: Remove smp_mb() from
arch_spin_is_locked()) made it pretty official that the call
semantics do not imply any sort of barriers, and any user that
gets creative must explicitly do any serialization.
This creativity, however, is nowadays pretty limited:
1.
Instead of both queued and simple spinlocks doing it. Move
it into the arch's spinlock.h.
Signed-off-by: Davidlohr Bueso
---
arch/powerpc/include/asm/qspinlock.h | 2 --
arch/powerpc/include/asm/simple_spinlock.h | 3 ---
arch/powerpc/include/asm/spinlock.h| 3 +++
3 files
Hi,
A few updates while going through the powerpc port of the qspinlock.
Patches 1 and 2 are straightforward, while patch 3 can be considered
more of an rfc as I've only tested on a single machine, and there
could be an alternative way if it doesn't end up being nearly a
universal performance
Fabiano Rosas writes:
> Nicholas Piggin writes:
>
>> Excerpts from Fabiano Rosas's message of March 6, 2021 9:10 am:
>>> As one of the arguments of the H_ENTER_NESTED hypercall, the nested
>>> hypervisor (L1) prepares a structure containing the values of various
>>> hypervisor-privileged
On 3/8/21 3:53 PM, Daniel Walker wrote:
> This fixed some problem identified in my last release. I made updates
> based on comments from Christophe Leroy.
>
> I added scripted updates to the defconfig file for mips and powerpc.
> This is required in order to maintain the status quo for those
Excerpts from Fabiano Rosas's message of March 9, 2021 1:47 am:
> Nicholas Piggin writes:
>
>> This bit only applies to hash partitions.
>>
>> Signed-off-by: Nicholas Piggin
>> ---
>> arch/powerpc/kvm/book3s_hv.c| 6 --
>> arch/powerpc/kvm/book3s_hv_nested.c | 2 +-
>> 2 files
Excerpts from Fabiano Rosas's message of March 9, 2021 1:26 am:
> Nicholas Piggin writes:
>
>> These are already disallowed by H_SET_MODE from the guest, also disallow
>> these by updating LPCR directly.
>>
>> AIL modes can affect the host interrupt behaviour while the guest LPCR
>> value is
Excerpts from Fabiano Rosas's message of March 9, 2021 1:04 am:
> Nicholas Piggin writes:
>
>> Excerpts from Fabiano Rosas's message of March 6, 2021 9:10 am:
>>> As one of the arguments of the H_ENTER_NESTED hypercall, the nested
>>> hypervisor (L1) prepares a structure containing the values of
allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a006-20210308
x86_64 randconfig-a001-20210308
x86_64 randconfig-a004-20210308
allnoconfig
x86_64 randconfig-a006-20210308
x86_64 randconfig-a001-20210308
x86_64 randconfig-a004-20210308
x86_64 randconfig-a002-20210308
x86_64 randconfig-a005-20210308
x86_64 randconfig-a003-20210308
This updates the x86 code to use the CONFIG_GENERIC_CMDLINE
option.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan Ruslichenko
Signed-off-by: Ruslan Bilovol
Signed-off-by: Daniel Walker
---
arch/x86/Kconfig| 44 +
arch/x86/kernel/setup.c
This updates the mips code to use the CONFIG_GENERIC_CMDLINE
option.
This deletes the option for MIPS_CMDLINE_BUILTIN_EXTEND
and replaces the functionality with generic code.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan Ruslichenko
Signed-off-by: Ruslan Bilovol
Signed-off-by: Daniel
This is a scripted mass convert of the config files to use
the new generic cmdline. There is a bit of a trim effect here.
It would seems that some of the config haven't been trimmed in
a while.
The script used is as follows,
if [[ -z "$1" || -z "$2" ]]; then
echo "Two arguments are
This updates the powerpc code to use the CONFIG_GENERIC_CMDLINE
option.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan Ruslichenko
Signed-off-by: Ruslan Bilovol
Signed-off-by: Daniel Walker
---
arch/powerpc/Kconfig| 37 +
This is a scripted mass convert of the config files to use
the new generic cmdline. There is a bit of a trim effect here.
It would seems that some of the config haven't been trimmed in
a while.
The bash script used to convert is as follows,
if [[ -z "$1" || -z "$2" ]]; then
echo "Two
It looks like there's some seepage of cmdline stuff into
the generic device tree code. This conflicts with the
generic cmdline implementation so I remove it in the case
when that's enabled.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan Ruslichenko
Signed-off-by: Daniel Walker
---
This fixed some problem identified in my last release. I made updates
based on comments from Christophe Leroy.
I added scripted updates to the defconfig file for mips and powerpc.
This is required in order to maintain the status quo for those platforms
which used the prior builtin command line
This code allows architectures to use a generic builtin command line.
The state of the builtin command line options across architecture is
diverse. On x86 and mips they have pretty much the same code and the
code prepends the builtin command line onto the boot loader provided
one. On powerpc there
It looks like there's some seepage of cmdline stuff into
the generic device tree code. This conflicts with the
generic cmdline implementation so I remove it in the case
when that's enabled.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan Ruslichenko
Signed-off-by: Daniel Walker
---
This code allows architectures to use a generic builtin command line.
The state of the builtin command line options across architecture is
diverse. On x86 and mips they have pretty much the same code and the
code prepends the builtin command line onto the boot loader provided
one. On powerpc there
This fixed some problem identified in my last release. I made updates
based on comments from Christophe Leroy.
I added scripted updates to the defconfig file for mips and powerpc.
This is required in order to maintain the status quo for those platforms
which used the prior builtin command line
On Mon, Mar 08, 2021 at 08:27:30PM +, Chris Packham wrote:
[ ... ]
> > Other than that, the only other real idea I have would be to monitor
> > the i2c bus.
> I am in the fortunate position of being able to go into the office and
> even happen to have the expensive scope at the moment. Now I
On 8/03/21 5:59 pm, Guenter Roeck wrote:
> On 3/7/21 8:37 PM, Chris Packham wrote:
> [ ... ]
>>> That's from -ENXIO which is used in only one place in i2c-mpc.c. I'll
>>> enable some debug and see what we get.
>> For the errant readings there was nothing abnormal reported by the driver.
>>
>> For
On 8/03/21 5:59 pm, Guenter Roeck wrote:
> On 3/7/21 8:37 PM, Chris Packham wrote:
> [ ... ]
>>> That's from -ENXIO which is used in only one place in i2c-mpc.c. I'll
>>> enable some debug and see what we get.
>> For the errant readings there was nothing abnormal reported by the driver.
>>
>> For
On Wed, 3 Mar 2021 18:48:51 +0100
Cédric Le Goater wrote:
> The IPI interrupt is a special case of the XIVE IRQ domain. When
> mapping and unmapping the interrupts in the Linux interrupt number
> space, the HW interrupt number 0 (XIVE_IPI_HW_IRQ) is checked to
> distinguish the IPI interrupt
Hello:
This patch was applied to netdev/net.git (refs/heads/master):
On Sun, 7 Mar 2021 01:12:56 -0800 you wrote:
> When priv->rx_skbuff or priv->tx_skbuff is NULL, no error return code of
> uhdlc_init() is assigned.
> To fix this bug, ret is assigned with -ENOMEM in these cases.
>
>
On Wed 2021-03-03 16:34:19, Petr Mladek wrote:
> On Wed 2021-03-03 11:15:13, John Ogness wrote:
> > Hello,
> >
> > Here is v4 of a series to remove @logbuf_lock, exposing the
> > ringbuffer locklessly to both readers and writers. v3 is
> > here [0].
>
> The series look ready. I am going to push
On 3/8/21 7:07 PM, Greg Kurz wrote:
> On Wed, 3 Mar 2021 18:48:53 +0100
> Cédric Le Goater wrote:
>
>> Now that the IPI interrupt has its own domain, the checks on the HW
>> interrupt number XIVE_IPI_HW_IRQ and on the chip can be replaced by a
>> check on the domain.
>>
>> Signed-off-by: Cédric
On Wed, 3 Mar 2021 18:48:53 +0100
Cédric Le Goater wrote:
> Now that the IPI interrupt has its own domain, the checks on the HW
> interrupt number XIVE_IPI_HW_IRQ and on the chip can be replaced by a
> check on the domain.
>
> Signed-off-by: Cédric Le Goater
> ---
Shouldn't this have the
On Wed, 3 Mar 2021 18:48:52 +0100
Cédric Le Goater wrote:
> The IPI interrupt has its own domain now. Testing the HW interrupt
> number is not needed anymore.
>
> Signed-off-by: Cédric Le Goater
> ---
Reviewed-by: Greg Kurz
> arch/powerpc/sysdev/xive/common.c | 3 +--
> 1 file changed, 1
Nicholas Piggin writes:
> LPCR[HDICE]=0 suppresses hypervisor decrementer exceptions on some
> processors, so it must be enabled before HDEC is set.
>
> Rather than set it in the host LPCR then setting HDEC, move the HDEC
> update to after the guest MMU context (including LPCR) is loaded.
>
On Wed, 3 Mar 2021 18:48:50 +0100
Cédric Le Goater wrote:
> The 'chip_id' field of the XIVE CPU structure is used to choose a
> target for a source located on the same chip when possible. This field
> is assigned on the PowerNV platform using the "ibm,chip-id" property
> on pSeries under KVM
On Tue, 2 Mar 2021 20:50:02 +0800, Tang Bin wrote:
> In this function, devm_platform_ioremap_resource_byname() should be
> suitable to simplify code.
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/1] ASoC: fsl_xcvr: Use
Nicholas Piggin writes:
> This bit only applies to hash partitions.
>
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/kvm/book3s_hv.c| 6 --
> arch/powerpc/kvm/book3s_hv_nested.c | 2 +-
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git
Nicholas Piggin writes:
> These are already disallowed by H_SET_MODE from the guest, also disallow
> these by updating LPCR directly.
>
> AIL modes can affect the host interrupt behaviour while the guest LPCR
> value is set, so filter it here too.
>
> Suggested-by: Fabiano Rosas
>
Nicholas Piggin writes:
> Excerpts from Fabiano Rosas's message of March 6, 2021 9:10 am:
>> As one of the arguments of the H_ENTER_NESTED hypercall, the nested
>> hypervisor (L1) prepares a structure containing the values of various
>> hypervisor-privileged registers with which it wants the
The radeon warning is trivial to fix, going to send out a patch in a few
moments.
Regards,
Christian.
Am 08.03.21 um 13:14 schrieb Christophe Leroy:
+Evgeniy for W1 Dallas
+Alex & Christian for RADEON
Le 07/03/2021 à 11:23, kernel test robot a écrit :
Hi Christophe,
I love your patch!
+Evgeniy for W1 Dallas
+Alex & Christian for RADEON
Le 07/03/2021 à 11:23, kernel test robot a écrit :
Hi Christophe,
I love your patch! Perhaps something to improve:
[auto build test WARNING on powerpc/next]
[also build test WARNING on v5.12-rc2 next-20210305]
[If your patch is applied to
On 2021/03/05 12:37PM, Christophe Leroy wrote:
>
>
> Le 04/03/2021 à 03:04, Naveen N. Rao a écrit :
> > 'lis r2,N' is 'addis r2,0,N' and the instruction encoding in the macro
> > LIS_R2 is incorrect (it currently maps to 'addis 0,r2,N'). Fix the same.
> >
> > Fixes: c71b7eff426fa7 ("powerpc:
With the new interrupt exit code, context tracking can be managed
more precisely, so remove the last of the 64e workarounds and switch
to the new context tracking code already used by 64s.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/interrupt.h | 28
With non-volatile registers saved on interrupt, bad_page_fault
can now be called by do_page_fault.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64e.S | 6 --
arch/powerpc/mm/fault.c | 4 ++--
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git
Change KVM to keep the irq soft-mask state hard disabled when entering
the guest, to avoid "reconciling" the state when exiting the guest.
IRQ tracing still has to be updated so host irqs are disabled when the
guest is exited, but this is now done in C, similarly to Book3S HV.
[ I don't have
Use existing 64s interrupt entry wrapper code to reconcile irqs in C.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/interrupt.h | 7 ++---
arch/powerpc/kernel/entry_64.S | 18 ++--
arch/powerpc/kernel/exceptions-64e.S | 42 +---
3 files
Update the new C and asm interrupt return code to account for some 64e
quirks, switch over to use it, and delete the old cruft that was moved
to 64e-only after 64s was converted.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/asm-prototypes.h | 2 -
arch/powerpc/kernel/entry_64.S
In order to use the C interrupt return, nvgprs must always be saved.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/ptrace.h| 9 +
arch/powerpc/kernel/entry_64.S | 13 -
arch/powerpc/kernel/exceptions-64e.S | 27 +++
3 files
user_exit_irqoff() -> __context_tracking_exit -> vtime_user_exit
warns in __seqprop_assert due to lockdep thinking preemption is enabled
because trace_hardirqs_off() has not yet been called.
Switch the order of these two calls, which matches their ordering in
interrupt_enter_prepare.
Fixes:
This bit operation was inverted and set the low bit rather than cleared
it, breaking the ability to ptrace non-volatile GPRs after exec. Fix.
Fixes: feb9df3462e68 ("powerpc/64s: Always has full regs, so remove remnant
checks")
Signed-off-by: Nicholas Piggin
---
Well this is embarrassing.
Time to finally try removing the remaining old cruft left over
from the big interrupt return rewrite in C.
This series will clash lightly with Christophe's one to switch
ppc32 over. His should go in first because it's a lot bigger
and more mature at this stage. I will rebase this series on top
of
This bit operation was inverted and set the low bit rather than cleared
it, breaking the ability to ptrace non-volatile GPRs after exec. Fix.
Fixes: feb9df3462e68 ("powerpc/64s: Always has full regs, so remove remnant
checks")
Signed-off-by: Nicholas Piggin
---
Well this is embarrassing.
Excerpts from Christophe Leroy's message of March 5, 2021 6:54 pm:
>
>
> Le 09/02/2021 à 08:49, Nicholas Piggin a écrit :
>> Excerpts from Christophe Leroy's message of February 9, 2021 4:18 pm:
>>>
>>>
>>> Le 09/02/2021 à 02:11, Nicholas Piggin a écrit :
Excerpts from Christophe Leroy's
On Mon, Mar 8, 2021 at 7:41 AM Anshuman Khandual
wrote:
>
> HAVE_ARCH_TRANSPARENT_HUGEPAGE has duplicate definitions on platforms that
> subscribe it. Drop these reduntant definitions and instead just select it
> on applicable platforms.
>
> Cc: Vineet Gupta
> Cc: Russell King
> Cc: Arnd
Excerpts from Fabiano Rosas's message of March 6, 2021 9:10 am:
> As one of the arguments of the H_ENTER_NESTED hypercall, the nested
> hypervisor (L1) prepares a structure containing the values of various
> hypervisor-privileged registers with which it wants the nested guest
> (L2) to run. Since
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