> From: Alexey Kardashevskiy
> Sent: Friday, July 29, 2022 11:50 AM
>
>
> On 29/07/2022 13:10, Tian, Kevin wrote:
> >> From: Oliver O'Halloran
> >> Sent: Friday, July 29, 2022 10:53 AM
> >>
> >> On Fri, Jul 29, 2022 at 12:21 PM Alexey Kardashevskiy
> wrote:
> >>>
> >>> *snip*
> >>>
> >>>
Linux-next (5.19.0-rc8-next-20220728) fails to build on powerpc with
following error:
ERROR: modpost: "memory_add_physaddr_to_nid" [drivers/cxl/cxl_pmem.ko]
undefined!
make[1]: *** [scripts/Makefile.modpost:128: modules-only.symvers] Error 1
The code in question was last changed by
On 29/07/2022 13:10, Tian, Kevin wrote:
From: Oliver O'Halloran
Sent: Friday, July 29, 2022 10:53 AM
On Fri, Jul 29, 2022 at 12:21 PM Alexey Kardashevskiy wrote:
*snip*
About this. If a platform has a concept of explicit DMA windows (2 or
more), is it one domain with 2 windows or 2
> From: Oliver O'Halloran
> Sent: Friday, July 29, 2022 10:53 AM
>
> On Fri, Jul 29, 2022 at 12:21 PM Alexey Kardashevskiy wrote:
> >
> > *snip*
> >
> > About this. If a platform has a concept of explicit DMA windows (2 or
> > more), is it one domain with 2 windows or 2 domains with one window
On Fri, Jul 29, 2022 at 12:21 PM Alexey Kardashevskiy wrote:
>
> *snip*
>
> About this. If a platform has a concept of explicit DMA windows (2 or
> more), is it one domain with 2 windows or 2 domains with one window each?
>
> If it is 2 windows, iommu_domain_ops misses windows manipulation
>
On 08/07/2022 17:32, Tian, Kevin wrote:
From: Alexey Kardashevskiy
Sent: Friday, July 8, 2022 2:35 PM
On 7/8/22 15:00, Alexey Kardashevskiy wrote:
On 7/8/22 01:10, Jason Gunthorpe wrote:
On Thu, Jul 07, 2022 at 11:55:52PM +1000, Alexey Kardashevskiy wrote:
Historically PPC64 managed to
On Fri, Jul 22, 2022 at 12:04 AM Sachin Sant wrote:
>
> next-20220721 build fails on IBM Power server with following error:
>
> libbpf.c: In function 'bpf_program__attach_ksyscall':
> libbpf.c:10130:45: error: '%s' directive argument is null
> [-Werror=format-truncation=]
>
successfully.
More configs may be tested in the coming days.
gcc tested configs:
um i386_defconfig
um x86_64_defconfig
arc randconfig-r043-20220728
riscvrandconfig-r042-20220728
s390 randconfig-r044
On Mon, Jul 25, 2022 at 12:43:06PM -0700, Michel Lespinasse wrote:
> On Wed, Jun 08, 2022 at 04:27:27PM +0200, Peter Zijlstra wrote:
> > Commit c227233ad64c ("intel_idle: enable interrupts before C1 on
> > Xeons") wrecked intel_idle in two ways:
> >
> > - must not have tracing in idle functions
Reviewed-by: Greg Joyce
Tested-by: Greg Joyce
On Sat, 2022-07-23 at 07:30 -0400, Nayna Jain wrote:
> PowerVM provides an isolated Platform Keystore(PKS) storage
> allocation
> for each LPAR with individually managed access controls to store
> sensitive information securely. It provides a new
commit 6320e693d98c ("powerpc/perf: Add support for caps
under sysfs in powerpc") added support for caps under sysfs
in powerpc. This added caps directory to:
/sys/bus/event_source/devices/cpu/ for power8, power9, power10
and generic compat PMU in respective PMU driver code.
For power10, it is
Bagas Sanjaya writes:
> Sphinx reported duplicate label warning:
>
> WARNING: duplicate label elf_hwcaps_index, other instance in
> Documentation/arm64/elf_hwcaps.rst
>
> The warning is caused by elf_hwcaps_index label name is already used for
> arm64 documentation, whileas powerpc use the same
Hello,
On Thu, Jul 28, 2022 at 09:13:59PM +1000, Michael Ellerman wrote:
> Thomas Zimmermann writes:
> > (was: drm: Add driverof PowerPC OF displays)
> >
> > PowerPC's Open Firmware offers a simple display buffer for graphics
> > output. Add ofdrm, a DRM driver for the device. As with the
Thomas Zimmermann writes:
> (was: drm: Add driverof PowerPC OF displays)
>
> PowerPC's Open Firmware offers a simple display buffer for graphics
> output. Add ofdrm, a DRM driver for the device. As with the existing
> simpledrm driver, the graphics hardware is pre-initialized by the
> firmware.
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
merge
branch HEAD: 7485dc1511cd16711cec686bd3ebfd80d327a9f6 powerpc/ci: Clang 44x
build is broken
elapsed time: 1161m
configs tested: 57
configs skipped: 2
The following configs have been built successfully.
More
Bagas Sanjaya writes:
> After merging powerpc tree for linux-next integration testing, Stephen
> Rothwell reported htmldocs warnings at [1]. Fix these with self-explanatory
> fixes in the shortlog below.
>
> [1]:
> https://lore.kernel.org/linuxppc-dev/20220727220050.549db...@canb.auug.org.au/
>
On Fri, Jul 15, 2022 at 12:01:36PM -0400, Stefan Berger wrote:
>
>
> On 7/10/22 23:04, Jarkko Sakkinen wrote:
> > On Wed, Jul 06, 2022 at 11:23:27AM -0400, Stefan Berger wrote:
> > > Simplify tpm_read_log_of() by moving reusable parts of the code into
> > > an inline function that makes it
Finding the owner or a queued waiter on a lock with a preempted vcpu
is indicative of an oversubscribed guest causing the lock to get into
trouble. Provide some options to detect this situation and have new
CPUs avoid queueing for a longer time (more steal iterations) to
minimise the problems
Provide an option that holds off queueing indefinitely while the lock
owner is preempted. This could reduce queueing latencies for very
overcommitted vcpu situations.
This is disabled by default.
---
arch/powerpc/lib/qspinlock.c | 91 +++-
1 file changed, 79
Allow for a reduction in the number of times a CPU from a different
node than the owner can attempt to steal the lock before queueing.
This could bias the transfer behaviour of the lock across the
machine and reduce NUMA crossings.
---
arch/powerpc/lib/qspinlock.c | 34
Use the spin_begin/spin_cpu_relax/spin_end APIs in qspinlock, which helps
to prevent threads issuing a lot of expensive priority nops which may not
have much effect due to immediately executing low then medium priority.
---
arch/powerpc/lib/qspinlock.c | 35 +++
1
This gives trylock slightly more strength, and it also gives most
of the benefit of passing 'val' back through the slowpath without
the complexity.
---
arch/powerpc/include/asm/qspinlock.h | 39 +++-
arch/powerpc/lib/qspinlock.c | 9 +++
2 files changed, 47
After the head of the queue acquires the lock, it releases the
next waiter in the queue to become the new head. Add an option
to prod the new head if its vCPU was preempted. This may only
have an effect if queue waiters are yielding.
Disable this option by default for now, i.e., no logical
Having all CPUs poll the lock word for the owner CPU that should be
yielded to defeats most of the purpose of using MCS queueing for
scalability. Yet it may be desirable for queued waiters to to yield
to a preempted owner.
s390 addreses this problem by having queued waiters sample the lock
word
If the head of queue is preventing stealing but it finds the owner vCPU
is preempted, it will yield its cycles to the owner which could cause it
to become preempted. Add an option to re-allow stealers before yielding,
and disallow them again after returning from the yield.
Disable this option by
Queued waiters which are not at the head of the queue don't spin on
the lock word but their qnode lock word, waiting for the previous queued
CPU to release them. Add an option which allows these waiters to yield
to the previous CPU if its vCPU is preempted.
Disable this option by default for now,
Waiters spinning on the lock word should yield to the lock owner if the
vCPU is preempted. This improves performance when the hypervisor has
oversubscribed physical CPUs.
---
arch/powerpc/lib/qspinlock.c | 97 ++--
1 file changed, 83 insertions(+), 14 deletions(-)
Store the owner CPU number in the lock word so it may be yielded to,
as powerpc's paravirtualised simple spinlocks do.
---
arch/powerpc/include/asm/qspinlock.h | 8 +++-
arch/powerpc/include/asm/qspinlock_types.h | 10 ++
arch/powerpc/lib/qspinlock.c | 6 +++---
Give the queue head the ability to stop stealers. After a number of
spins without sucessfully acquiring the lock, the queue head employs
this, which will assure it is the next owner.
---
arch/powerpc/include/asm/qspinlock_types.h | 10 +++-
arch/powerpc/lib/qspinlock.c | 56
Allow new waiters a number of spins on the lock word before queueing,
which particularly helps paravirt performance when physical CPUs are
oversubscribed.
---
arch/powerpc/lib/qspinlock.c | 152 ---
1 file changed, 141 insertions(+), 11 deletions(-)
diff --git
This uses more optimal ll/sc style access patterns (rather than
cmpxchg), and also sets the EH=1 lock hint on those operations
which acquire ownership of the lock.
---
arch/powerpc/include/asm/qspinlock.h | 25 +--
arch/powerpc/include/asm/qspinlock_types.h | 6 +-
The first 16 bits of the lock are only modified by the owner, and other
modifications always use atomic operations on the entire 32 bits, so
unlocks can use plain stores on the 16 bits. This is the same kind of
optimisation done by core qspinlock code.
---
arch/powerpc/include/asm/qspinlock.h
This forms the basis of the qspinlock slow path.
Like generic qspinlocks and unlike the vanilla MCS algorithm, the lock
owner does not participate in the queue, only waiters. The first waiter
spins on the lock word, then when the lock is released it takes
ownership and unqueues the next waiter.
I have a bunch of parallel patches that clean up the generic queued
spinlock code, but the powerpc implementation does not use or depend
on any of that except patch collision. I've based the powerpc series
on top of that work, but it's annoying to post or carry around all
those patches as well.
Add a powerpc specific implementation of queued spinlocks. This is the
build framework with a very simple (non-queued) spinlock implementation
to begin with. Later changes add queueing, and other features and
optimisations one-at-a-time. It is done this way to more easily see how
the queued
This replaces the generic queued spinlock code (like s390 does) with
our own implementation. There is an extra shim patch 1a here to get the
series to apply.
So far the microbenchmarks look okay, haven't really had time to write
up a good set of results. I hope to get some significant bigger
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