On Wed, 2017-06-28 at 08:21 +0530, Aneesh Kumar K.V wrote:
>
>
> I am not sure the new location of flushing the tlb is correct/perfect. For ex:
> may be we should do it before htab_initialize() so that we start with
> all everything flushed ? But otherwise
Doesn't matter as long as you do it bef
On Mon, 2017-06-26 at 09:03 +1000, Balbir Singh wrote:
> On Wed, 2017-06-21 at 18:39 -0700, Ram Pai wrote:
> > Introduce set_hidx_slot() which sets the (H_PAGE_F_SECOND|H_PAGE_F_GIX)
> > bits at the appropriate location in the PTE of 4K PTE. In the
> > case of 64K PTE, it sets the bits in
chael Neuling
Signed-off-by: Benjamin Herrenschmidt
diff --git a/arch/powerpc/mm/mmu_context_book3s64.c
b/arch/powerpc/mm/mmu_context_book3s64.c
index a3edf813d4..71de2c6d88 100644
--- a/arch/powerpc/mm/mmu_context_book3s64.c
+++ b/arch/powerpc/mm/mmu_context_book3s64.c
@@ -235,10 +235,15 @@
That will allow OPAL to configure the CPU in an optimal way.
Signed-off-by: Benjamin Herrenschmidt
---
The matching OPAL change has been sent to the skiboot list.
Setting those bits in the reinit() call with an older OPAL
will result in the call returning an error which Linux ignores
but it
There is no reason for that message to be pr_info(), it will be printed
every time we start a KVM guest.
Signed-off-by: Benjamin Herrenschmidt
---
diff --git a/arch/powerpc/sysdev/xive/native.c
b/arch/powerpc/sysdev/xive/native.c
index ab9ecce..0f95476b 100644
--- a/arch/powerpc/sysdev/xive
Signed-off-by: Benjamin Herrenschmidt
---
v2. [BenH] Move to a place before we branch off to KVM if the
core was in a guest. Also add a comment about the
SRR1 bit extraction.
---
arch/powerpc/kernel/exceptions-64s.S | 4 +++-
arch/powerpc/kernel/idle_book3s.S| 7
On Sat, 2017-06-24 at 09:18 +0200, Christoph Hellwig wrote:
> On Wed, Jun 21, 2017 at 12:24:28PM -0700, tndave wrote:
> > Thanks for doing this.
> > So archs can still have their own definition for dma_set_mask() if
> > HAVE_ARCH_DMA_SET_MASK is y?
> > (and similarly for dma_set_coherent_mask() wh
On Fri, 2017-06-23 at 19:33 +1000, Michael Ellerman wrote:
> Michael Neuling writes:
>
> > On POWER9 the ERAT may be incorrect on wakeup from some stop states
> > that lose state. This causes random segvs and illegal instructions
> > when these stop states are enabled.
>
> Incorrect how?
As in
On Thu, 2017-06-22 at 11:29 +0200, Cédric Le Goater wrote:
> This is the framework for using XIVE in a PowerVM guest. The support
> is very similar to the native one in a much simpler form.
Looks really good. Minor nits & comments...
> Instead of OPAL calls, a set of Hypervisors call are used to
On Wed, 2017-06-21 at 20:33 +1000, Michael Ellerman wrote:
> victora writes:
>
> > Hi Alistair/Jeremy,
> >
> > I am working on a bug related to 1M hugepage size being registered on
> > Linux (Power 8 Baremetal - Garrison).
>
> Wasn't that caused by a firmware bug?
>
> > I was checking dmesg a
On Thu, 2017-06-22 at 13:59 +1000, Michael Ellerman wrote:
> It's unsupported in Linux because it doesn't match the page table
> geometry.
>
> We merged a patch from Aneesh to filter it out in 4.12-rc1:
>
> a525108cf1cc ("powerpc/mm/hugetlb: Filter out hugepage size not supported
> by page tab
On Tue, 2017-06-20 at 14:17 -0700, Thomas Besemer wrote:
> I'm working on a project that is derived from the Yosemite
> PPC 440EP board. It's a legacy project that was running the
> 2.6.24 Kernel, and network traffic was stalling due to transmission
> halting without an understandable error (in th
On Tue, 2017-06-20 at 15:10 +1000, Balbir Singh wrote:
> On Fri, 2017-06-16 at 20:52 -0700, Ram Pai wrote:
> > Memory protection keys enable applications to protect its
> > address space from inadvertent access or corruption from
> > itself.
>
> I presume by itself you mean protection between thre
On Sun, 2017-06-18 at 00:13 -0700, Christoph Hellwig wrote:
> On Sun, Jun 18, 2017 at 06:50:27AM +1000, Benjamin Herrenschmidt wrote:
> > What is your rationale here ? (I have missed patch 0 it seems).
>
> Less code duplication, more modular dma_map_ops insteance.
>
>
On Fri, 2017-06-16 at 20:10 +0200, Christoph Hellwig wrote:
> Besides removing the last instance of the set_dma_mask method this also
> reduced the code duplication.
What is your rationale here ? (I have missed patch 0 it seems).
dma_supported() was supposed to be pretty much a "const" function
s
On Fri, 2017-06-16 at 12:15 -0700, Ram Pai wrote:
> gp_regs size is not changed, nor is the layout. A unused field in
> the gp_regs is used to fill in the AMR contents. Old binaries will not
> be knowing about this unused field, and hence should not break.
>
> New binaries can leverage this alread
On Fri, 2017-06-16 at 14:50 +0530, Anshuman Khandual wrote:
> On 06/06/2017 06:35 AM, Ram Pai wrote:
> > The value of the AMR register at the time of the exception
> > is made available in gp_regs[PT_AMR] of the siginfo.
>
> But its already available there in uctxt->uc_mcontext.regs->amr
> while i
On Thu, 2017-06-15 at 17:06 +, Rowand, Frank wrote:
> On Thursday, June 15, 2017 2:25 AM, Abdul Haleem
> [mailto:abdha...@linux.vnet.ibm.com] wrote:
> >
> > On Thu, 2017-06-15 at 11:30 +0530, Abdul Haleem wrote:
> > > Hi,
> > >
> > > linux-next fails to boot on powerpc Bare-metal with these
On Thu, 2017-06-15 at 19:25 +1000, Michael Ellerman wrote:
> Alexey Kardashevskiy writes:
>
> > From: Yongji Xie
> >
> > Any IODA host bridge have the capability of IRQ remapping.
> > So we set PCI_BUS_FLAGS_MSI_REMAP when this kind of host birdge
> > is detected.
>
> Where's the code that act
On Thu, 2017-06-15 at 16:28 +1000, Michael Ellerman wrote:
> This reverts commit 45cb08f4791ce6a15c54598b4cb73db4b4b8294f.
>
> For some reason this is causing IRQ problems on Freescale Book3E
> machines, eg on my p5020ds:
This looks like a driver bug it could be that you get hammered by
an in
On Wed, 2017-06-14 at 14:44 +1000, Michael Ellerman wrote:
> Benjamin Herrenschmidt writes:
>
> > Architecturally we should apply a 0x400 offset for these. Not doing
> > it will break future HW implementations.
>
> Can you elaborate a bit?
>
> You're chang
Architecturally we should apply a 0x400 offset for these. Not doing
it will break future HW implementations.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/xive.h | 12 +++-
arch/powerpc/kvm/book3s_xive_template.c | 4 ++--
arch/powerpc/sysdev/xive/common.c
On Tue, 2017-06-13 at 20:04 +1000, Michael Ellerman wrote:
> > Good idea. Writing to CTRL register can change only the RUN field.
> > Was this any different in older generations?
>
> No AFAICS back to 2.02.
>
> > Anton and Ben kept the mfspr/mtspr part in earlier updates to this
> > routine.
>
On Sun, 2017-06-11 at 19:30 +1000, Nicholas Piggin wrote:
> I rebased this on the powerpc next tree.
>
> A couple of things are changed since last post:
>
> - Patch 1 now properly accounts for the fact the powernv idle
> wakeups do not re-enable interrupts until the cpuidle driver
> enables t
On Wed, 2017-06-07 at 07:45 +0200, Greg Kroah-Hartman wrote:
> On Wed, Jun 07, 2017 at 09:04:41AM +1000, Benjamin Herrenschmidt wrote:
> > On Tue, 2017-06-06 at 21:30 +0200, Greg Kroah-Hartman wrote:
> > > >
> > > > static struct device_attribute vio_dev_att
On Tue, 2017-06-06 at 21:30 +0200, Greg Kroah-Hartman wrote:
> >
> > static struct device_attribute vio_dev_attrs[] = {
> > __ATTR_RO(name),
> > @@ -1573,6 +1576,13 @@ static struct device_attribute vio_dev_attrs[] = {
> > __ATTR_RO(modalias),
> > __ATTR_NULL
> > };
> >
On Mon, 2017-06-05 at 20:21 +1000, Michael Ellerman wrote:
> On Thu, 2017-03-16 at 08:55:45 UTC, Christophe Leroy wrote:
> > It often happens to have simultaneous interrupts, for instance
> > when having double Ethernet attachment. With the current
> > implementation, we suffer the cost of kernel e
On Fri, 2017-06-02 at 14:39 +0200, Geert Uytterhoeven wrote:
>
> > diff --git a/arch/powerpc/platforms/powernv/opal-irqchip.c
> > b/arch/powerpc/platforms/powernv/opal-irqchip.c
> > index 998316bf2dad..ecdcba9d1220 100644
> > --- a/arch/powerpc/platforms/powernv/opal-irqchip.c
> > +++ b/arch/powe
On Fri, 2017-06-02 at 11:39 +0200, Christophe LEROY wrote:
> The difference between get_user() and __get_user() is that get_user()
> performs an access_ok() in addition.
>
> Doesn't access_ok() only checks whether addr is below TASK_SIZE to
> ensure it is a valid user address ?
Do you have a me
On Tue, 2017-05-30 at 15:58 +0200, Frederic Barrat wrote:
> P9 has support for PCI peer-to-peer, enabling a device to write in the
> mmio space of another device directly, without interrupting the CPU.
>
> This patch adds support for it on powernv, by defining two APIs to
> declare a pci_dev as ei
On Mon, 2017-05-29 at 20:02 +0530, Aneesh Kumar K.V wrote:
> kvmppc_do_h_enter() when get called in real mode.
>
> For now i have dropped hard_irq_disabled() and switched these usage to
> __find_linux_pte with explict comment around them stating they are
> called with MSR_EE = 0.
Shouldn't these
gt; decided to split this out from the core ISA 3 feature as well.
>
> Signed-off-by: Nicholas Piggin
Acked-by: Benjamin Herrenschmidt
> ---
> These uapi changes have been agreed by powerpc toolchain and firmware
> teams. I believe this completes our anticipated requirements for us
On Mon, 2017-05-22 at 00:00 +1000, Nicholas Piggin wrote:
> I'd like to take over the r14 register for use as a per-cpu kernel
> register similar to the way r13 is used for the paca.
Why not use r13 instead ? We don't need to access the PACA that often
from C code, I thought we could flip them...
On Mon, 2017-05-15 at 16:07 +0300, Ivan Mikhaylov wrote:
> +#ifdef CONFIG_FSP2
> + /*
> + * Prevent a kernel panic caused by unintentionally clearing TCR
> + * watchdog bits. At this point in the kernel boot, the watchdog has
> + * already been enabled by u-boot. The or
On Wed, 2017-05-17 at 08:57 +0530, Aneesh Kumar K.V wrote:
> Benjamin Herrenschmidt writes:
>
> > On Tue, 2017-05-16 at 14:56 +0530, Aneesh Kumar K.V wrote:
> > > +static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea,
> > > +
On Fri, 2017-05-12 at 13:37 -0400, David Miller wrote:
> > Right now it is larger, but what I suggested is to add a new optimized
> > routine just for this case, which would do STBI for 64-bytes but
> > without membar (do membar at the end of memmap_init_zone() and
> > deferred_init_memmap()
> >
>
On Tue, 2017-05-16 at 14:56 +0530, Aneesh Kumar K.V wrote:
> +static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea,
> + bool *is_thp, unsigned *hshift)
> +{
> + VM_WARN((!arch_irqs_disabled() && !__hard_irqs_disabled()) ,
> + "%s c
On Tue, 2017-05-16 at 14:56 +0530, Aneesh Kumar K.V wrote:
>
> +static inline bool __hard_irqs_disabled(void)
> +{
> + unsigned long flags = mfmsr();
> + return (flags & MSR_EE) == 0;
> +}
> +
Reading the MSR has a cost. Can't we rely on paca->irq_happened being
non-0 ?
(If you are
On Sat, 2017-05-06 at 01:50 +0300, Alexey Khoroshilov wrote:
> Could you please clarify if iounmap(NULL) safe or not.
> I guess it would be less errorprone if the answer is architecture independent.
I think it's supposed to be and we should fix ppc.
Cheers,
Ben.
On Fri, 2017-05-05 at 15:52 +0200, Michal Suchánek wrote:
>
> So you have an e-mail message from one of the authors of the code.
> Andy Polyakov wrote most of the code but there are probably other
> contributors who never gave explicit consent for using their code
> outside of OpenSSL.
The only c
On Wed, 2017-05-03 at 20:26 +1000, Michael Ellerman wrote:
> Couldn't we avoid the whole problem by just having two bolted slots for
> the stack, meaning we could have the current and next stack bolted at
> all times.
>
> That would mean we'd be using 4 slots for bolted entries, which is one
> mor
On Wed, 2017-05-03 at 17:34 +1000, Nicholas Piggin wrote:
> Extending the soft IRQ disable to cover PMU interrupts will allow this
> hard disable to be removed from hash based kernels too, but they will
> still have to soft-disable PMU interrupts.
>
> - Q1: Can we do this? It gives nice profiles o
On Fri, 2017-04-28 at 16:34 +1000, Michael Ellerman wrote:
> > > If there's non-verbose debug that we think would be useful to
> > > differentiate from verbose then those could be pr_debug() - which means
> > > they'll be jump labelled off in most production kernels, but still able
> > > to be enab
On Fri, 2017-04-28 at 13:07 +1000, Michael Ellerman wrote:
> Benjamin Herrenschmidt writes:
>
> > The existing verbose debug code doesn't build when enabled.
>
> So why don't we convert all the DBG_VERBOSE() to pr_devel()?
pr_devel provides a bunch of debug a
The existing verbose debug code doesn't build when enabled.
This fixes it and generally improves the output to make it
more useful.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/sysdev/xive/common.c | 37 ++---
1 file changed, 26 insertions(+
On Mon, 2017-04-24 at 10:25 -0700, Sukadev Bhattiprolu wrote:
> which maybe due to this :-) Should I change to pgprot_noncached() for
> the MMIO writes?
Just use normal ioremap().
> > requires being mapped cachable. Ask Aneesh for a cleaner way of
> > doing it too while at it.
On Thu, 2017-03-30 at 22:13 -0700, Sukadev Bhattiprolu wrote:
> +static void *map_mmio_region(char *name, uint64_t start, int len)
> +{
> + void *map;
> +
> + if (!request_mem_region(start, len, name)) {
> + pr_devel("%s(): request_mem_region(0x%llx, %d) failed\n",
> +
On Thu, 2017-03-30 at 22:13 -0700, Sukadev Bhattiprolu wrote:
>
> + p = of_get_property(dn, "vas-id", NULL);
> + if (!p) {
> + pr_err("VAS: NULL vas-id? %p\n", p);
> + return -ENODEV;
> + }
> +
> + vinst->vas_id = of_read_number(p, 1);
of_property_read_u32(
On Thu, 2017-03-30 at 22:13 -0700, Sukadev Bhattiprolu wrote:
> +config VAS
> + tristate "IBM Virtual Accelerator Switchboard (VAS)"
CONFIG_IBM_VAS or PPC_VAS ... too high risk of collision otherwise
Ben.
On Mon, 2017-04-24 at 14:55 +1000, Nicholas Piggin wrote:
> On Mon, 24 Apr 2017 11:47:48 +1000
> > Benjamin Herrenschmidt wrote:
>
> > On Thu, 2017-03-30 at 22:10 +1000, Nicholas Piggin wrote:
> > > There are some windows in opal entry/exit that can not recover from a
On Thu, 2017-03-30 at 22:10 +1000, Nicholas Piggin wrote:
> There are some windows in opal entry/exit that can not recover from a
> re-entrant interrupt (e.g., machine check) due to using SRR registers,
> but they currently do not have MSR_RI clear.
>
> These were found by machine check injection
On Sun, 2017-04-23 at 19:57 +1000, Nicholas Piggin wrote:
> On Sun, 23 Apr 2017 10:39:11 +1000
> Benjamin Herrenschmidt wrote:
>
> > On Sun, 2017-04-23 at 09:14 +1000, Nicholas Piggin wrote:
> > > I think we were going to take another look at moving the setup
> > &
On Sun, 2017-04-23 at 09:14 +1000, Nicholas Piggin wrote:
> I think we were going to take another look at moving the setup code
> later, but I think that might wait until 4.13.
Except without that we won't boot a post-P9 CPU right ? So we'll end up
having to chase distros to backport it :-( Oh wel
On Sat, 2017-04-22 at 10:58 +1000, Nicholas Piggin wrote:
> +static void __init init_mmu_tlb_sets_hash(unsigned long node)
> +{
> + const __be32 *ptr;
> +
> + ptr = of_get_flat_dt_prop(node, "ibm,tlbiel-congruence-classes-hash",
> NULL);
> + if (ptr)
> + cur_cpu_spe
On Thu, 2017-04-20 at 04:20 +0300, Dan Carpenter wrote:
> Hello Benjamin Herrenschmidt,
>
> The patch 243e25112d06: "powerpc/xive: Native exploitation of the
> XIVE interrupt controller" from Apr 5, 2017, leads to the following
> static checker warning:
>
>
On Sat, 2017-04-15 at 11:36 -0500, Bjorn Helgaas wrote:
> > I agree in principle. I'm surprised that PowerPC is the only one
> > interested here though, what about other platforms who want to use
> > KVM and PCI pass-through and use Linux to assign BARs ?
>
> If I understand correctly, the problem
On Fri, 2017-04-14 at 10:58 -0500, Bjorn Helgaas wrote:
> On Mon, Apr 10, 2017 at 07:58:13PM +0800, Yongji Xie wrote:
> > This overrides pcibios_default_alignment() to set default alignment
> > to PAGE_SIZE for all PCI devices on PowerNV platform. Thus sub-page
> > BARs would not share a page and c
On Thu, 2017-04-13 at 09:28 +0530, Aneesh Kumar K.V wrote:
> > #endif
> > mtctr r12
> > bctrl
> > +/*
> > + * cur_cpu_spec->cpu_restore would restore LPCR to a
> > + * sane value that is set at early boot time,
> > + * thereby clearing LPCR_UPRT.
> > + * LPCR_UPRT is required if w
On Thu, 2017-04-13 at 00:12 +1000, Nicholas Piggin wrote:
> Yeah sure that sounds good. How's this then?
I suppose so :-) When I was testing all that I had a "b ." at 0x500 and
0x4500 and I didn't hit them :)
On Wed, 2017-04-12 at 01:42 -0700, IanJiang wrote:
>
> In my test, DMA buffers are allocated with (bus 2, device 1, function
> 0) in module Plx8000_NT, but DMA is issued by (bus 1 device 0 function
> 1) in module Plx8000_DMA. And error of (bus 1 device 0 function 1) is
> reported by EEH.
Thi
On Wed, 2017-04-12 at 23:11 +1000, Nicholas Piggin wrote:
> After setting LPES0 in the host on POWER9, the host external interrupt
> handler no longer works correctly, because it's set to HV mode (HSRR)
> for POWER7/8 with LPES0 clear. We don't expect to get any EE in the host
> with XIVE, but it s
On Tue, 2017-04-11 at 18:39 -0700, IanJiang wrote:
> On Tue, Apr 11, 2017 at 5:37 PM, Benjamin Herrenschmidt [via
> linuxppc]
> wrote:
>
> > Another possibility would be if the requests from the PLX have a
> > different initiator ID on the bus than the device you are set
On Tue, 2017-04-11 at 02:26 -0700, IanJiang wrote:
> I did another test:
> - Call dma_set_mask_and_coherent(&pPciDev->dev, DMA_BIT_MASK(32)) in
> probe;
> - Use DMA address or BUS address in DMA
> But EHH error remains.
We need to dig out the details of the EEH error. It will tell us
more precisel
On Tue, 2017-04-11 at 12:08 +0900, Minchan Kim wrote:
> Hello,
>
> When I tested zram in ppc64, I got random corruption.
> With investigation, it seems clear_page corrupted the memory.
> I passed 64K kmalloced(kmalloc(PAGE_SIZE)) address to clear_page
> and turned on slub debug so address is not a
On Mon, 2017-04-10 at 19:04 -0700, IanJiang wrote:
> Thanks for your replay.
>
> I fixed my test according your suggestion. The CPU physical addresses (0x
> 1f9e40 and 0x 1f82c0) converted with virt_to_phys() are used ,
> instead of DMA addresses, or BUS physical addresses (0x 60a0 and
When targetting interrupts we do various manipulations of cpu numbers
and CPU masks. This adds some sanity checking to ensure we don't
break assumptions and manpulate cpu numbers that are out of bounds
of the various cpumasks.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/sysdev
: Benjamin Herrenschmidt
---
arch/powerpc/sysdev/xive/common.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/common.c
b/arch/powerpc/sysdev/xive/common.c
index dbd0f45..f37d257 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc
If the interrupt didn't have a selected target yet, we could
call cpu_online() and do other cpumask tests with cpu #-1 which
would result in random outcomes.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/sysdev/xive/common.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
: Benjamin Herrenschmidt
---
arch/powerpc/sysdev/xive/common.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/common.c
b/arch/powerpc/sysdev/xive/common.c
index dbbe446..abda9b2 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc
When targetting interrupts we do various manipulations of cpu numbers
and CPU masks. This adds some sanity checking to ensure we don't
break assumptions and manpulate cpu numbers that are out of bounds
of the various cpumasks.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/sysdev
If the interrupt didn't have a selected target yet, we could
call cpu_online() and do other cpumask tests with cpu #-1 which
would result in random outcomes.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/sysdev/xive/common.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
On Mon, 2017-04-10 at 13:22 +1000, Nicholas Piggin wrote:
> On Sun, 09 Apr 2017 18:03:35 +1000
> > Benjamin Herrenschmidt wrote:
>
> > On Fri, 2017-04-07 at 22:55 +1000, Nicholas Piggin wrote:
> > > POWER9 hypervisors will not necessarily run guest threads together on
On Fri, 2017-04-07 at 22:55 +1000, Nicholas Piggin wrote:
> POWER9 hypervisors will not necessarily run guest threads together on
> the same core at the same time, so msgsndp should not be used.
Maybe we shouldn't advertise doorbells at all ?
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerp
Signed-off-by: Benjamin Herrenschmidt
---
That should have been the first patch in the XIVE series...
arch/powerpc/include/asm/opal-api.h| 74 +-
arch/powerpc/include/asm/opal.h| 36 +
arch/powerpc/platforms/powernv/opal
ops, I was 1 patch off in my git send-email, forgetting the
opal-api.h updates. I'm sending the pre-req patch separately.
Cheers,
Ben.
> url:https://github.com/0day-ci/linux/commits/Benjamin-
> Herrenschmidt/powerpc-Add-more-PPC-bit-conversion-macros/20170406-
> 041935
> bas
On Wed, 2017-04-05 at 10:58 -0500, Rob Herring wrote:
> Well, I'd like to avoid expanding usage of flat DT parsing in the
> kernel. But you could just put this function into arch/powerpc and I'd
> never see it, but I like that even less. Mainly, I just wanted to
> raise the point.
>
> Your argumen
no
longer available when the XIVE is used natively by Linux.
A latter patch will make KVM also directly exploit the XIVE, thus
recovering the lost performance (and more).
Signed-off-by: Benjamin Herrenschmidt
--
v2: - Add comments, rename a few things, move some around, based
on review comments
e.
Signed-off-by: Benjamin Herrenschmidt
--
v2. Address review comments
# Conflicts:
# arch/powerpc/sysdev/xive/common.c
# arch/powerpc/sysdev/xive/native.c
# Conflicts:
# arch/powerpc/sysdev/xive/common.c
---
arch/powerpc/include/asm/kvm_book3s_asm.h |2 +
arch/powerpc/i
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/smp.h | 1 -
arch/powerpc/kernel/irq.c | 40
arch/powerpc/kernel/smp.c | 9 -
4 files changed, 9 insertions(+), 42 deletions(-)
di
The function doesn't exist anymore
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/kvm_ppc.h | 4
1 file changed, 4 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_ppc.h
b/arch/powerpc/include/asm/kvm_ppc.h
index bfef1ae..0c41865 100644
--- a/arch/po
ding __raw variants. Any code using these is already
pretty much hand tuned to operate in a very specific environment.
I've fixed up the 2 users (only one of them actually needed
a barrier in the first place).
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/io.h
We traditionally have linux/ before asm/
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/kvm/book3s.c| 8
arch/powerpc/kvm/book3s_hv.c | 18 +-
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm
host external interrupts come in via the new
hypervisor virtualization interrupts vector.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/reg.h| 1 +
arch/powerpc/kernel/cpu_setup_power.S | 15 ++-
2 files changed, 11 insertions(+), 5 deletions(-)
diff --
It's only used within the same file it's defined
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/kvm_ppc.h | 4
arch/powerpc/kvm/book3s_xics.c | 2 +-
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_ppc.h
b/ar
ong others
Instead, add a new callback that is called from __cpu_up (so from
the context trying to online the new CPU) at a point where we
can safely allocate and handle failures.
This will be used by XIVE support.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/smp.h | 1 +
a
Add 32 and 8 bit variants
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/bitops.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/include/asm/bitops.h
b/arch/powerpc/include/asm/bitops.h
index bc5fdfd..33a24fd 100644
--- a/arch/powerpc/include/asm
On Tue, 2017-04-04 at 23:03 +1000, Michael Ellerman wrote:
>
> > 14 files changed, 2186 insertions(+), 12 deletions(-)
>
> I'm not going to review this in one go, given it's 10:30pm already.
Well, good, I was about to send (well tomorrow morning actually) v2
hoping it was going to be final sinc
On Tue, 2017-04-04 at 22:20 +1000, Michael Ellerman wrote:
> Benjamin Herrenschmidt writes:
>
> ...
>
> Give me some change log !
Well, the subject says it all :-) Sync the API with the latest OPAL :-)
> > Signed-off-by: Benjamin Herrenschmidt
> > ---
> > ar
On Mon, 2017-04-03 at 23:29 +1000, Michael Ellerman wrote:
> The other option would be just to make a rule that anything EXPORT'ed
> must use _GLOBAL_TOC().
Can we enforce that somewhat at build time ?
Cheers,
Ben.
On Tue, 2017-03-28 at 16:26 +1100, Paul Mackerras wrote:
>
> > --- a/arch/powerpc/include/asm/kvm_book3s_asm.h
> > +++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
> > @@ -111,6 +111,8 @@ struct kvmppc_host_state {
> > struct kvm_vcpu *kvm_vcpu;
> > struct kvmppc_vcore *kvm_vcore;
> > v
On Mon, 2017-04-03 at 10:54 +1000, Anton Blanchard wrote:
> > > Good idea, I hadn't thought of embedding it all in a feature
> > > section.
> >
> > It may not work currently because you get those ftr_alt_97 relocation
> > errors with the "else" parts because relative branches to other code
> > n
On Wed, 2017-03-29 at 23:29 +0200, Arnd Bergmann wrote:
> Why not move the mac_hid module to drivers/input instead so
> it no longer depends on MACINTOSH_DRIVERS?
>
> For the other mac drivers, it may be helpful to to add '||
> COMPILE_TEST'
> to the dependency line here to allow building them on
On Mon, 2017-03-27 at 21:17 +1100, Michael Ellerman wrote:
> > If so, is it acceptable to force that kernel to user 64K alignment
> > even
> > when it's running on non-PowerNV systems?
>
> Probably, but I'm not sure TBH. Benh will know, I'll try and get his
> attention.
Can we make the alignment
On Tue, 2017-03-21 at 06:29 -0700, Matthew Wilcox wrote:
>
> Well, those are the generic versions in the first patch:
>
> http://git.infradead.org/users/willy/linux-dax.git/commitdiff/538b977
> 6ac925199969bd5af4e994da776d461e7
>
> so if those are good enough for you guys, there's no need for yo
On Mon, 2017-03-20 at 14:14 -0700, Matthew Wilcox wrote:
> I recently introduced memset32() / memset64(). I've done implementations
> for x86 & ARM; akpm has agreed to take the patchset through his tree.
> Do you fancy doing a powerpc version? Minchan Kim got a 7% performance
> increase with zram
no
longer available when the XIVE is used natively by Linux.
A latter patch will make KVM also directly exploit the XIVE, thus
recovering the lost performance (and more).
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/xive.h | 116 +++
arch/powerpc/include/asm/xmon.h
e.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/kvm_book3s_asm.h |2 +
arch/powerpc/include/asm/kvm_host.h | 28 +-
arch/powerpc/include/asm/kvm_ppc.h| 38 +
arch/powerpc/include/asm/xive.h | 11 +-
arch/powerpc/kernel/asm-offsets.c
host external interrupts come in via the new
hypervisor virtualization interrupts vector.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/reg.h| 1 +
arch/powerpc/kernel/cpu_setup_power.S | 15 ++-
2 files changed, 11 insertions(+), 5 deletions(-)
diff --
ding __raw variants. Any code using these is already
pretty much hand tuned to operate in a very specific environment.
I've fixed up the 2 users (only one of them actually needed
a barrier in the first place).
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/io.h
The function doesn't exist anymore
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/kvm_ppc.h | 4
1 file changed, 4 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_ppc.h
b/arch/powerpc/include/asm/kvm_ppc.h
index bfef1ae..0c41865 100644
--- a/arch/po
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