Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 13 +
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 3 +++
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.
Some CCSR registers will lost during deep sleep. Therefore,
should save them before entering deep sleep, and restore them
when resuming from deep sleep.
Signed-off-by: Tang Yuantian <yuantian.t...@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
arch/powerpc/include/
precedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
arch/powerpc/platforms/85xx/Makefile| 2 +-
arch/powerpc/platforms/85xx/sleep_fsm.c | 267
arch/powerpc/platforms/85xx/sleep_fsm.h
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 13 +
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi| 3 +++
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.
access. This piece of code and related TLBs are prefetched in advance.
Due to the different initialization code between 32-bit and 64-bit, they
have separate resume entry and precedure.
The feature supports 32-bit and 64-bit kernel mode.
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
arch/powerpc/Kconfig | 3 +-
arch/powerpc/include/asm/fsl_pm.h | 2 +-
arch/powerpc/platforms/85xx/Kconfig| 5 +++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/qoriq_
http://patchwork.ozlabs.org/patch/502548/
[4/4] powerpc: pm: support deep sleep feature on T104x
http://patchwork.ozlabs.org/patch/502550/
Chenhui Zhao (5):
powerpc/dts: add mcke-gpios for PM feature
powerpc/85xx: support sleep feature on QorIQ SoCs with RCPM
powerpc: pm: add EPU FSM
Any comment?
Thanks,
Chenhui
From: Chenhui Zhao <chenhui.z...@nxp.com>
Sent: Friday, April 15, 2016 7:13 PM
To: linuxppc-dev@lists.ozlabs.org; o...@buserror.net
Cc: Zhengxiong Jin; Chenhui Zhao
Subject: [PATCH v2 0/5] powerpc/pm: QorIQ deep
Thank you for your comment. I'll change it according to the GPIO binding
document.
Thanks,
Chenhui
From: Yang-Leo Li
Sent: Saturday, April 16, 2016 12:47 AM
To: Chenhui Zhao; linuxppc-dev@lists.ozlabs.org; o...@buserror.net
Cc: Chenhui Zhao; Zhengxiong
off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
arch/powerpc/Kconfig | 3 +-
arch/powerpc/include/asm/fsl_pm.h | 2 +-
arch/powerpc/platforms/85xx/Kconfig| 5 +++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/qoriq_
access. This piece of code and related TLBs are prefetched in advance.
Due to the different initialization code between 32-bit and 64-bit, they
have separate resume entry and precedure.
The feature supports 32-bit and 64-bit kernel mode.
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
Some CCSR registers will lost during deep sleep. Therefore,
should save them before entering deep sleep, and restore them
when resuming from deep sleep.
Signed-off-by: Tang Yuantian <yuantian.t...@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
arch/powerpc/include/
on T104x
http://patchwork.ozlabs.org/patch/502550/
Chenhui Zhao (5):
powerpc/85xx: support sleep feature on QorIQ SoCs with RCPM
powerpc: pm: add EPU FSM configuration for deep sleep
powerpc/dts: add a compatible string to gpio0
powerpc/pm: support deep sleep feature on T104x
powerpc/pm
precedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
arch/powerpc/platforms/85xx/Makefile| 2 +-
arch/powerpc/platforms/85xx/sleep_fsm.c | 267
arch/powerpc/platforms/85xx/sleep_fsm.h
For T1040, T1042, T1023, and T1024, they should use the compatible
string "fsl,qoriq-rcpm-2.1".
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 2 +-
2 files changed, 2
All gpio nodes used the same compatible string "fsl,qoriq-gpio".
To identify the node corresponding to the GPIO1 pins, add a
compatible string "fsl,qoriq-gpio-1".
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi
On e6500, in the case of cpu hotplug, either thread in one core
may be the first thread initilzing the TLB1. The subsequent threads
must not setup it again.
The code is derived from the comment of Scott Wood.
Signed-off-by: Chenhui Zhao <chenhui.z...@freescale.com>
---
Changes for v4:
*
On Wed, Dec 2, 2015 at 8:12 PM, Denis Kirjanov <k...@linux-powerpc.org>
wrote:
On 11/20/15, Chenhui Zhao <chenhui.z...@freescale.com> wrote:
On e6500, in the case of cpu hotplug, either thread in one core
may be the first thread initilzing the TLB1. The subsequent threads
mu
Hi Scott,
Any comment on these pathes?
Thanks,
Chenhui
On Fri, Nov 20, 2015 at 5:13 PM, Chenhui Zhao
<chenhui.z...@freescale.com> wrote:
On e6500, in the case of cpu hotplug, either thread in one core
may be the first thread initilzing the TLB1. The subsequent threads
must not
Freescale CoreNet-based and Non-CoreNet-based platforms require
different PM operations. This patch extracted existing PM operations
on Non-CoreNet-based platforms to a new file which can accommodate
both platforms. In this way, PM operation codes are clearer structurally.
Signed-off-by: Chenhui
caches inside the current cpu.
Signed-off-by: Chenhui Zhao <chenhui.z...@freescale.com>
Signed-off-by: Tang Yuantian <yuantian.t...@feescale.com>
---
Changes for v3:
* remove unnecessary ifdef
arch/powerpc/include/asm/cacheflush.h | 2 -
arch/powerpc/include/asm/cputable.h
*
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * Author: Chenhui Zhao <chenhui.z...@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; e
Support Freescale E6500 core-based platforms, like t4240.
Support disabling/enabling individual CPU thread dynamically.
Signed-off-by: Chenhui Zhao <chenhui.z...@freescale.com>
---
changes for v3
* rebase patches on the latest code
* add const for info in wake_hw_thread()
* use r8 instead
On e6500, in the case of cpu hotplug, either thread in one core
may be the first thread initilzing the TLB1. The subsequent threads
must not setup it again.
The code is derived from the comment of Scott Wood.
Signed-off-by: Chenhui Zhao <chenhui.z...@freescale.com>
---
arch/powerpc/inclu
Freescale E500MC and E5500 core-based platforms, like P4080, T1040,
support disabling/enabling CPU dynamically.
This patch adds this feature on those platforms.
Signed-off-by: Chenhui Zhao <chenhui.z...@freescale.com>
Signed-off-by: Tang Yuantian <yuantian.t...@feescale.com>
---
ch
On Thu, Aug 27, 2015 at 6:42 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed, Aug 26, 2015 at 08:09:48PM +0800, Chenhui Zhao wrote:
+ .globl booting_thread_hwid
+booting_thread_hwid:
+ .long INVALID_THREAD_HWID
+ .align 3
The commit message goes into no detail
On Thu, Aug 27, 2015 at 4:55 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed, Aug 26, 2015 at 08:09:47PM +0800, Chenhui Zhao wrote:
+int check_cpu_dead(unsigned int cpu)
+{
+ return per_cpu(cpu_state, cpu) == CPU_DEAD;
+}
I'm not sure this needs to be a function versus open
Freescale CoreNet-based and Non-CoreNet-based platforms require
different PM operations. This patch extracted existing PM operations
on Non-CoreNet-based platforms to a new file which can accommodate
both platforms.
In this way, PM operation codes are clearer structurally.
Signed-off-by: Chenhui
caches inside the current cpu.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@feescale.com
---
arch/powerpc/include/asm/cacheflush.h | 2 -
arch/powerpc/include/asm/cputable.h | 11 +++
arch/powerpc/kernel/asm-offsets.c | 3
000..ed59881
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rcpm.c
@@ -0,0 +1,390 @@
+/*
+ * RCPM(Run Control/Power Management) support
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * Author: Chenhui Zhao chenhui.z...@freescale.com
+ *
+ * This program is free software; you can
Support Freescale E6500 core-based platforms, like t4240.
Support disabling/enabling individual CPU thread dynamically.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
major changes for v2:
* start Thread1 by Thread0 when we want to boot Thread1 only replacing
the method of changing
Freescale E500MC and E5500 core-based platforms, like P4080, T1040,
support disabling/enabling CPU dynamically.
This patch adds this feature on those platforms.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@feescale.com
---
major changes for v2
On Fri, Aug 7, 2015 at 2:02 AM, Scott Wood scottw...@freescale.com
wrote:
On Thu, 2015-08-06 at 13:54 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood scottw...@freescale.com
wrote:
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 10
On Tue, Aug 4, 2015 at 5:18 AM, Scott Wood scottw...@freescale.com
wrote:
[Added linuxppc-dev@lists.ozlabs.org. Besides that list being
required for
review of PPC patches, it feeds the patchwork that I use to track and
apply
patches.]
On Mon, 2015-08-03 at 19:52 +0800, Chenhui Zhao wrote
On Thu, Aug 6, 2015 at 11:16 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 19:08 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 8:22 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-07-31 at 17:20 +0800, b29983@freescale.comwrote
On Thu, Aug 6, 2015 at 1:46 PM, Scott Wood scottw...@freescale.com
wrote:
On Thu, 2015-08-06 at 12:20 +0800, Chenhui Zhao wrote:
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood
scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at 4
On Thu, Aug 6, 2015 at 10:57 AM, Scott Wood scottw...@freescale.com
wrote:
On Wed, 2015-08-05 at 18:11 +0800, Chenhui Zhao wrote:
On Tue, Aug 4, 2015 at 4:26 AM, Scott Wood scottw...@freescale.com
wrote:
On Mon, 2015-08-03 at 19:32 +0800, Chenhui Zhao wrote:
On Sat, Aug 1
On Tue, Aug 4, 2015 at 4:23 AM, Scott Wood scottw...@freescale.com
wrote:
On Mon, 2015-08-03 at 19:14 +0800, Chenhui Zhao wrote:
On Sat, Aug 1, 2015 at 8:45 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-06-26 at 15:44 +0800,
Yuantian.Tang@freescale.comwrote:
+static
On Sat, Aug 1, 2015 at 10:57 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-07-24 at 20:46 +0800, Chenhui Zhao wrote:
+static void mpc85xx_pmc_set_wake(struct device *dev, void *enable)
{
int ret;
+ u32 value[2];
+
+ if (!device_may_wakeup(dev
On Sat, Aug 1, 2015 at 8:41 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-07-31 at 20:53 +0800, Chenhui Zhao wrote:
In the last stage of deep sleep, software will trigger a Finite
State Machine (FSM) to control the hardware precedure, such as
board isolation, killing PLLs
On Sat, Aug 1, 2015 at 8:45 AM, Scott Wood scottw...@freescale.com
wrote:
On Fri, 2015-06-26 at 15:44 +0800, yuantian.t...@freescale.com wrote:
+static void rcpm_v1_set_ip_power(bool enable, u32 *mask)
+{
+ if (enable)
+ setbits32(rcpm_v1_regs-ippdexpcr, *mask);
+
-by: Chenhui Zhao chenhui.z...@freescale.com
---
Note: This patch set is based on CPU hotplug patches.
arch/powerpc/Kconfig | 3 +-
arch/powerpc/platforms/85xx/Kconfig| 5 +++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/qoriq_pm.c | 59
access. This piece of code and related TLBs are prefetched in advance.
Due to the different initialization code between 32-bit and 64-bit, they
have separate resume entry and precedure.
The feature supports 32-bit and 64-bit kernel mode.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch
precedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/platforms/85xx/Makefile| 2 +-
arch/powerpc/platforms/85xx/sleep_fsm.c | 256
arch/powerpc/platforms/85xx/sleep_fsm.h | 104
Add get_dcsrbase() to get the physical base address of DCSR.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/sysdev/fsl_soc.c | 31 +++
arch/powerpc/sysdev/fsl_soc.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/arch/powerpc/sysdev
of Linux Power Management.
Command to enter sleep mode.
echo standby /sys/power/state
Command to enter deep sleep mode.
echo mem /sys/power/state
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/include/asm/cacheflush.h
Core reset may cause issue if using the proxy mode of MPIC.
Use the mixed mode of MPIC if enabling CPU hotplug.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/platforms/85xx/corenet_generic.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc
caches inside the current cpu.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/include/asm/cacheflush.h | 2 -
arch/powerpc/include/asm/cputable.h | 11 +++
arch/powerpc/kernel/asm-offsets.c | 3 +
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 114
power
state). When the core is up again, Thread0 is up first, and it will be
bound with the present booting cpu. This way, all CPUs can hotplug
separately.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/include/asm/fsl_pm.h | 4
mode 100644
index 000..e30f1bc
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_rcpm.c
@@ -0,0 +1,353 @@
+/*
+ * RCPM(Run Control/Power Management) support
+ *
+ * Copyright 2012-2015 Freescale Semiconductor Inc.
+ *
+ * Author: Chenhui Zhao chenhui.z...@freescale.com
+ *
+ * This program is free
-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/Kconfig | 3 +-
arch/powerpc/platforms/85xx/Kconfig| 5 +++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/qoriq_pm.c | 59 ++
arch/powerpc/platforms/86xx/Kconfig
On Tue, Mar 18, 2014 at 06:21:22PM -0500, Scott Wood wrote:
On Mon, 2014-03-17 at 18:27 +0800, Chenhui Zhao wrote:
On Fri, Mar 14, 2014 at 05:51:09PM -0500, Scott Wood wrote:
On Wed, 2014-03-12 at 16:34 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 07:08:43PM -0500, Scott Wood wrote
On Tue, Mar 18, 2014 at 05:42:09PM -0500, Scott Wood wrote:
On Mon, 2014-03-17 at 19:19 +0800, Chenhui Zhao wrote:
On Fri, Mar 14, 2014 at 06:18:27PM -0500, Scott Wood wrote:
On Wed, 2014-03-12 at 18:40 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote
On Fri, Mar 14, 2014 at 05:41:41PM -0500, Scott Wood wrote:
On Wed, 2014-03-12 at 15:46 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 06:51:20PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
In 64-bit mode, kernel just clears the irq soft-enable
On Fri, Mar 14, 2014 at 05:51:09PM -0500, Scott Wood wrote:
On Wed, 2014-03-12 at 16:34 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 07:08:43PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
On Fri, Mar 14, 2014 at 06:01:45PM -0500, Scott Wood wrote:
On Wed, 2014-03-12 at 17:42 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 07:45:14PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
On Fri, Mar 14, 2014 at 06:18:27PM -0500, Scott Wood wrote:
On Wed, 2014-03-12 at 18:40 +0800, Chenhui Zhao wrote:
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Zhao Chenhui chenhui.z...@freescale.com
On Tue, Mar 11, 2014 at 06:51:20PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
In 64-bit mode, kernel just clears the irq soft-enable flag
in struct paca_struct to disable external irqs. But, in
the case of suspend, irqs should be disabled by hardware
On Tue, Mar 11, 2014 at 07:00:27PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
In sleep mode, the clocks of e500 cores and unused IP blocks is
turned off. The IP blocks which are allowed to wake up the processor
are still running.
The sleep mode
On Tue, Mar 11, 2014 at 07:08:43PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Hongbo Zhang hongbo.zh...@freescale.com
In the last stage of deep sleep, software will trigger a Finite
State Machine (FSM) to control the hardware precedure
On Tue, Mar 11, 2014 at 07:45:14PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Wang Dongsheng dongsheng.w...@freescale.com
Add booke_cpu_state_save() and booke_cpu_state_restore() functions which
can be
used to save/restore CPU's registers
On Tue, Mar 11, 2014 at 08:10:24PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
From: Zhao Chenhui chenhui.z...@freescale.com
T1040 supports deep sleep feature, which can switch off most parts of
the SoC when it is in deep sleep mode. This way
On Tue, Mar 11, 2014 at 06:42:51PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:57 +0800, Chenhui Zhao wrote:
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c
b/arch/powerpc/platforms/85xx/corenet_generic.c
index b756f3d..3fdf9f3 100644
--- a/arch/powerpc/platforms/85xx
On Tue, Mar 11, 2014 at 06:48:13PM -0500, Scott Wood wrote:
On Fri, 2014-03-07 at 12:58 +0800, Chenhui Zhao wrote:
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index ac2621a..f3f4401 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -405,8
Implemented CPU hotplug on e500mc and e5500. On e5500 both 32-bit and
64-bit modes can work. Used some callback functions implemented in RCPM
driver.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/kernel/smp.c |6
In 64-bit mode, kernel just clears the irq soft-enable flag
in struct paca_struct to disable external irqs. But, in
the case of suspend, irqs should be disabled by hardware.
Therefore, hook a function to ppc_md.suspend_disable_irqs
to really disable irqs.
Signed-off-by: Chenhui Zhao chenhui.z
of register map in RCPM, which is specified by
the compatible entry in the RCPM node of device tree.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/include/asm/fsl_guts.h | 105
arch/powerpc/platforms/85xx/Kconfig |1 +
arch/powerpc
-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/Kconfig |4 +-
arch/powerpc/platforms/85xx/Makefile |3 +
arch/powerpc/platforms/85xx/qoriq_pm.c | 78
3 files changed, 83 insertions(+), 2 deletions(-)
create mode 100644 arch
the
hardware to complete the early resume precedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Hongbo Zhang hongbo.zh...@freescale.com
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/platforms/85xx/Kconfig |1 +
arch/powerpc/sysdev
Dongsheng dongsheng.w...@freescale.com
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/include/asm/booke_save_regs.h | 96
arch/powerpc/kernel/Makefile |1 +
arch/powerpc/kernel/booke_save_regs.S | 361
3 files
/platforms/85xx/deepsleep.c
new file mode 100644
index 000..ddd7185
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/deepsleep.c
@@ -0,0 +1,201 @@
+/*
+ * Support deep sleep feature
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Author: Chenhui Zhao chenhui.z...@freescale.com
caches in the current cpu.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/powerpc/include/asm/cacheflush.h |2 -
arch/powerpc/include/asm/cputable.h | 11 +++
arch/powerpc/kernel/asm-offsets.c |3 +
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 114
From: Wang Dongsheng dongsheng.w...@freescale.com
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
---
arch/powerpc/include/asm/reg.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index
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