On Sat, Nov 18, 2023 at 05:45:03PM -0600, Timothy Pearson wrote:
> During floating point and vector save to thread data fr0/vs0 are clobbered
> by the FPSCR/VSCR store routine. This leads to userspace register corruption
> and application data corruption / crash under the following rare
On Sat, Sep 30, 2023 at 09:50:41AM -0500, Steve French wrote:
> On Fri, Sep 29, 2023 at 3:06 AM David Howells via samba-technical
> wrote:
> >
> >
> > Jeff Layton wrote:
> >
> > > Correct. We'd lose some fidelity in currently stored timestamps, but as
> > > Linus and Ted pointed out, anything
On Thu, Sep 01, 2022 at 05:22:32AM +, Christophe Leroy wrote:
>
>
> Le 01/09/2022 à 00:45, Segher Boessenkool a écrit :
> > Hi!
> >
> > On Tue, Aug 30, 2022 at 09:10:02AM +, Christophe Leroy wrote:
> >> Le 30/08/2022 à 11:01, Nicholas Piggin a écrit :
> >>> On Tue Aug 30, 2022 at 3:24
On Mon, Aug 22, 2022 at 05:33:35PM +0200, Pali Rohár wrote:
> On Monday 22 August 2022 14:25:57 Christophe Leroy wrote:
> > Le 19/08/2022 à 23:12, Pali Rohár a écrit :
> > > Currently powerpc early debugging contains lot of platform specific
> > > options, but does not support standard UART /
On Mon, Jul 18, 2022 at 04:31:11PM +1000, Michael Ellerman wrote:
> "Jason A. Donenfeld" writes:
> > The archrandom interface was originally designed for x86, which supplies
> > RDRAND/RDSEED for receiving random words into registers, resulting in
> > one function to generate an int and another
On Wed, Apr 06, 2022 at 02:01:48PM +1000, Alexey Kardashevskiy wrote:
> So far the RELACOUNT tag from the ELF header was containing the exact
> number of R_PPC_RELATIVE/R_PPC64_RELATIVE relocations. However the LLVM's
> recent change [1] make it equal-or-less than the actual number which
> makes
On Wed, Mar 23, 2022 at 11:18:40AM +1100, Alexey Kardashevskiy wrote:
>
>
> On 3/22/22 13:12, Michael Ellerman wrote:
> > Alexey Kardashevskiy writes:
> > > So far the RELACOUNT tag from the ELF header was containing the exact
> > > number of R_PPC_RELATIVE/R_PPC64_RELATIVE relocations. However
On Wed, Feb 23, 2022 at 05:27:39PM -0600, Segher Boessenkool wrote:
> On Wed, Feb 23, 2022 at 09:48:09PM +0100, Gabriel Paubert wrote:
> > On Wed, Feb 23, 2022 at 06:11:36PM +0100, Christophe Leroy wrote:
> > > + /* Zero volatile regs that may contain sensitive kernel data */
&g
On Wed, Feb 23, 2022 at 06:11:36PM +0100, Christophe Leroy wrote:
> Commit a82adfd5c7cb ("hardening: Introduce CONFIG_ZERO_CALL_USED_REGS")
> added zeroing of used registers at function exit.
>
> At the time being, PPC64 clears volatile registers on syscall exit but
> PPC32 doesn't do it for
On Mon, Jul 26, 2021 at 05:42:43PM +0200, Michal Suchanek wrote:
> commit 7c6986ade69e ("powerpc/stacktrace: Fix spurious "stale" traces in
> raise_backtrace_ipi()")
> introduces udelay() call without including the linux/delay.h header.
> This may happen to work on master but the header that
On Tue, May 18, 2021 at 08:43:39PM +0200, Christophe Leroy wrote:
>
>
> Le 06/05/2020 à 05:40, Jordan Niethe a écrit :
> > Do not allow inserting breakpoints on the suffix of a prefix instruction
> > in kprobes.
> >
> > Signed-off-by: Jordan Niethe
> > ---
> > v8: Add this back from v3
> > ---
On Thu, Apr 22, 2021 at 06:26:16PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Fri, Apr 23, 2021 at 12:16:18AM +0200, Gabriel Paubert wrote:
> > On Thu, Apr 22, 2021 at 02:13:34PM -0500, Segher Boessenkool wrote:
> > > On Fri, Apr 16, 2021 at 05:44:52PM +1
Hi,
On Thu, Apr 22, 2021 at 02:13:34PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Fri, Apr 16, 2021 at 05:44:52PM +1000, Daniel Axtens wrote:
> > Sathvika Vasireddy writes:
> > Ok, if I've understood correctly...
> >
> > > + ra = ra & ~0x3;
> >
> > This masks off
On Thu, Feb 11, 2021 at 06:34:43AM +, Christophe Leroy wrote:
> unrecoverable_exception() is never expected to return, most callers
> have an infiniteloop in case it returns.
>
> Ensure it really never returns by terminating it with a BUG(), and
> declare it __no_return.
>
> It always GCC to
On Mon, Feb 01, 2021 at 09:55:44AM -0600, Christopher M. Riedl wrote:
> On Thu Jan 28, 2021 at 4:38 AM CST, David Laight wrote:
> > From: Christopher M. Riedl
> > > Sent: 28 January 2021 04:04
> > >
> > > Reuse the "safe" implementation from signal.c except for calling
> > >
On Sat, Nov 07, 2020 at 05:42:57AM -0600, Segher Boessenkool wrote:
> On Sat, Nov 07, 2020 at 08:12:13AM +0100, Gabriel Paubert wrote:
> > On Sat, Nov 07, 2020 at 01:23:28PM +1000, Nicholas Piggin wrote:
> > > ISA v2.06 (POWER7 and up) as well as e6500 support lbarx and lwarx.
&
On Sat, Nov 07, 2020 at 01:23:28PM +1000, Nicholas Piggin wrote:
> ISA v2.06 (POWER7 and up) as well as e6500 support lbarx and lwarx.
Hmm, lwarx exists since original Power AFAIR, s/lwarx/lharx/ perhaps?
Same for the title of the patch and the CONFIG variable.
Gabriel
> Add a
On Thu, Aug 27, 2020 at 12:39:06PM +0200, Christophe Leroy wrote:
> Hi,
>
> Le 27/08/2020 à 10:28, Giuseppe Sacco a écrit :
> > Il giorno gio, 27/08/2020 alle 09.46 +0200, Giuseppe Sacco ha scritto:
> > > Il giorno gio, 27/08/2020 alle 00.28 +0200, Giuseppe Sacco ha scritto:
> > > > Hello
On Tue, Aug 25, 2020 at 09:45:07PM +1000, Jordan Niethe wrote:
> Update the CPU to ISA Version Mapping document to include Power10 and
> ISA v3.1.
>
> Signed-off-by: Jordan Niethe
> ---
> Documentation/powerpc/isa-versions.rst | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
On Sun, Aug 23, 2020 at 12:54:33AM +0800, Guohua Zhong wrote:
> >In generic version in lib/math/div64.c, there is no checking of 'base'
> >either.
> >Do we really want to add this check in the powerpc version only ?
>
> >The only user of __div64_32() is do_div() in
>
On Fri, Jul 24, 2020 at 07:25:25PM +1000, Michael Ellerman wrote:
> We have powerpc specific logic in our page fault handling to decide if
> an access to an unmapped address below the stack pointer should expand
> the stack VMA.
>
> The code was originally added in 2004 "ported from 2.4". The
On Fri, Mar 06, 2020 at 11:26:36AM +1100, Gustavo Romero wrote:
> Fix typos found in comments about the parameter passed
> through r5 to kvmppc_{save,restore}_tm_hv functions.
Actually "iff" is a common shorthand in some fields and not necessarily
a spelling error:
On Thu, Jan 16, 2020 at 07:57:29AM -0600, Segher Boessenkool wrote:
> On Thu, Jan 16, 2020 at 09:06:08AM +0100, Gabriel Paubert wrote:
> > On Thu, Jan 16, 2020 at 07:11:36AM +0100, Christophe Leroy wrote:
> > > Hi Segher,
> > >
> > > I'm trying to see if we cou
On Thu, Jan 16, 2020 at 07:11:36AM +0100, Christophe Leroy wrote:
> Hi Segher,
>
> I'm trying to see if we could enhance TCP checksum calculations by splitting
> inline assembly blocks to give GCC the opportunity to mix it with other
> stuff, but I'm getting difficulties with the carry.
>
> As
On Thu, Sep 05, 2019 at 11:09:35AM +0200, Andreas Schwab wrote:
> On Sep 05 2019, Aleksa Sarai wrote:
>
> > diff --git a/lib/struct_user.c b/lib/struct_user.c
> > new file mode 100644
> > index ..7301ab1bbe98
> > --- /dev/null
> > +++ b/lib/struct_user.c
> > @@ -0,0 +1,182 @@
> > +//
On Tue, Sep 03, 2019 at 01:31:57PM -0500, Segher Boessenkool wrote:
> On Tue, Sep 03, 2019 at 07:05:19PM +0200, Christophe Leroy wrote:
> > Le 03/09/2019 à 18:04, Segher Boessenkool a écrit :
> > >(Why are they separate though? It could just be one loop var).
> >
> > Yes it could just be a
On Thu, Jan 24, 2019 at 04:58:41PM +0100, Christophe Leroy wrote:
>
>
> Le 24/01/2019 à 16:01, Christophe Leroy a écrit :
> >
> >
> > Le 24/01/2019 à 10:43, Christophe Leroy a écrit :
> > >
> > >
> > > On 01/24/2019 01:06 AM, Michael Ellerman wrote:
> > > > Christophe Leroy writes:
> > > >
On Fri, Jan 18, 2019 at 05:18:19PM +0100, Arnd Bergmann wrote:
> The IPC system call handling is highly inconsistent across architectures,
> some use sys_ipc, some use separate calls, and some use both. We also
> have some architectures that require passing IPC_64 in the flags, and
> others that
On Sat, Dec 22, 2018 at 05:04:51PM -0600, Segher Boessenkool wrote:
> On Sat, Dec 22, 2018 at 08:37:28PM +0100, christophe leroy wrote:
> > Le 22/12/2018 à 18:16, Segher Boessenkool a écrit :
> > >On Sat, Dec 22, 2018 at 02:08:02PM +0100, christophe leroy wrote:
> > >>
> > >>Usually, Guarded
On Thu, Oct 04, 2018 at 10:41:13AM +0300, Raz wrote:
> Frankly, the more I read the more perplexed I get. For example,
> according to BOOK III-S, chapter 3,
> the MSR bits are differ from the ones described in
> arch/powerpc/include/asm/reg.h.
> Bit zero, is LE, but in the book it is 64-bit mode.
On Fri, Jun 29, 2018 at 09:58:37PM -0300, Thiago Jung Bauermann wrote:
>
> Gabriel Paubert writes:
>
> > On Thu, Jun 28, 2018 at 11:56:34PM -0300, Thiago Jung Bauermann wrote:
> >>
> >> Hello,
> >>
> >> Ram Pai writes:
> >>
&g
On Thu, Jun 28, 2018 at 11:56:34PM -0300, Thiago Jung Bauermann wrote:
>
> Hello,
>
> Ram Pai writes:
>
> > Key 2 is preallocated and reserved for execute-only key. In rare
> > cases if key-2 is unavailable, mprotect(PROT_EXEC) will behave
> > incorrectly. NOTE: mprotect(PROT_EXEC) uses
On Wed, Jun 27, 2018 at 05:39:15PM +1200, Michael Schmitz wrote:
> Ben,
>
> Am 27.06.2018 um 15:27 schrieb Benjamin Herrenschmidt:
> > On Wed, 2018-06-27 at 13:08 +1000, Michael Ellerman wrote:
> > > > I will rewrite patch 10/12 after Arnd's fixes and this series have all
> > > > made their way
On Fri, Jun 08, 2018 at 10:20:41AM +, Christophe Leroy wrote:
> The generic implementation of strlen() reads strings byte per byte.
>
> This patch implements strlen() in assembly based on a read of entire
> words, in the same spirit as what some other arches and glibc do.
>
> On a 8xx the
On Wed, May 16, 2018 at 02:48:29PM +1000, Stephen Rothwell wrote:
> Hi all,
>
> I have decided that any email sent to the linuxppc-dev mailing list
> that contains an HTML attachment (or is just an HTML email) will be
> rejected. The vast majority of such mail are spam (and I have to spend
>
On Tue, Mar 27, 2018 at 11:01:44PM +1100, Michael Ellerman wrote:
> This commit adds security feature flags to reflect the settings we
> receive from firmware regarding Spectre/Meltdown mitigations.
>
> The feature names reflect the names we are given by firmware on bare
> metal machines. See the
On Thu, Mar 22, 2018 at 08:25:43PM +1100, Oliver wrote:
> On Thu, Mar 22, 2018 at 7:20 PM, Gabriel Paubert <paub...@iram.es> wrote:
> > On Thu, Mar 22, 2018 at 04:24:24PM +1100, Oliver wrote:
> >> On Thu, Mar 22, 2018 at 1:35 AM, David Laight <david.lai...@aculab.com>
On Thu, Mar 22, 2018 at 04:24:24PM +1100, Oliver wrote:
> On Thu, Mar 22, 2018 at 1:35 AM, David Laight wrote:
> >> x86 has compiler barrier inside the relaxed() API so that code does not
> >> get reordered. ARM64 architecturally guarantees device writes to be
> >>
On Wed, Jan 31, 2018 at 10:03:46AM +, James Hogan wrote:
> On Wed, Jan 31, 2018 at 10:37:30AM +0100, Gabriel Paubert wrote:
> > Hi,
> >
> > yesterday I recompiled the kernel on my late 2005 G4 PowerBook, and the
> > Wifi stopped working. After comparing the
, and I'm not sure that
I fully understand it.
Nevertheless the following patch fixes the regression, but there might
be a better way to solve the problem.
If you pick up this trivial patch as is, you may add:
Signed-off-by: Gabriel Paubert <paub...@iram.es>
diff --git a/drivers/ssb/Kco
On Mon, Jan 29, 2018 at 01:33:08PM -0600, Larry Finger wrote:
> In kernel 4.15, the modprobe step on my PowerBook G5 started complaining that
PowerBook G5? Really, could you send a pic! :-)
> there was no module license for ans-lcd.
>
> Signed-off-by: Larry Finger
On Thu, Dec 21, 2017 at 12:52:01AM +1000, Nicholas Piggin wrote:
> Shifted left by 16 bits, so the low 16 bits of r14 remain available.
> This allows per-cpu pointers to be dereferenced with a single extra
> shift whereas previously it was a load and add.
> ---
> arch/powerpc/include/asm/paca.h
On Mon, Dec 18, 2017 at 03:15:51PM -0800, Ram Pai wrote:
> On Mon, Dec 18, 2017 at 02:28:14PM -0800, Dave Hansen wrote:
> > On 12/18/2017 02:18 PM, Ram Pai wrote:
> > > b) minimum number of keys available to the application.
> > > if libraries consumes a few, they could provide a library
> > >
On Tue, Nov 14, 2017 at 02:32:17PM +, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to spelling mistake in pr_err error message text. Also
> fix spelling mistake in proceeding comment.
s/proceeding/preceding/ ?
>
> Signed-off-by: Colin Ian King
On Tue, Jul 25, 2017 at 06:08:05PM +1000, Balbir Singh wrote:
> On Tue, 2017-07-25 at 13:33 +1000, Matt Brown wrote:
> > This adds emulation for the prtyw and prtyd instructions.
> > Tested for logical correctness against the prtyw and prtyd instructions
> > on ppc64le.
> >
> > Signed-off-by:
On Tue, Jul 25, 2017 at 01:33:17PM +1000, Matt Brown wrote:
> This adds emulations for the popcntb, popcntw, and popcntd instructions.
> Tested for correctness against the popcnt{b,w,d} instructions on ppc64le.
>
> Signed-off-by: Matt Brown
> ---
> v3:
> -
On Thu, Jul 13, 2017 at 01:25:46PM +1000, Matt Brown wrote:
> This adds emulation for the bpermd instruction.
>
> Signed-off-by: Matt Brown
> ---
> arch/powerpc/lib/sstep.c | 23 +++
> 1 file changed, 23 insertions(+)
>
> diff --git
On Sun, Mar 05, 2017 at 11:24:56AM -0600, Segher Boessenkool wrote:
> On Sun, Mar 05, 2017 at 05:58:37PM +0100, Gabriel Paubert wrote:
> > > > Erk sorry. One of the static checkers spotted it, but I hadn't got
> > > > around to fixing it because it seemed to
On Sun, Mar 05, 2017 at 06:37:37AM -0600, Segher Boessenkool wrote:
> On Sun, Mar 05, 2017 at 09:26:47PM +1100, Michael Ellerman wrote:
> > > I see a panic in early boot when building with a recent gcc toolchain.
> > > The issue is a divide by zero, which is undefined. Older toolchains
> > > let
On Tue, Feb 21, 2017 at 09:24:38AM +1300, Hamish Martin wrote:
> This patch series adds the ability to configure the THREAD_SHIFT value and
> thereby alter the stack size on powerpc systems. We are particularly
> interested
> in configuring for a 32k stack on PPC64.
>
> Using an NXP T2081 (e6500
Hi,
On Mon, Nov 14, 2016 at 11:34:52PM +0530, Madhavan Srinivasan wrote:
> Local atomic operations are fast and highly reentrant per CPU counters.
> Used for percpu variable updates. Local atomic operations only guarantee
> variable modification atomicity wrt the CPU which owns the data
On Tue, Aug 23, 2016 at 05:45:04PM -0700, mcg...@kernel.org wrote:
[snip]
> ---
> Documentation/firmware_class/README| 20
> drivers/base/Kconfig | 2 +-
> .../request_firmware-avoid-init-probe-init.cocci | 130
> +
> 3
On Thu, Aug 18, 2016 at 12:13:21PM +0200, Christophe Leroy wrote:
>
>
> Le 18/08/2016 à 11:58, Gabriel Paubert a écrit :
> >On Thu, Aug 18, 2016 at 11:44:20AM +0200, Christophe Leroy wrote:
> >>SPRN_ICR must be read for clearing the internal freeze signal which
> >&
On Thu, Aug 18, 2016 at 11:44:20AM +0200, Christophe Leroy wrote:
> SPRN_ICR must be read for clearing the internal freeze signal which
> is asserted by the single step exception, otherwise the timebase and
> decrementer remain freezed
Minor nit: s/freezed/frozen/
If the timebase and decrementer
On Thu, Aug 11, 2016 at 05:11:19PM -0500, Segher Boessenkool wrote:
> On Thu, Aug 11, 2016 at 11:34:37PM +0200, Gabriel Paubert wrote:
> > On the other hand gcc did at the time a very poor job (quite an
> > understatement) at bswapdi when compiling for 64 bit processors
>
On Wed, Aug 10, 2016 at 12:18:15PM +0200, Christophe Leroy wrote:
>
>
> Le 10/08/2016 à 10:56, Gabriel Paubert a écrit :
> >On Fri, Aug 05, 2016 at 01:28:02PM +0200, Christophe Leroy wrote:
> >>Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
> >>
On Fri, Aug 05, 2016 at 01:28:02PM +0200, Christophe Leroy wrote:
> Signed-off-by: Christophe Leroy
> ---
> arch/powerpc/kernel/misc_32.S | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/kernel/misc_32.S
On Wed, Aug 10, 2016 at 01:17:55AM -0700, Christian Kujau wrote:
> On Wed, 10 Aug 2016, Benjamin Herrenschmidt wrote:
> > We cannot do those initializations from apply_feature_fixups() as
> > this function runs in a very restricted environment in 32-bit where
> > the kernel isn't running at its
On Sun, May 29, 2016 at 10:03:50PM +1000, Anton Blanchard wrote:
> From: Anton Blanchard
>
> In both __giveup_fpu() and __giveup_altivec() we make two modifications
> to tsk->thread.regs->msr. gcc decides to do a read/modify/write of
> each change, so we end up with a load hit
On Mon, May 23, 2016 at 10:46:36AM +0200, Christophe Leroy wrote:
> lmw/stmw have a 1 cycle (2 cycles for lmw on some ppc) in addition
> and implies serialising, however it reduces the amount of instructions
> hence the amount of instruction fetch compared to the equivalent
> operation with
On Mon, May 23, 2016 at 10:46:02AM +0200, Christophe Leroy wrote:
> current_stack_pointeur() is a single instruction function. it
> It is not worth breaking the execution flow with a bl/blr for a
> single instruction
Are you sure that the result is always the same?
Calling an external function
On Fri, May 13, 2016 at 04:16:57PM +1000, Michael Ellerman wrote:
> On Thu, 2016-12-05 at 15:32:22 UTC, Christophe Leroy wrote:
> > With the ffs() function as defined in arch/powerpc/include/asm/bitops.h
> > GCC will not optimise the code in case of constant parameter, as shown
> > by the small
Hi Michael,
On Fri, Apr 01, 2016 at 05:14:35PM +1100, Michael Ellerman wrote:
> On Wed, 2016-03-30 at 23:49 +0530, Hari Bathini wrote:
> > Some of the interrupt vectors on 64-bit POWER server processors are
> > only 32 bytes long (8 instructions), which is not enough for the full
> ...
> >
On Wed, Mar 09, 2016 at 03:26:21PM -0600, Scott Wood wrote:
> On Wed, 2016-03-09 at 11:28 +0100, Gabriel Paubert wrote:
> > On Wed, Mar 09, 2016 at 12:38:18AM -0600, Scott Wood wrote:
> > > On Tue, Mar 08, 2016 at 08:59:12AM +0100, Alessio Igor Bogani wrote:
> > > &
On Wed, Mar 09, 2016 at 12:38:18AM -0600, Scott Wood wrote:
> On Tue, Mar 08, 2016 at 08:59:12AM +0100, Alessio Igor Bogani wrote:
> > The mtmsr() function hangs during restart. Make reboot works on
> > MVME5100 removing that function call.
> > ---
> >
On Thu, Dec 17, 2015 at 01:43:12PM +1100, Alistair Popple wrote:
> Move __raw_rw_writeq() from platforms/powernv/pci-ioda.c to
^
Typo?
(not a big deal)
Gabriel
> include/asm/io.h so that it can be used by other code.
>
> Signed-off-by: Alistair Popple
>
On Mon, Nov 30, 2015 at 06:08:23PM +0100, Christian Zigotzky wrote:
> Hi All,
>
> I have tested the PA Semi Ethernet with the kernels 4.2.3 and 4.3.0
> today. With the kernel 4.2.3 it works but with the kernel 4.3.0
> final it doesn't work.
>
> After that I tested some git kernels and release
On Fri, Oct 16, 2015 at 08:20:13AM +0200, Christophe JAILLET wrote:
> Le 15/10/2015 08:36, Michael Ellerman a écrit :
> >On Thu, 2015-10-15 at 07:56 +0200, Christophe JAILLET wrote:
> >>Use 'of_property_read_u32()' instead of 'of_get_property()'+pointer
> >>dereference in order to avoid access to
On Fri, Sep 25, 2015 at 12:28:30PM +0300, Denis Kirjanov wrote:
> On 9/25/15, Arnd Bergmann wrote:
> > On Friday 25 September 2015 14:01:39 Michael Neuling wrote:
> >> This adds a benchmark directory to the powerpc selftests and adds a
> >> gettimeofday() benchmark to it.
> >>
> >>
On Wed, Jul 22, 2015 at 03:51:03PM +1000, Michael Ellerman wrote:
On Tue, 2015-07-21 at 12:28 +0530, Anshuman Khandual wrote:
From: khand...@linux.vnet.ibm.com khand...@linux.vnet.ibm.com
This patch adds some documentation to 'patch_slb_encoding' function
explaining about how it clears
On Sat, Mar 28, 2015 at 12:19:10PM +1100, Michael Ellerman wrote:
This adds a test of the switch_endian() syscall we added in the previous
commit.
We test it by calling the endian switch syscall, and then executing some
code in the other endian to check everything went as expected. That code
On Fri, Jan 30, 2015 at 05:37:29AM +, Markus Stockhausen wrote:
Von: Scott Wood [scottw...@freescale.com]
Gesendet: Freitag, 30. Januar 2015 01:49
An: Markus Stockhausen
Cc: Michael Ellerman; linuxppc-dev@lists.ozlabs.org; Herbert Xu
Betreff: Re: AW: SPE Interrupt context (was how
On Fri, Jan 30, 2015 at 09:39:41AM +, Markus Stockhausen wrote:
Von: Gabriel Paubert [paub...@iram.es]
Gesendet: Freitag, 30. Januar 2015 09:49
An: Markus Stockhausen
Cc: Scott Wood; linuxppc-dev@lists.ozlabs.org; Herbert Xu
Betreff: Re: AW: SPE Interrupt context (was how to make
On Wed, Dec 03, 2014 at 08:29:37PM +0530, Madhavan Srinivasan wrote:
On Tuesday 02 December 2014 03:05 AM, Gabriel Paubert wrote:
On Thu, Nov 27, 2014 at 05:48:40PM +0530, Madhavan Srinivasan wrote:
diff --git a/arch/powerpc/include/asm/exception-64s.h
b/arch/powerpc/include/asm/exception
On Thu, Nov 27, 2014 at 05:48:41PM +0530, Madhavan Srinivasan wrote:
This patch re-write the current local_* functions to CR5 based one.
Base flow for each function is
{
set cr5(eq)
load
..
store
clear cr5(eq)
}
Above set of instructions are followed by
On Thu, Nov 27, 2014 at 05:48:40PM +0530, Madhavan Srinivasan wrote:
This patch create the infrastructure to handle the CR based
local_* atomic operations. Local atomic operations are fast
and highly reentrant per CPU counters. Used for percpu
variable updates. Local atomic operations only
On Fri, Sep 05, 2014 at 03:28:47PM +1000, Michael Neuling wrote:
The Debian powerpc little endian architecture is called ppc64le. This
Huh? ppc64le or ppc64el?
is the default architecture used by Ubuntu for powerpc.
The below checks the kernel config to see if we are compiling little
On Wed, Sep 03, 2014 at 10:36:57PM -0400, Jerome Glisse wrote:
On Wed, Sep 03, 2014 at 10:31:18PM -0400, Jerome Glisse wrote:
On Thu, Sep 04, 2014 at 12:25:23PM +1000, Benjamin Herrenschmidt wrote:
On Wed, 2014-09-03 at 22:07 -0400, Jerome Glisse wrote:
So in the meantime the
On Thu, Jun 12, 2014 at 07:26:39AM -0500, Segher Boessenkool wrote:
Actually, from gcc/config/rs6000.h:
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator.
[snip]
So cr5, which is number 73, is never used by gcc.
Not
On Thu, Jun 12, 2014 at 06:22:11AM +1000, Benjamin Herrenschmidt wrote:
On Wed, 2014-06-11 at 14:37 -0500, Christoph Lameter wrote:
Looking at arch/powerpc/include/asm/percpu.h I see that the per cpu offset
comes from a local_paca field and local_paca is in r13. That means that
for all
On Fri, May 09, 2014 at 06:41:13AM -0700, Paul E. McKenney wrote:
On Fri, May 09, 2014 at 05:47:12PM +1000, Anton Blanchard wrote:
I am seeing an issue where a CPU running perf eventually hangs.
Traces show timer interrupts happening every 4 seconds even
when a userspace task is running on
On Thu, Mar 06, 2014 at 09:44:47AM +, David Laight wrote:
From: Sukadev Bhattiprolu
When checking whether a bit representing a register is set in
sample_regs, a 64-bit mask, use 64-bit value (1LL).
Signed-off-by: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
---
On Fri, Feb 07, 2014 at 02:49:40PM -0600, James Yang wrote:
On Fri, 7 Feb 2014, Gabriel Paubert wrote:
Hi Stephen,
On Fri, Feb 07, 2014 at 11:27:57AM +1000, Stephen N Chivers wrote:
Gabriel Paubert paub...@iram.es wrote on 02/06/2014 07:26:37 PM:
From: Gabriel Paubert paub
On Mon, Feb 10, 2014 at 11:17:38AM +, David Laight wrote:
However, your other solutions are better.
mask = (FM 1);
mask |= (FM 3) 0x10;
mask |= (FM 6) 0x100;
mask |= (FM 9) 0x1000;
mask |= (FM 12) 0x1;
mask |= (FM 15) 0x10;
On Mon, Feb 10, 2014 at 12:32:18PM +, David Laight wrote:
I disagree, perhaps mostly because the compiler is not clever enough, but
right
now the code for solution 1 is (actually I have rewritten the code
and it reads:
mask = (FM 1)
| ((FM 3) 0x10)
Hi James,
On Mon, Feb 10, 2014 at 11:03:07AM -0600, James Yang wrote:
[snipped]
Ok, if you have measured that method1 is faster than method2, let us go for
it.
I believe method2 would be faster if you had a large out-of-order execution
window, because more parallelism can be
Hi Stephen,
On Fri, Feb 07, 2014 at 11:27:57AM +1000, Stephen N Chivers wrote:
Gabriel Paubert paub...@iram.es wrote on 02/06/2014 07:26:37 PM:
From: Gabriel Paubert paub...@iram.es
To: Stephen N Chivers schiv...@csc.com.au
Cc: linuxppc-dev@lists.ozlabs.org, Chris Proctor cproc
On Thu, Feb 06, 2014 at 12:09:00PM +1000, Stephen N Chivers wrote:
I have a MPC8548e based board and an application that makes
extensive use of floating point including numerous calls to cos.
In the same program there is the use of an sqlite database.
The kernel is derived from 2.6.31 and is
On Mon, Feb 03, 2014 at 08:16:49AM +0100, Michael Moese wrote:
Allow for IO memory to be mapped cacheable for performing
PCI read bursts.
Signed-off-by: Michael Moese michael.mo...@men.de
---
arch/powerpc/include/asm/io.h | 3 +++
arch/powerpc/mm/pgtable_32.c | 8
2 files
On Thu, Jan 30, 2014 at 12:20:21PM +, Moese, Michael wrote:
Hello PPC-developers,
I'm currently trying to benchmark access speeds to our PCIe-connected IP-cores
located inside our FPGA. On x86-based systems I was able to achieve bursts for
both read and write access. On PPC32, using an
On Mon, May 13, 2013 at 05:09:59PM +1000, Michael Neuling wrote:
David Woodhouse dw...@infradead.org wrote:
From: David Woodhouse david.woodho...@intel.com
Some versions of GCC apparently expect this to be provided by libgcc.
Signed-off-by: David Woodhouse david.woodho...@intel.com
On Mon, May 13, 2013 at 11:38:13AM +0100, David Woodhouse wrote:
On Mon, 2013-05-13 at 11:33 +0100, David Woodhouse wrote:
On Mon, 2013-05-13 at 09:33 +0200, Gabriel Paubert wrote:
Actually, I'd swap the two mr instructions to never
have an instruction that uses the result from
On Fri, Nov 09, 2012 at 05:18:58PM +1100, Michael Neuling wrote:
This set of patches adds support for taking exceptions with the MMU on which
is
supported by POWER8.
A new set of exception vectors is added at 0xc000___4xxx. When the HW
takes us here, MSR IR/DR will be set already
On Fri, Nov 09, 2012 at 05:26:42PM +1100, Michael Neuling wrote:
A PVR of 0x0F04 means we are arch v2.07 complicate ie, POWER8.
Huh?
s/complicate/compliant/ ?
Also ie has to be written with dots (i.e.).
Gabriel
Signed-off-by: Michael Neuling mi...@neuling.org
diff
On Sun, Sep 23, 2012 at 03:46:06AM +0200, Segher Boessenkool wrote:
Why does the kernel emulate this, btw? I can see emulation is useful
for running older binaries, for instructions that have been removed
from the architecture; but for newly added instructions, or optional
instructions, it
On Mon, Sep 24, 2012 at 05:58:37PM +1000, Benjamin Herrenschmidt wrote:
On Mon, 2012-09-24 at 09:55 +0200, Gabriel Paubert wrote:
On Sun, Sep 23, 2012 at 03:46:06AM +0200, Segher Boessenkool wrote:
Why does the kernel emulate this, btw? I can see emulation is useful
for running older
On Sat, Sep 22, 2012 at 02:12:42PM +0400, malc wrote:
On Sat, 22 Sep 2012, Segher Boessenkool wrote:
Is it possible to determine if _native_ isel is available from userspace
somehow?
Just try to execute one and catch the SIGILL?
Unfortunately my kernel emulates ISEL for me in
On Thu, Jul 12, 2012 at 04:59:12PM -0700, Sukadev Bhattiprolu wrote:
From: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Date: Tue, 3 Jul 2012 13:32:46 -0700
Subject: [PATCH 1/2] power: Define PV_POWER7P
This change is based on the patch that Carl Love posted to LKML
On Thu, Jun 21, 2012 at 03:36:01PM +1000, Michael Ellerman wrote:
On Wed, 2012-06-20 at 17:50 +1000, Stephen Rothwell wrote:
Hi all,
After merging the final tree, today's linux-next build (powerpc
allyesconfig) failed like this:
powerpc64-linux-ld: arch/powerpc/net/built-in.o: In
On Tue, Jun 05, 2012 at 08:00:42AM +1000, Benjamin Herrenschmidt wrote:
On Mon, 2012-06-04 at 13:03 +0200, Gabriel Paubert wrote:
There is no conflict to the ABI. These functions are supposed to be
directly reachable from whatever code
section may need them.
Now I have a question: how
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