letion on submit for interruptless buffers.
>
> Signed-off-by: Christophe Leroy
> ---
> drivers/soc/fsl/qe/qmc.c | 44 ++--
> 1 file changed, 33 insertions(+), 11 deletions(-)
>
Acked-by: Herve Codina
Best regards,
Hervé
o
> frame, it is possible to re-order codecs on the TDM bus, no need to
> mix up timeslots in channels.
>
> Signed-off-by: Christophe Leroy
> ---
> sound/soc/fsl/fsl_qmc_audio.c | 29 +
> 1 file changed, 29 insertions(+)
>
Acked-by: Herve Codina
Best regards,
Hervé
On Tue, 12 Aug 2025 12:50:56 +0200
Christophe Leroy wrote:
> To reduce complexity of interrupt handling in following patch, ensure
> audio channels are configured in the same order as timeslots on the
> TDM bus. If we need a given ordering of audio sources in the audio
> frame, it is possible to
Hi Christophe,
On Wed, 13 Aug 2025 12:06:51 +0200
Herve Codina wrote:
> Hi Christophe,
>
> On Tue, 12 Aug 2025 12:50:55 +0200
> Christophe Leroy wrote:
>
> > When no post-completion processing is expected, don't waste time
> > handling useless interrupts.
&
Hi Christophe,
On Tue, 12 Aug 2025 12:50:56 +0200
Christophe Leroy wrote:
...
> @@ -879,6 +884,30 @@ static int qmc_audio_dai_parse(struct qmc_audio
> *qmc_audio, struct device_node *
> return -EINVAL;
> }
> }
> +
> +
Hi Christophe,
On Tue, 12 Aug 2025 12:50:55 +0200
Christophe Leroy wrote:
> When no post-completion processing is expected, don't waste time
> handling useless interrupts.
>
> Only set QMC_BD_[R/T]X_I when a completion function is passed in,
> and perform seamless completion on submit for inter
he QMC irq thread uses 16% CPU time with this
> patch while it uses 26% CPU time without this patch.
>
> Signed-off-by: Christophe Leroy
> ---
> sound/soc/fsl/fsl_qmc_audio.c | 46 +------
> 1 file changed, 6 insertions(+), 40 deletions(-)
>
Acked-by:
off-by: Christophe Leroy
> ---
> v2: New
> ---
> sound/soc/fsl/fsl_qmc_audio.c | 50 +--
> 1 file changed, 19 insertions(+), 31 deletions(-)
Acked-by: Herve Codina
Best regards,
Hervé
On Fri, 9 May 2025 09:48:45 +0200
Christophe Leroy wrote:
> In non-interleaved mode, several QMC channels are used in sync.
> More details can be found in commit 188d9cae5438 ("ASoC: fsl:
> fsl_qmc_audio: Add support for non-interleaved mode.")
> At the time being, an interrupt is requested on e
Hi Christophe,
On Fri, 9 May 2025 11:13:12 +0200
Christophe Leroy wrote:
> Hi Hervé,
>
> Le 09/05/2025 à 10:45, Herve Codina a écrit :
> > On Fri, 9 May 2025 09:48:45 +0200
> > Christophe Leroy wrote:
> >
> >> In non-interleaved mode, several QMC
Hi Christophe,
On Fri, 9 May 2025 09:48:44 +0200
Christophe Leroy wrote:
> When no post-completion processing is expected, don't waste time
> handling useless interrupts.
>
> Only set QMC_BD_[R/T]X_I and QMC_BD_[R/T]X_UB when a completion
> function is passed in.
>
> Signed-off-by: Christophe
or the user-space and the driver are writing and reading
the same area.
Fix that resetting data pointers on each SNDRV_PCM_TRIGGER_START events.
Fixes: 075c7125b11c ("ASoC: fsl: Add support for QMC audio")
Cc: sta...@vger.kernel.org
Signed-off-by: Herve Codina
---
sound/soc/fsl/fsl_q
ff --git a/sound/soc/fsl/fsl_qmc_audio.c b/sound/soc/fsl/fsl_qmc_audio.c
> index e257b8adafe0..b2979290c973 100644
> --- a/sound/soc/fsl/fsl_qmc_audio.c
> +++ b/sound/soc/fsl/fsl_qmc_audio.c
Acked-by: Herve Codina
Best regards,
Hervé
Hi Pei,
On Wed, 20 Nov 2024 17:38:20 +0800
Pei Xiao wrote:
> platform_get_irq() may failed,but ret still equals to 0,
> will cacuse qmc_probe() return 0 but fail.
>
> Reported-by: Dan Carpenter
> Closes: https://lore.kernel.org/r/202411051350.kny6ziwa-...@intel.com/
> Fixes: 3178d58e0b97 ("soc
7;s refcount.
>
> Note that the device_node is declared within the macro, and its explicit
> declaration can be dropped as well if it is not used anywhere else.
>
> Signed-off-by: Javier Carrasco
> ---
> drivers/soc/fsl/qe/tsa.c | 28
> 1 file ch
error code.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Closes: https://lore.kernel.org/r/202411051350.kny6ziwa-...@intel.com/
Fixes: 3178d58e0b97 ("soc: fsl: cpm1: Add support for QMC")
Cc: sta...@vger.kernel.org
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 4 +++
ace changes to make indention consistent.
>
> Signed-off-by: Uwe Kleine-König
> ---
...
> drivers/soc/fsl/qe/qmc.c| 2 +-
> drivers/soc/fsl/qe/tsa.c| 2 +-
Acked-by: Herve Codina # for fsl/qe/{qmc,tsa}.c
Best regards,
Hervé
On each channel parsing, a log message is issued. This log message is
not needed and become annoying when many channels are used (up to 64
channel supported).
Simply remove this unneeded log message.
Signed-off-by: Herve Codina
---
sound/soc/fsl/fsl_qmc_audio.c | 2 --
1 file changed, 2
Hi Geert,
On Mon, 30 Sep 2024 17:11:09 +0200 (CEST)
Geert Uytterhoeven wrote:
> On Mon, 30 Sep 2024, Geert Uytterhoeven wrote:
> > Below is the list of build error/warning regressions/improvements in
> > v6.12-rc1[1] compared to v6.11[2].
...
powerpc-gcc13/ppc64_book3e_allmodconfig
>
> dri
3 insertions(+), 4 deletions(-)
>
Thanks for the patch.
Works on my side, no regressions found on my MPC8321 system.
Tested-by: Herve Codina
And of course:
Acked-by: Herve Codina
Sorry for this mistake.
Best regards,
Hervé
.ou2kfnko-...@intel.com/
Fixes: eb680d563089 ("soc: fsl: cpm1: qmc: Add support for QUICC Engine (QE)
implementation")
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fs
es:
https://lore.kernel.org/oe-kbuild-all/202409051409.fszn8reo-...@intel.com/
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/ucc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c
index 21dbcd787cd5..892aa5931d5b 100644
--- a/drivers/soc/fsl/qe/u
L_SOC.
>
> Reported-by: Stephen Rothwell
> Closes: https://lore.kernel.org/lkml/20240904104859.020fe...@canb.auug.org.au/
> Fixes: 8655b76b7004 ("soc: fsl: cpm1: qmc: Handle QUICC Engine (QE) soft-qmc
> firmware")
> Signed-off-by: Christophe Leroy
Thanks for this patch!
Acked-by: Herve Codina
Best regards,
Hervé
that case.
Simply add the missing command in the commands list available in the QE
header file.
Signed-off-by: Herve Codina
---
include/soc/fsl/qe/qe.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index 629835b6c71d..8f967d15e479 100644
--- a
be automatically freed on driver detach.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qe_common.c | 80 ++
include/soc/fsl/qe/qe.h| 22 +-
2 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qe/qe_common.c b
The Freescale QMC controller driver supports both QE and CPM1.
Add the newly introduced QE files to the existing entry.
Signed-off-by: Herve Codina
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1d32d38f2247..1331bdeb7386 100644
--- a
() for consistency to revert operations done
in qmc_init_xcc().
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 66 +++-
1 file changed, 45 insertions(+), 21 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index
The QUICC Engine (QE) QMC can use a firmware to have the QMC working in
'soft-qmc' mode.
Handle this optional 'soft-qmc' firmware.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 67
1 file changed, 67 insertions(+)
diff
, compared against the CPM QMC, this QE QMC does not
use a fixed area for the UCC/SCC parameters area but it uses a dynamic
area allocated and provided to the hardware at runtime.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/Kconfig | 9 +-
drivers/soc/fsl/qe/qmc.c | 209
, compared against the CPM QMC, this QE QMC does not
use a fixed area for the UCC/SCC parameters area but it uses a dynamic
area allocated and provided to the hardware at runtime.
Last point, the QE QMC can use a firmware to have the QMC working in
'soft-qmc' mode.
Signed-off-by: He
Current code handles the CPM1 version of QMC.
In order to prepare the support for the QUICC Engine (QE) version of
QMC, introduce qmc_version to identify versions. This will enable the
code to make the distinction between several QMC implementations.
Signed-off-by: Herve Codina
---
drivers/soc
defined for the QMC mode is CPM1 specific.
In order to prepare the support for the QE version, rename this bitfield
value to clearly identify it as CPM1 specific.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers
initialization has no impact in the CPM1 version
of QMC.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 272da250a763..63af2608c3cd 100644
--- a/drivers/soc/fsl/qe/qmc.c
Current code handles CPM1 version of QMC and qmc_chan_command() is
clearly CPM1 specific.
In order to prepare the support for the QUICC Engine (QE) version,
rename qmc_chan_command() to reflect that point.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 6 +++---
1 file changed, 3
fined.
In order to prepare the support for QE version, introduce
qmc_init_resource() to initialize those resources and isolate the CPM1
specific operations in a specific function.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 47 ++--
1 file c
initializing resources.
- Group SCC initialisation and do this initialization when it is really
needed in the probe() sequence.
Having the QE compatible sequence in the CPM1 version does not lead to
any issue and works correctly without any regressions.
Signed-off-by: Herve Codina
---
drivers/soc
, introduce the qmc_data structure to define
these version specific values.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 69 ++--
1 file changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index
checkpatch.pl raises the following issue
CHECK: spinlock_t definition without comment
Add the missing comments.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
checkpatch.pl raises the following issue
CHECK: 'transmiter' may be misspelled - perhaps 'transmitter'?
Indeed, fix it.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc
checkpatch.pl raises the following issue in several places
CHECK: Unnecessary parenthesis around ...
Remove them.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe
checkpatch.pl raises the following issues
CHECK: Please don't use multiple blank lines
CHECK: Alignment should match open parenthesis
Fix them.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/dr
checkpatch.pl signals the following improvement for qmc.c
CHECK: Prefer using the BIT macro
Follow its suggestion and convert the code to BIT() and related macros.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 132 +--
1 file changed, 72
QMC_TSA_MASK is a bitfield. The value defined is a specific value of
this bitfield and correspond to the use of 8bit resolution for the
routing entry.
Be accurate and rename the defined constant to reflect this point.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 8
1
TSA consumers in CPM1 implementation don't need to know about the serial
device number used by the TSA component. In QUICC Engine implementation,
this information is needed.
Improve the TSA API with tsa_serial_get_num() in order to provide this
information.
Signed-off-by: Herve C
The Freescale TSA controller driver supports both QE and CPM1.
Add the newly introduced QE files to the existing entry.
Signed-off-by: Herve Codina
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 42decde38320..1d32d38f2247 100644
--- a
against the CPM1 TSA, this QE TSA can handle up to 4 TDMs
instead of 2 and allows to configure the logic level of sync signals.
At a lower level, compared against CPM TSA implementation, some
registers are slightly different even if same features are present.
Signed-off-by: Herve Codina
Current code handles CPM1 version of TSA.
In order to prepare the support for the QUICC Engine (QE) version of
TSA, introduce tsa_version to identify versions. This will enable the
code to make the distinction between several TSA implementations.
Signed-off-by: Herve Codina
---
drivers/soc/fsl
QE version, clearly identify
SICR register as specific to CPM1 and isolate its handling done in
connect and disconnect functions.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 103 ---
1 file changed, 43 insertions(+), 60 deletions(-)
diff --git
as CPM1 compatible and isolate their handling in a CPM1
specific function.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 93 +++-
1 file changed, 54 insertions(+), 39 deletions(-)
diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
Current code handles the CPM1 version of TSA. Compared against QUICC
Engine (QE) version of TSA, CPM1 SIRAM entries are slightly different.
In order to prepare the support for the QE version, clearly identify
these entries and functions handling them as CPM1 compatible.
Signed-off-by: Herve
ing device.h header for devres_* function declarations
(issue detected by kernel test robots).
- Other patches
No changes
Herve Codina (36):
soc: fsl: cpm1: qmc: Update TRNSYNC only in transparent mode
soc: fsl: cpm1: qmc: Enable TRNSYNC only when needed
soc: fsl: cpm1: tsa: Fix tsa_wr
The TRNSYNC feature is enabled whatever the number of time-slots used.
The feature is needed only when more than one time-slot is used.
Improve the driver enabling TRNSYNC only when it is needed.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 12 +++-
1 file changed, 11
checkpatch.pl raises the following issue
CHECK: spinlock_t definition without comment
Add the missing comment.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
SISTR, SICMR and SIRP registers offset definitions are not used.
In order to avoid unneeded code, remove them.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
index
The tsa_write8() parameter is an u32 value. This is not consistent with
the function itself. Indeed, tsa_write8() writes an 8bits value.
Be consistent and use an u8 parameter value.
Fixes: 1d4ba0b81c1c ("soc: fsl: cpm1: Add support for TSA")
Cc: sta...@vger.kernel.org
Signed-off-by: He
checkpatch.pl raises the following issues
CHECK: Please don't use multiple blank lines
CHECK: spaces preferred around that '/' (ctx:VxV)
CHECK: spaces preferred around that '+' (ctx:VxV)
CHECK: spaces preferred around that '-' (ctx:VxV)
Fix them.
Signed
Loops handling the tdm array use hardcoded size and the initialization
part uses hardcoded indexes to initialize the array.
Use ARRAY_SIZE() to avoid the hardcoded size and initialize the array
using a loop.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 8
1 file changed
against the CPM TSA, this QE TSA can handle
up to 4 TDMs instead of 2 and allows to configure the logic level of
sync signals.
Signed-off-by: Herve Codina
---
.../bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml | 210 ++
include/dt-bindings/soc/qe-fsl,tsa.h | 13 ++
2 files
top()")
Cc: sta...@vger.kernel.org
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 76bb496305a0..bacabf731dcb 100644
--- a/drivers/soc/fsl/qe/qmc
checkpatch.pl signals the following improvement for tsa.c
CHECK: Prefer using the BIT macro
Follow its suggestion and convert the code to BIT() and related macros.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 127 +--
1 file changed, 68
Hi Rob,
On Tue, 30 Jul 2024 13:36:35 -0600
Rob Herring wrote:
...
> > +
> > +patternProperties:
> > + '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
>
> Unit-addresses are typically in hex.
I thought it was more related to the reg value.
In our case, the reg value is just the channel number from 0
g
Signed-off-by: Herve Codina
---
drivers/net/wan/fsl_qmc_hdlc.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/net/wan/fsl_qmc_hdlc.c b/drivers/net/wan/fsl_qmc_hdlc.c
index 64b4bfa6fea7..8fcfbde31a1c 100644
--- a/drivers/net/wan/fsl_qmc_hdlc.
er_set_carrier+0x30/0x98
Avoid the spinlock usage and convert carrier_lock to a mutex.
Fixes: 54762918ca85 ("net: wan: fsl_qmc_hdlc: Add framer support")
Cc: sta...@vger.kernel.org
Signed-off-by: Herve Codina
---
drivers/net/wan/fsl_qmc_hdlc.c | 7 ---
1 file changed, 4 insertions(
The QUICC Engine (QE) QMC can use a firmware to have the QMC working in
'soft-qmc' mode.
Handle this optional 'soft-qmc' firmware.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 67
1 file changed, 67 insertions(+)
diff
checkpatch.pl raises the following issue
CHECK: spinlock_t definition without comment
Add the missing comments.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
be automatically freed on driver detach.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qe_common.c | 79 ++
include/soc/fsl/qe/qe.h| 22 +-
2 files changed, 100 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qe/qe_common.c b
checkpatch.pl signals the following improvement for qmc.c
CHECK: Prefer using the BIT macro
Follow its suggestion and convert the code to BIT() and related macros.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 132 +--
1 file changed, 72
initialization has no impact in the CPM1 version
of QMC.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 272da250a763..63af2608c3cd 100644
--- a/drivers/soc/fsl/qe/qmc.c
() for consistency to revert operations done
in qmc_init_xcc().
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 66 +++-
1 file changed, 45 insertions(+), 21 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index
The Freescale QMC controller driver supports both QE and CPM1.
Add the newly introduced QE files to the existing entry.
Signed-off-by: Herve Codina
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1d32d38f2247..1331bdeb7386 100644
--- a
, compared against the CPM QMC, this QE QMC does not
use a fixed area for the UCC/SCC parameters area but it uses a dynamic
area allocated and provided to the hardware at runtime.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/Kconfig | 9 +-
drivers/soc/fsl/qe/qmc.c | 209
that case.
Simply add the missing command in the commands list available in the QE
header file.
Signed-off-by: Herve Codina
---
include/soc/fsl/qe/qe.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index 629835b6c71d..8f967d15e479 100644
--- a
Current code handles the CPM1 version of QMC.
In order to prepare the support for the QUICC Engine (QE) version of
QMC, introduce qmc_version to identify versions. This will enable the
code to make the distinction between several QMC implementations.
Signed-off-by: Herve Codina
---
drivers/soc
defined for the QMC mode is CPM1 specific.
In order to prepare the support for the QE version, rename this bitfield
value to clearly identify it as CPM1 specific.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers
Current code handles CPM1 version of QMC and qmc_chan_command() is
clearly CPM1 specific.
In order to prepare the support for the QUICC Engine (QE) version,
rename qmc_chan_command() to reflect that point.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 6 +++---
1 file changed, 3
initializing resources.
- Group SCC initialisation and do this initialization when it is really
needed in the probe() sequence.
Having the QE compatible sequence in the CPM1 version does not lead to
any issue and works correctly without any regressions.
Signed-off-by: Herve Codina
---
drivers/soc
fined.
In order to prepare the support for QE version, introduce
qmc_init_resource() to initialize those resources and isolate the CPM1
specific operations in a specific function.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 47 ++--
1 file c
, introduce the qmc_data structure to define
these version specific values.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 69 ++--
1 file changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index
, compared against the CPM QMC, this QE QMC does not
use a fixed area for the UCC/SCC parameters area but it uses a dynamic
area allocated and provided to the hardware at runtime.
Last point, the QE QMC can use a firmware to have the QMC working in
'soft-qmc' mode.
Signed-off-by: He
checkpatch.pl raises the following issue
CHECK: 'transmiter' may be misspelled - perhaps 'transmitter'?
Indeed, fix it.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc
checkpatch.pl raises the following issue in several places
CHECK: Unnecessary parenthesis around ...
Remove them.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe
checkpatch.pl raises the following issues
CHECK: Please don't use multiple blank lines
CHECK: Alignment should match open parenthesis
Fix them.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/dr
QMC_TSA_MASK is a bitfield. The value defined is a specific value of
this bitfield and correspond to the use of 8bit resolution for the
routing entry.
Be accurate and rename the defined constant to reflect this point.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 8
1
TSA consumers in CPM1 implementation don't need to know about the serial
device number used by the TSA component. In QUICC Engine implementation,
this information is needed.
Improve the TSA API with tsa_serial_get_num() in order to provide this
information.
Signed-off-by: Herve C
The Freescale TSA controller driver supports both QE and CPM1.
Add the newly introduced QE files to the existing entry.
Signed-off-by: Herve Codina
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 42decde38320..1d32d38f2247 100644
--- a
against the CPM1 TSA, this QE TSA can handle up to 4 TDMs
instead of 2 and allows to configure the logic level of sync signals.
At a lower level, compared against CPM TSA implementation, some
registers are slightly different even if same features are present.
Signed-off-by: Herve Codina
Current code handles the CPM1 version of TSA. Compared against QUICC
Engine (QE) version of TSA, CPM1 SIRAM entries are slightly different.
In order to prepare the support for the QE version, clearly identify
these entries and functions handling them as CPM1 compatible.
Signed-off-by: Herve
QE version, clearly identify
SICR register as specific to CPM1 and isolate its handling done in
connect and disconnect functions.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 103 ---
1 file changed, 43 insertions(+), 60 deletions(-)
diff --git
as CPM1 compatible and isolate their handling in a CPM1
specific function.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 93 +++-
1 file changed, 54 insertions(+), 39 deletions(-)
diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
Current code handles CPM1 version of TSA.
In order to prepare the support for the QUICC Engine (QE) version of
TSA, introduce tsa_version to identify versions. This will enable the
code to make the distinction between several TSA implementations.
Signed-off-by: Herve Codina
---
drivers/soc/fsl
Loops handling the tdm array use hardcoded size and the initialization
part uses hardcoded indexes to initialize the array.
Use ARRAY_SIZE() to avoid the hardcoded size and initialize the array
using a loop.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 8
1 file changed
checkpatch.pl raises the following issues
CHECK: Please don't use multiple blank lines
CHECK: spaces preferred around that '/' (ctx:VxV)
CHECK: spaces preferred around that '+' (ctx:VxV)
CHECK: spaces preferred around that '-' (ctx:VxV)
Fix them.
Signed
The TRNSYNC feature is enabled whatever the number of time-slots used.
The feature is needed only when more than one time-slot is used.
Improve the driver enabling TRNSYNC only when it is needed.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 12 +++-
1 file changed, 11
against the CPM TSA, this QE TSA can handle
up to 4 TDMs instead of 2 and allows to configure the logic level of
sync signals.
Signed-off-by: Herve Codina
---
.../bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml | 212 ++
include/dt-bindings/soc/qe-fsl,tsa.h | 13 ++
2 files
+ MAINTAINERS update
Best regards,
Hervé
Herve Codina (36):
soc: fsl: cpm1: qmc: Update TRNSYNC only in transparent mode
soc: fsl: cpm1: qmc: Enable TRNSYNC only when needed
soc: fsl: cpm1: tsa: Fix tsa_write8()
soc: fsl: cpm1: tsa: Use BIT(), GENMASK() and FIELD_PREP() macros
soc: fsl
SISTR, SICMR and SIRP registers offset definitions are not used.
In order to avoid unneeded code, remove them.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
index
top()")
Cc: sta...@vger.kernel.org
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/qmc.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c
index 76bb496305a0..bacabf731dcb 100644
--- a/drivers/soc/fsl/qe/qmc
checkpatch.pl raises the following issue
CHECK: spinlock_t definition without comment
Add the missing comment.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c
The tsa_write8() parameter is an u32 value. This is not consistent with
the function itself. Indeed, tsa_write8() writes an 8bits value.
Be consistent and use an u8 parameter value.
Fixes: 1d4ba0b81c1c ("soc: fsl: cpm1: Add support for TSA")
Cc: sta...@vger.kernel.org
Signed-off-by: He
checkpatch.pl signals the following improvement for tsa.c
CHECK: Prefer using the BIT macro
Follow its suggestion and convert the code to BIT() and related macros.
Signed-off-by: Herve Codina
---
drivers/soc/fsl/qe/tsa.c | 127 +--
1 file changed, 68
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