Re: [RESEND PATCH v5 2/5] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo

2020-01-10 Thread James Morse
Hi Bhupesh, On 25/12/2019 19:01, Bhupesh Sharma wrote: > On 12/12/2019 04:02 PM, James Morse wrote: >> On 29/11/2019 19:59, Bhupesh Sharma wrote: >>> vabits_actual variable on arm64 indicates the actual VA space size, >>> and allows a single binary to support both 48-b

Re: [RESEND PATCH v5 5/5] Documentation/vmcoreinfo: Add documentation for 'TCR_EL1.T1SZ'

2019-12-12 Thread James Morse
Hi Bhupesh, On 29/11/2019 19:59, Bhupesh Sharma wrote: > Add documentation for TCR_EL1.T1SZ variable being added to > vmcoreinfo. > > It indicates the size offset of the memory region addressed by TTBR1_EL1 > and hence can be used for determining the vabits_actual value. used for determining ra

Re: [RESEND PATCH v5 2/5] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo

2019-12-12 Thread James Morse
Hi Bhupesh, On 29/11/2019 19:59, Bhupesh Sharma wrote: > vabits_actual variable on arm64 indicates the actual VA space size, > and allows a single binary to support both 48-bit and 52-bit VA > spaces. > > If the ARMv8.2-LVA optional feature is present, and we are running > with a 64KB page size;

Re: [PATCH RFC 6/7] arm64: kexec: no need to ClearPageReserved()

2018-12-05 Thread James Morse
page = phys_to_page(addr); > - ClearPageReserved(page); > free_reserved_page(page); > } > } > Acked-by: James Morse Thanks, James

Re: [PATCH 1/5] arm64: entry: isb in el1_irq

2018-04-06 Thread James Morse
Hi Mark, On 06/04/18 18:22, Mark Rutland wrote: > Digging a bit, I also thing that our ct_user_exit and ct_user_enter > usage is on dodgy ground today. [...] > I think similar applies to SDEI; we don't negotiate with RCU prior to > invoking handlers, which might need RCU. The arch code's __sdei

Re: [PATCH 3/5] arm64: early ISB at exit from extended quiescent state

2018-04-06 Thread James Morse
Hi Yury, On 05/04/18 18:17, Yury Norov wrote: > This series enables delaying of kernel memory synchronization > for CPUs running in extended quiescent state (EQS) till the exit > of that state. > > ARM64 uses IPI mechanism to notify all cores in SMP system that > kernel text is changed; and IPI

Re: [PATCH 1/5] arm64: entry: isb in el1_irq

2018-04-06 Thread James Morse
Hi Yury, On 05/04/18 18:17, Yury Norov wrote: > Kernel text patching framework relies on IPI to ensure that other > SMP cores observe the change. Target core calls isb() in IPI handler (Odd, if its just to synchronize the CPU, taking the IPI should be enough). > path, but not at the beginning o

Re: [PATCH] ptrace: Add compat PTRACE_{G,S}ETSIGMASK handlers

2017-07-17 Thread James Morse
Hi Michael, On 17/07/17 11:17, Michael Ellerman wrote: > James Morse writes: >> compat_ptrace_request() lacks handlers for PTRACE_{G,S}ETSIGMASK, >> instead using those in ptrace_request(). The compat variant should >> read a compat_sigset_t from userspace instead

[PATCH] ptrace: Add compat PTRACE_{G,S}ETSIGMASK handlers

2017-06-29 Thread James Morse
significant. Instead of duplicating ptrace_request()s code as a special case in the arch code, handle it here. CC: Yury Norov CC: Andrey Vagin Reported-by: Zhou Chengming Signed-off-by: James Morse Fixes: 29000caecbe87 ("ptrace: add ability to get/set signal-blocked mask") --- LTP test