On Fri, 9 Mar 2012 14:46:45 +1100
Anton Blanchard an...@samba.org wrote:
Hi Ben,
Looks like something that got fixed but the new patches from Bjorn
aren't in next yet. I'll fwd you the patch separately to apply on
top of what you have see if that helps (to confirm that's indeed the
On Thu, 23 Feb 2012 12:51:30 -0800
Bjorn Helgaas bhelg...@google.com wrote:
On Thu, Feb 23, 2012 at 12:25 PM, Jesse Barnes jbar...@virtuousgeek.org
wrote:
On Fri, 10 Feb 2012 08:35:58 +1100
Benjamin Herrenschmidt b...@kernel.crashing.org wrote:
On Thu, 2012-02-09 at 11:24 -0800, Bjorn
-by!
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
On Wed, 9 Jun 2010 16:14:10 -0700 (PDT)
Linus Torvalds torva...@linux-foundation.org wrote:
On Wed, 9 Jun 2010, Jesse Barnes wrote:
Nothing too big here; I do have a couple of fixes in the queue that
aren't included here though. I'll be pulling them together over the
next couple of days
like a good
excuse to do it. IIRC they had even thought about just dumping the
code directly into drivers/pci so that API updates won't get missed...
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing list
Linuxppc-dev
linux-next branch.
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
.
Signed-off-by: Bjorn Helgaas bjorn.helg...@hp.com
---
Applied this series, thanks Bjorn. Hopefully this one will
successfully run the linux-next gauntlet too. :)
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing list
!
ERROR: pci_bus_resource_n [drivers/pci/hotplug/shpchp.ko] undefined!
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2
when building.
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing list
Linuxppc-dev
a real effort needs to be put
in place to at least ping Benjamin and myself when changes are going
in to drivers/pci/probe.c
Ok I'll include you guys on further changes.
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing
with special platform devices?
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
currently
have all their partitions with PCI-E devices in them in FAIL state in ABAT
and our admin is out.
Yeah, generic bits look fine.
Acked-by: Jesse Barnes jbar...@virtuousgeek.org
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev
On Wed, 27 Jan 2010 16:01:21 -0800 (PST)
David Miller da...@davemloft.net wrote:
From: Benjamin Herrenschmidt b...@kernel.crashing.org
Date: Thu, 28 Jan 2010 09:00:12 +1100
On Wed, 2010-01-27 at 08:26 -0800, Jesse Barnes wrote:
Thanks Ben. Any refactoring we need to handle this stuff
(), who sets dev-pcie, is not being called on PPC
PCI code.
You mean dev-is_pcie?
Why isn't pci_scan_device calling pci_setup_device for you? That
should do the proper PCIe init depending on the device, along with
extracting other device info...
--
Jesse Barnes, Intel Open Source Technology Center
On Mon, 25 Jan 2010 12:38:49 -0800
Jesse Barnes jbar...@virtuousgeek.org wrote:
On Mon, 25 Jan 2010 11:42:29 -0200
Breno Leitao lei...@linux.vnet.ibm.com wrote:
Hello,
I found that qlge is broken on PPC, and it got broken after commit
06a1cbafb253c4c60d6a54a994887f5fbceabcc0
, thanks. Had to fix up a conflict since someone had helpfully
changed the comment from a // to a /* .. */ in cardbus.c.
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https
for-linus branch?
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
failure was my fault. I had fixed up the conflict
incorrectly. It's applied now.
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
, PCI: document PCIe fundamental
reset, or for arch specific patches, PCI/powerpc: implement support
for PCIe fundamental reset.
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https
11726640 b2ef30 build/powerpc/vmlinux-before
9354052 1693852 678424 11726328 b2edf8 build/powerpc/vmlinux-after
Also smaller on x86_64 and arm (iop13xx).
Signed-off-by: Michael Ellerman mich...@ellerman.id.au
Applied to my linux-next branch, thanks Michael.
--
Jesse Barnes, Intel Open
On Tuesday, October 21, 2008 3:33 pm Benjamin Herrenschmidt wrote:
On Tue, 2008-10-21 at 09:36 -0500, Ayman El-Khashab wrote:
Ayman, can you double check that this variant of the patch still
fixes your problem ? Thanks !
I've tried it out and it is working correctly with my devices.
On Monday, October 20, 2008 4:06 pm Benjamin Herrenschmidt wrote:
Some firmware fail to properly configure P2P bridges, leaving them
with invalid bus numbers. In some cases, this happens on some embedded
4xx boards as the result of the kernel allocating different bus space
than the firmware
On Monday, October 13, 2008 5:55 pm Benjamin Herrenschmidt wrote:
This patch adds support for legacy_io and legacy_mem files in
bus class directories in sysfs for powerpc
Signed-off-by: Benjamin Herrenschmidt [EMAIL PROTECTED]
Ok, applied this one. Should be pushing to Linus soon.
Thanks,
On Monday, October 13, 2008 7:07 am Josh Boyer wrote:
On Fri, Oct 10, 2008 at 10:39:18AM -0700, Jesse Barnes wrote:
On Thursday, October 9, 2008 7:50 pm Benjamin Herrenschmidt wrote:
This patch adds support for legacy_io and legacy_mem files in
bus class directories in sysfs for powerpc
On Thursday, October 9, 2008 7:50 pm Benjamin Herrenschmidt wrote:
This patch adds support for legacy_io and legacy_mem files in
bus class directories in sysfs for powerpc
Signed-off-by: Benjamin Herrenschmidt [EMAIL PROTECTED]
---
This is version 2, slightly different approach for getting
On Thursday, October 9, 2008 7:50 pm Benjamin Herrenschmidt wrote:
This patch adds support for legacy_io and legacy_mem files in
bus class directories in sysfs for powerpc
Signed-off-by: Benjamin Herrenschmidt [EMAIL PROTECTED]
---
Applied to linux-next, thanks.
Jesse
On Friday, October 3, 2008 2:49 am Benjamin Herrenschmidt wrote:
This adds the ability to mmap legacy IO space to the legacy_io files
in sysfs on platforms that support it. This will allow to clean up
X to use this instead of /dev/mem for legacy IO accesses such as
those performed by Int10.
On Friday, October 3, 2008 2:49 am Benjamin Herrenschmidt wrote:
+ /* WARNING: The generic code is idiotic. It gets passed a pointer
+ * to what can be a 1, 2 or 4 byte quantity and always reads that
+ * as a u32, which means that we have to correct the location of
+ * the
On Friday, October 3, 2008 2:52 pm Benjamin Herrenschmidt wrote:
On Fri, 2008-10-03 at 08:59 -0700, Jesse Barnes wrote:
Feel free to change the generic code if it makes things easier for you,
the only limitation is that we have to live within the generic sysfs
read/write functions
On Monday, August 18, 2008 6:45 pm Stephen Rothwell wrote:
Commit f46753c5e354b857b20ab8e0fe7b2579831dc369 (PCI: introduce pci_slot)
removed the need for this error path. Eliminate this warning:
drivers/pci/hotplug/rpaphp_slot.c: In function 'rpaphp_register_slot':
On Monday, July 28, 2008 5:52 pm Stephen Rothwell wrote:
Hi Jesse,
Today's linux-next build (powerpc ppc64_defconfig) failed like this:
arch/powerpc/kernel/iommu.c:54: error: static declaration of
'iommu_num_pages' follows non-static declaration
include/linux/iommu-helper.h:11: error:
On Tuesday, June 10, 2008 8:29 pm Nick Piggin wrote:
On Wednesday 11 June 2008 05:19, Jesse Barnes wrote:
On Tuesday, June 10, 2008 12:05 pm Roland Dreier wrote:
me too. That's the whole basis for readX_relaxed() and its cohorts:
we make our weirdest machines (like altix) conform
On Monday, June 09, 2008 11:56 pm Nick Piggin wrote:
So that still doesn't tell us what *minimum* level of ordering we should
provide in the cross platform readl/writel API. Some relatively sane
suggestions would be:
- as strong as x86. guaranteed not to break drivers that work on x86,
but
On Tuesday, June 10, 2008 12:05 pm Roland Dreier wrote:
me too. That's the whole basis for readX_relaxed() and its cohorts: we
make our weirdest machines (like altix) conform to the x86 norm. Then
where it really kills us we introduce additional semantics to selected
drivers that
On Monday, June 09, 2008 1:48 am Andrew Morton wrote:
At boot, using http://userweb.kernel.org/~akpm/config-g5.txt on a mac g5:
io scheduler cfq registered
proc_dir_entry '00' already registered
Call Trace:
[c0017a0fbb70] [c00120fc] .show_stack+0x58/0x1dc (unreliable)
On Friday, May 30, 2008 2:36 am Jes Sorensen wrote:
James Bottomley wrote:
The only way to guarantee ordering in the above setup, is to either
make writel() fully ordered or adding the mmiowb()'s inbetween the two
writel's. On Altix you have to go and read from the PCI brige to
ensure all
On Thursday, May 29, 2008 2:40 pm Benjamin Herrenschmidt wrote:
On Thu, 2008-05-29 at 10:47 -0400, Jes Sorensen wrote:
The only way to guarantee ordering in the above setup, is to either
make writel() fully ordered or adding the mmiowb()'s inbetween the two
writel's. On Altix you have to go
On Thursday, May 29, 2008 8:39 pm Benjamin Herrenschmidt wrote:
When Greg fixed the sysfs usage of that driver a while back, he seem
to have introduced a bug where the quotes are added around the name of
our specific sysfs files, thus breaking the user space tool.
This fixes it. Tested DLPAR
On Wednesday, February 27, 2008 4:04 pm Bjorn Helgaas wrote:
Move bridge enable from pcibios_enable_resources() to
platform_pci_enable_device() so the former matches other
architectures and can be shared.
I really like the direction of these patches. Getting PCI resources assigned
devices
On Thursday, February 28, 2008 9:31 am Grant Grundler wrote:
In general, I'm wondering if the check for device class would be
sufficient here to NOT enable PERR/SERR for graphics automatically.
While disabling PERR was the right thing for older mostly write
devices of the 1990's and early
On Monday, March 03, 2008 12:35 pm Benjamin Herrenschmidt wrote:
On Mon, 2008-03-03 at 09:59 -0800, Jesse Barnes wrote:
On Wednesday, February 27, 2008 4:04 pm Bjorn Helgaas wrote:
Move bridge enable from pcibios_enable_resources() to
platform_pci_enable_device() so the former matches
On Thursday, February 14, 2008 1:40 am Martin Mares wrote:
Hi Greg!
I have no idea, it sounds like a PPC specific thing, not anything the
PCI core does, right? So I'll add the ppc list to the cc: and ask if
anyone there has any ideas?
Unfortunately, this is not PPC specific at all --
On Thursday, August 23, 2007 12:27 am Benjamin Herrenschmidt wrote:
Of course, the normal memory barrier would usually be a
spin_unlock() or something like that, not a wmb(). In fact, I
don't think the powerpc implementation (as an example of this) will
actually synchronize with anything
Yeah, they keep threatening to use this instead, but I'm not sure
how easy it would be. Also they may have more devices/drivers to
worry about than sn2, so maybe changing over would mean too much
driver debugging (well auditing really since it's not that hard to
know where to put them).
On Wednesday, August 22, 2007 11:07 am Linus Torvalds wrote:
It really seems like it is some completely different concept from a
barrier. And it shows, on the platform where it really matters
(sn2), where the thing actually spins.
I agree that it probably isn't a write barrier per se.
44 matches
Mail list logo
