On 4/29/24 7:39 PM, Michael Ellerman wrote:
Madhavan Srinivasan writes:
When running `make -C powerpc/pmu run_tests` from top level selftests
directory, currently this error is being reported
make: Entering directory '/home/maddy/linux/tools/testing/selftests/powerpc/pmu'
Makefile:40
On 4/22/24 7:04 PM, Michael Ellerman wrote:
The pmu Makefile has grown more sub directories over the years. Rather
than open coding the rules for each subdir, use for loops.
Nice cleanup. Thanks.
Tested-by: Madhavan Srinivasan
Signed-off-by: Michael Ellerman
---
tools/testing
On 3/26/24 3:10 PM, Gautam Menghani wrote:
PAPR hypervisor has introduced three new counters in the VPA area of
LPAR CPUs for KVM L2 guest (see [1] for terminology) observability - 2
for context switches from host to guest and vice versa, and 1 counter
for getting the total time spent inside
lso remove the CFLAGS and GIT_VERSION macros from powerpc/
folder Makefile since the same is definied in flags.mk
Signed-off-by: Madhavan Srinivasan
---
tools/testing/selftests/powerpc/Makefile | 7 +--
tools/testing/selftests/powerpc/alignment/Makefile | 1 +
tools/testing
t directly,
a new rule file has been addded by the patch called "flags.mk" under
selftest/powerpc/ folder and is linked to all the Makefile of powerpc/pmu
sub-folders.
Reported-by: Sachin Sant
Signed-off-by: Madhavan Srinivasan
---
Changelog RFC:
- Rename the rule file as flags.mk
- Adde
In some powerpc/ sub-folder Makefiles, CFLAGS are
defined before lib.mk include. Clean it up by
re-ordering it to follow after the mk include.
This is needed to support sub-folders in powerpc/
buildable on its own.
Signed-off-by: Madhavan Srinivasan
---
.../selftests/powerpc/benchmarks/Makefile
older test directly,
a new rule file has been addded by the patch called "include.mk" under
selftest/powerpc/ folder and is linked to all Makefile of powerpc/pmu
sub-folders.
Signed-off-by: Madhavan Srinivasan
---
tools/testing/selftests/powerpc/include.mk | 10 ++
too
Base enablement patch to register performance monitoring
hardware support for Power11. Most of fields are copied
from power10_pmu struct for power11_pmu struct.
Signed-off-by: Madhavan Srinivasan
---
Changelog V2:
- No change
Changelog v1:
- Copied power10 struct for power11 with name change
-off-by: Madhavan Srinivasan
---
Changelog v2:
- added macro to address logical PVR to
handle compat mode PCR setting
- removed power11 functions which were
just re-direction to power10. Instead
used power10 functions as suggested.
Changelog v1
- No change
arch/powerpc/include/asm
On 2/5/24 2:13 PM, Aneesh Kumar K.V wrote:
Madhavan Srinivasan writes:
reg.h is updated with Power11 pvr. pvr_mask value of 0x0F07
means we are arch v3.1 compliant.
If it is called arch v3.1, it will conflict with.
#define PVR_ARCH_31 0x0f06
Nice catch. My bad, missed
Base enablement patch to register performance monitoring
hardware support for Power11. Most of fields are copied
from power10_pmu struct for power11_pmu struct.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Copied power10 struct for power11 with name change
arch/powerpc/perf/core
relevant
Power11 setup/restore and device tree routines.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- no change in this patch.
arch/powerpc/include/asm/cpu_setup.h | 2 ++
arch/powerpc/include/asm/cputable.h | 3 ++
arch/powerpc/include/asm/mce.h| 1 +
arch
Update the Power11 PVR to json mapfile to enable
json events. Power11 is PowerISA v3.1 compliant
and support Power10 events.
Signed-off-by: Madhavan Srinivasan
---
tools/perf/pmu-events/arch/powerpc/mapfile.csv | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/pmu-events/arch
-by: Madhavan Srinivasan
---
arch/powerpc/perf/Makefile | 3 +-
arch/powerpc/perf/core-book3s.c | 2 +
arch/powerpc/perf/internal.h| 1 +
arch/powerpc/perf/power11-events-list.h | 8 +
arch/powerpc/perf/power11-pmu.c | 475
5 files
Power11 setup/restore and device tree routines.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/cpu_setup.h | 2 ++
arch/powerpc/include/asm/cputable.h | 3 ++
arch/powerpc/include/asm/mce.h| 1 +
arch/powerpc/include/asm/mmu.h| 1 +
arch
On 10/3/23 3:16 AM, Gaurav Batra wrote:
When a device is initialized, the driver invokes dma_supported() twice - first
for streaming mappings followed by coherent mappings. For an SR-IOV device,
default window is deleted and DDW created. With vPMEM enabled, TCE mappings
are dynamically created
On 3/2/23 8:49 AM, Madhavan Srinivasan wrote:
On 3/2/23 3:35 AM, Benjamin Gray wrote:
On Wed, 2023-03-01 at 22:39 +0530, Kajol Jain wrote:
From: Madhavan Srinivasan
event.h header already includes utlis.h. Avoid including
the same explicitly in the code when event.h included.
Signed-off
On 3/2/23 3:35 AM, Benjamin Gray wrote:
On Wed, 2023-03-01 at 22:39 +0530, Kajol Jain wrote:
From: Madhavan Srinivasan
event.h header already includes utlis.h. Avoid including
the same explicitly in the code when event.h included.
Signed-off-by: Madhavan Srinivasan
As I understand
On 10/18/22 1:35 PM, Michael Ellerman wrote:
Kajol Jain writes:
Based on getPerfCountInfo v1.018 documentation, some of the
hv_gpci events got deprecated for platforms firmware that
supports counter_info_version 0x8 or above.
Patch fixes the hv_gpci event list by adding a new attribute
inator of the metric expression as a fix.
Result in powerpc box after this patch changes:
90: perf all metrics test : Ok
Looks ok, applied. Next time please try to ask others to provide a
Reviewed-by or at least an Acked-by.
Reviewed-by: Madhavan Srinivasan
I did review this patch yesterday. B
On 7/13/22 11:11 AM, Nicholas Piggin wrote:
Excerpts from Kajol Jain's message of July 11, 2022 1:49 pm:
File book3s_hv_p9_entry.c in powerpc/kvm folder consists of functions
like freeze_pmu, switch_pmu_to_guest and switch_pmu_to_host which are
specific to Performance Monitoring Unit(PMU) for
On 5/26/22 12:07 PM, Joel Stanley wrote:
When booting on a machine that uses the compat pmu driver we see this:
[0.071192] GENERIC_COMPAT performance monitor hardware support registered
Sorry that was my mistake.
I agree having it as ISAv3 is better.
Maddy
Which is a bit shouty.
lder, file is linked with thirty_two_instruction_loop() in
loop.S from top folder. Since fixed_instruction_loop.S not used, patch
removes the file.
Signed-off-by: Madhavan Srinivasan
---
.../powerpc/pmu/ebb/fixed_instruction_loop.S | 43 ---
1 file changed, 43 deletions(-)
delete m
IBM pseries platform nmem* device
performance stats using this interface.
Result from power9 pseries lpar with 2 nvdimm device:
Patchset looks fine to me.
Reviewed-by: Madhavan Srinivasan
Ex: List all event by perf list
command:# perf list nmem
nmem0/cache_rh_cnt
On 10/21/21 11:03 PM, Nathan Lynch wrote:
Nicholas Piggin writes:
Excerpts from Athira Rajeev's message of July 11, 2021 10:25 pm:
During Live Partition Migration (LPM), it is observed that perf
counter values reports zero post migration completion. However
'perf stat' with workload
On 8/16/21 12:59 PM, Nicholas Piggin wrote:
Interrupt handling code would like to know whether perf is enabled, to
know whether it should enable MSR[EE] to improve PMI coverage.
Cc: Madhavan Srinivasan
Cc: Athira Rajeev
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/hw_irq.h
On 8/16/21 12:26 PM, Christophe Leroy wrote:
Le 16/08/2021 à 08:44, kajoljain a écrit :
On 8/14/21 6:14 PM, Michael Ellerman wrote:
Christophe Leroy writes:
Le 13/08/2021 à 10:24, Kajol Jain a écrit :
Incase of random sampling, there can be scenarios where SIAR is not
latching sample
On 8/6/21 4:08 PM, Nicholas Piggin wrote:
Excerpts from Madhavan Srinivasan's message of August 6, 2021 5:33 pm:
On 7/26/21 9:19 AM, Nicholas Piggin wrote:
It can be useful in simulators (with very constrained environments)
to allow some PMCs to run from boot so they can be sampled directly
On 7/26/21 9:19 AM, Nicholas Piggin wrote:
It can be useful in simulators (with very constrained environments)
to allow some PMCs to run from boot so they can be sampled directly
by a test harness, rather than having to run perf.
A previous change freezes counters at boot by default, so
On 7/14/21 6:09 PM, Nicholas Piggin wrote:
Excerpts from Nicholas Piggin's message of July 12, 2021 12:41 pm:
Excerpts from Athira Rajeev's message of July 10, 2021 12:50 pm:
On 22-Jun-2021, at 4:27 PM, Nicholas Piggin wrote:
KVM PMU management code looks for particular frozen/disabled
On 7/2/21 5:57 AM, Nicholas Piggin wrote:
Excerpts from Madhavan Srinivasan's message of July 1, 2021 11:17 pm:
On 6/22/21 4:27 PM, Nicholas Piggin wrote:
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
On 6/22/21 4:27 PM, Nicholas Piggin wrote:
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term
On 6/16/21 11:56 AM, Christophe Leroy wrote:
Le 16/06/2021 à 05:40, Athira Rajeev a écrit :
On 16-Jun-2021, at 8:53 AM, Madhavan Srinivasan
wrote:
On 6/15/21 8:35 PM, Christophe Leroy wrote:
For your information, I'm getting the following Oops. Detected with
5.13-rc6, it also oopses
On 6/15/21 8:35 PM, Christophe Leroy wrote:
For your information, I'm getting the following Oops. Detected with
5.13-rc6, it also oopses on 5.12 and 5.11.
Runs ok on 5.10. I'm starting bisecting now.
Thanks for reporting, got the issue. What has happened in this case is
that, pmu device
architected. The
Yeah as you pointed, this was aimed at IBM system implementations.
Thanks for the patch and patch looks fine to me.
Reviewed-by: Madhavan Srinivasan
I can send a follow up patch to return EINVAL for a non-zero value
other than pmc and pmcsel filed via check_attr_config
to freeze counting based on the Control Register
CTRL[RUN] state. CTRL[RUN] is not set when idle task is
running. Patch adds a check for event attr.exclude_idle to
set MMCR2[FCnWAIT] bit.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/isa207-common.c | 3 +++
arch/powerpc/perf/isa207-common.
for a given platform.
Signed-off-by: Madhavan Srinivasan
---
Changelog v3:
-Made the check_attr_config() to be called for all event type of instead
only for raw event type.
Changelog v2:
-Fixed commit message
Changelog v1:
-Fixed commit message and in-code comments
arch/powerpc/include/asm/perf
Add platform specific attr.config value checks. Patch
includes checks for both power9 and power10.
Signed-off-by: Madhavan Srinivasan
---
Changelog v3:
- No changes
Changelog v2:
- Changed function name as suggested.
- Added name of source document referred for reserved values
Changelog v1
On 4/7/21 5:08 PM, Michael Ellerman wrote:
Madhavan Srinivasan writes:
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 6817331e22ff..c6eeb4fdc5fd 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1958,6 +1958,20
On 3/25/21 6:36 PM, Arnaldo Carvalho de Melo wrote:
Em Wed, Mar 24, 2021 at 10:05:23AM +0530, Madhavan Srinivasan escreveu:
On 3/22/21 8:27 PM, Athira Rajeev wrote:
Performance Monitoring Unit (PMU) registers in powerpc provides
information on cycles elapsed between different stages
for a given platform.
"check_attr_config" is valid only for raw event type.
Signed-off-by: Madhavan Srinivasan
---
Changelog v2:
-Fixed commit message
Changelog v1:
-Fixed commit message and in-code comments
arch/powerpc/include/asm/perf_event_server.h | 6 ++
arch/powerpc/perf/c
Add platform specific attr.config value checks. Patch
includes checks for both power9 and power10.
Signed-off-by: Madhavan Srinivasan
---
Changelog v2:
- Changed function name as suggested.
- Added name of source document referred for reserved values
Changelog v1:
- No changes
arch/powerpc
structure.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Athira Rajeev
---
arch/powerpc/include/asm/perf_event_server.h | 2 +-
arch/powerpc/perf/core-book3s.c | 4 ++--
arch/powerpc/perf/isa207-common.c| 29
On 3/10/21 6:46 PM, Alexey Kardashevskiy wrote:
On 26/02/2021 17:50, Madhavan Srinivasan wrote:
Add platform specific attr.config value checks. Patch
includes checks for both power9 and power10.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- No changes.
arch/powerpc/perf/isa207
On 2/26/21 7:33 PM, Paul A. Clarke wrote:
Another drive-by review... just some minor nits, below...
On Fri, Feb 26, 2021 at 12:20:24PM +0530, Madhavan Srinivasan wrote:
Introduce code to support the checking of attr.config* for
values which are reserved for a given platform.
Performance
for memory events to use issue
to complete.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
We should also CC stable to include this fix?
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/powe
fixes the functions to handle type value 7 for
CPU_FTR_ARCH_31.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev
---
arch/powerpc/perf/isa207-com
Add platform specific attr.config value checks. Patch
includes checks for both power9 and power10.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- No changes.
arch/powerpc/perf/isa207-common.c | 41 +++
arch/powerpc/perf/isa207-common.h | 2 ++
arch/powerpc
attr.config* values for a given platform.
"check_attr_config" is valid only for raw event type.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
-Fixed commit message and in-code comments
arch/powerpc/include/asm/perf_event_server.h | 6 ++
arch/powerpc/perf/core-book3s.c
On 2/24/21 8:17 PM, Paul A. Clarke wrote:
On Wed, Feb 24, 2021 at 07:58:39PM +0530, Madhavan Srinivasan wrote:
Introduce code to support the checking of attr.config* for
values which are reserved for a given platform.
Performance Monitoring Unit (PMU) configuration registers
have fileds
Add platform specific attr.config value checks. Patch
includes checks for power9 and power10 platforms.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/isa207-common.c | 41 +++
arch/powerpc/perf/isa207-common.h | 2 ++
arch/powerpc/perf/power10-pmu.c
for raw event type.
Suggested-by: Alexey Kardashevskiy
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/perf_event_server.h | 6 ++
arch/powerpc/perf/core-book3s.c | 12
2 files changed, 18 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event_server
event]
hv_24x7/TOD,chip=?/[Kernel PMU event]
..
Demsg:
[0.000357] printk: console [hvc0] enabled
[0.808592] hv-24x7: read 1530 catalog entries, created 509 event attrs
(0 failures), 275 descs
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Kajol
On 12/17/20 5:02 PM, Kajol Jain wrote:
hv_24x7 performance monitoring unit creates list of supported events
from the event catalog obtained via HCALL. hv_24x7 catalog could also
contain invalid or dummy events (with names like FREE_ or CPM_FREE_ so
Can you also include " RESERVED_NEST*" as
I saw were fixed by
https://github.com/aik/linux/commit/17899eaf88d689 but it is hardly a
replacement. Thanks,
sorry missed this. Will look at this again. Since we will need
generation specific checks for the reserve field.
Maddy
On 04/06/2020 02:34, Madhavan Srinivasan wrote:
On 6/2/
On 11/24/20 10:21 AM, Namhyung Kim wrote:
Hello,
On Mon, Nov 23, 2020 at 8:00 PM Michael Ellerman wrote:
Namhyung Kim writes:
Hi Peter and Kan,
(Adding PPC folks)
On Tue, Nov 17, 2020 at 2:01 PM Namhyung Kim wrote:
Hello,
On Thu, Nov 12, 2020 at 4:54 AM Liang, Kan wrote:
On
On 10/22/20 6:55 AM, Michael Ellerman wrote:
Christophe Leroy writes:
Le 21/10/2020 à 10:53, Madhavan Srinivasan a écrit :
In power10 DD1, there is an issue where the
Sampled Instruction Address Register (SIAR)
not latching to the sampled address during
random sampling. This results
In power10 DD1, there is an issue where the
Sampled Instruction Address Register (SIAR)
not latching to the sampled address during
random sampling. This results in value of 0s
in the SIAR. Patch adds a check to use regs->nip
when SIAR is zero.
Signed-off-by: Madhavan Srinivasan
---
arch/powe
for marked
events. Hence add a check to use the address in Sampled Instruction Address
Register (SIAR) to identify the privilege level.
Signed-off-by: Athira Rajeev
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/core-book3s.c | 14 ++
1 file changed, 14 insertions(+)
diff
Control Register (MMCR2). Patch adds a check to drop
these samples at such conditions.
Signed-off-by: Athira Rajeev
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/core-book3s.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc
if the SIAR_VALID bit is set.
So drop the check for SIAR_VALID and return true always incase of
power10 DD1.
Signed-off-by: Athira Rajeev
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Drop the check for SIER[CMPL] and retur true instead
- Made changes to commit message
arch/powerpc
by: Athira Rajeev
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/perf_event_server.h | 1 +
arch/powerpc/perf/power10-pmu.c | 6 ++
2 files changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event_server.h
b/arch/powerpc/include/asm/perf_event_serv
to 8bits. Patch fixes the current
code to modify the MMCRA[TECM] extraction macro to handle this changes.
Fixes: 170a315f41c64 ('powerpc/perf: Support to export MMCRA[TEC*] field to
userspace')
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Fixed the commit message
- Fixed the condition check
On 10/13/20 9:28 PM, Michal Suchánek wrote:
On Tue, Oct 13, 2020 at 06:27:05PM +0530, Madhavan Srinivasan wrote:
On 10/12/20 4:59 PM, Michal Suchánek wrote:
Hello,
On Mon, Oct 12, 2020 at 04:01:28PM +0530, Madhavan Srinivasan wrote:
Power9 and isa v3.1 has 7bit mantissa field for Threshold
On 10/12/20 4:59 PM, Michal Suchánek wrote:
Hello,
On Mon, Oct 12, 2020 at 04:01:28PM +0530, Madhavan Srinivasan wrote:
Power9 and isa v3.1 has 7bit mantissa field for Threshold Event Counter
^^^ Shouldn't his be 3.0?
My bad, What I meant was
Power9, ISA v3.0 and ISA
to 8bits. Patch fixes the current code to modify the MMCRA[TECM]
extraction macro to handling this changes.
Fixes: 170a315f41c64 ('powerpc/perf: Support to export MMCRA[TEC*] field to
userspace')
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/isa207-common.c | 3 +++
arch/powerpc/perf
constraints
which are not relevant for it.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
we need to CC this in Stable too.
Fixes: 7ffd948 ("powerpc/perf: factor out power8 pmu functions")
Signed-off-by: Athira Rajeev
---
Changes in v2:
- Added a block comment in th
. Should it be static?
They're already declared in internal.h, so just make sure all the C
files include that directly or indirectly.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Michael Ellerman
---
arch/powerpc/perf/isa207-common.h | 2 ++
arch/powerpc/perf/power10-pmu.c | 1
SLB/TLBs if we get SLB/TLB machine
check errors on power8")
Fixes: 7b9f71f974a1 ("powerpc/64s: POWER9 machine check handler")
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/cputable.h | 5 +
arch/powerpc/include/asm/mce.h | 7 +++
arch/powerpc/kernel
able entry. But in VMs we still rely on the raw cputable entry to
set the correct values for the PMU related fields.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/kernel/cputable.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/powerpc/kernel/cputable.c b/ar
able entry. But in VMs we still rely on the raw cputable entry to
set the correct values for the PMU related fields.
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Fixed function undeclared compiler error.
arch/powerpc/kernel/cputable.c | 20
1 file changed, 20
patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Madhavan-Srinivasan/powerpc-Add-POWER10-raw-mode-cputable-entry/20200814-120142
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
able entry. But in VMs we still rely on the raw cputable entry to
set the correct values for the PMU related fields.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/kernel/cputable.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/powerpc/kernel/cputable.c b/ar
fine to me.
Reviewed-by: Madhavan Srinivasan
Fixes: 9908c826d5ed ("Add Power10 PMU feature to DT CPU features")
Signed-off-by: Athira Rajeev
Suggested-by: Michael Ellerman
---
arch/powerpc/include/asm/reg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch
On 7/22/20 10:24 AM, Paul Mackerras wrote:
On Wed, Jul 22, 2020 at 07:39:26AM +0530, Athira Rajeev wrote:
On 21-Jul-2020, at 9:24 AM, Paul Mackerras wrote:
On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote:
Currently `kvm_vcpu_arch` stores all Monitor Mode Control registers
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Changed check to use CPU_FTR_ARCH_31
arch/powerpc/include/asm/imc-pmu.h | 5 +
arch/powerpc/perf/imc-pmu.c| 29 -
2 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm
in kernel to use these bits to set the cpumode for
each sample.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Anju T Sudhakar
---
arch/powerpc/include/asm/imc-pmu.h | 5 +
arch
the number of perf command
line parameters (will avoid "-C" option in the perf tool
command line). It can also notify the user which is
the current cpu used to retrieve the counter data.
command:# cat /sys/devices/hv_24x7/interface/cpumask
0
Reviewed-by: Madhavan Srinivasan
On 7/8/20 2:29 PM, Kajol Jain wrote:
Patch here adds a cpumask attr to hv_24x7 pmu along with ABI documentation.
Primary use to expose the cpumask is for the perf tool which has the
capability to parse the driver sysfs folder and understand the
cpumask file. Having cpumask file will reduce
On 7/7/20 10:26 AM, Michael Ellerman wrote:
Madhavan Srinivasan writes:
On 7/6/20 8:43 AM, Michael Ellerman wrote:
Kajol Jain writes:
Patch here adds cpu hotplug functions to hv_24x7 pmu.
A new cpuhp_state "CPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE" enum
is added.
The onlin
On 7/6/20 8:43 AM, Michael Ellerman wrote:
Kajol Jain writes:
Patch here adds cpu hotplug functions to hv_24x7 pmu.
A new cpuhp_state "CPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE" enum
is added.
The online callback function updates the cpumask only if its
empty. As the primary intention of adding
On 6/24/20 4:26 PM, Gautham R Shenoy wrote:
Hi Kajol,
On Wed, Jun 24, 2020 at 03:47:54PM +0530, Kajol Jain wrote:
Patch here adds a cpumask attr to hv_24x7 pmu along with ABI documentation.
command:# cat /sys/devices/hv_24x7/cpumask
0
Since this sysfs interface is read-only, and the user
d-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/perf_event.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event.h
b/arch/powerpc/include/asm/perf_event.h
index eed3954082fa..1e8b2e1ec1db 100644
--- a/arch/powerpc/include/asm/perf_event.h
+++ b
On 6/10/20 8:37 PM, Oleg Nesterov wrote:
Hi,
looks like this patch was forgotten.
yep, I missed this. But mpe did have comments for the patch.
https://lkml.org/lkml/2019/9/19/107
Maddy
Do you think this should be fixed or should we document that
PTRACE_GETREGS is not consistent with
s add a NULL pointer check for bhrb_filter_map() which behaves as if
the callback returned an error.
This does not add the same check for config_bhrb() as the only caller
checks for cpuhw->bhrb_users which remains zero if bhrb_filter_map==0.
Changes looks fine.
Reviewed-by: Madhavan Srinivasan
T
to the kernel to capture the extended registers
in each sample. Hence decide the mask value based on the processor
version.
Signed-off-by: Anju T Sudhakar
[Decide extended mask at run time based on platform]
Signed-off-by: Athira Rajeev
Reviewed-by: Madhavan Srinivasan
---
tools/arch/powerpc/include
except for couple minor nits (extra tabs and newline
issue).
Reviewed-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/perf_event_server.h | 8 +++
arch/powerpc/include/uapi/asm/perf_regs.h| 14 +++-
arch/powerpc/perf/core-book3s.c | 1 +
arch/powerpc/perf
On 5/19/20 11:45 AM, Athira Rajeev wrote:
From: Anju T Sudhakar
Add support for perf extended register capability in powerpc.
The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the
PMU which support extended registers. The generic code define the mask
of extended registers
On 4/29/20 11:34 AM, Anju T Sudhakar wrote:
The capability flag PERF_PMU_CAP_EXTENDED_REGS, is used to indicate the
PMU which support extended registers. The generic code define the mask
of extended registers as 0 for non supported architectures.
Add support for extended registers in POWER9
ips values.
Changes looks fine to me.
Reviewed-by: Madhavan Srinivasan
Signed-off-by: Kajol Jain
---
arch/powerpc/platforms/pseries/mobility.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/mobility.c
b/arch/powerpc/platforms/pseries/mobili
On 3/27/20 12:06 PM, Kajol Jain wrote:
To expose the system dependent parameter like total number of
sockets and numbers of chips per socket, patch adds two sysfs files.
"sockets" and "chips" are added to /sys/devices/hv_24x7/interface/
of the "hv_24x7" pmu.
Signed-off-by: Kajol Jain
---
69997 22
hv_24x7/PM_MCS01_128B_RD_DISP_PORT01,chip=0/
Signed-off-by: Kajol Jain
Suggested-by: Sukadev Bhattiprolu
Tested-by: Madhavan Srinivasan
---
arch/powerpc/perf/hv-24x7.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/
values like number of sockets and chips per socket.
Rtas_call with token "PROCESSOR_MODULE_INFO"
is used to get these values.
Patch looks good to me.
Reviewed-by: Madhavan Srinivasan
Sub-sequent patch exports these values via sysfs.
Patch also make these parameters default to 1.
peterz,
Can you please help. Is it okay to use PERF_SAMPLE_RAW to expose
the pipeline stall details and
add tool side infrastructure to handle the PERF_SAMPLE_RAW for cpu-pmu
samples.
Maddy
On 4/20/20 12:39 PM, Madhavan Srinivasan wrote:
On 3/27/20 1:18 AM, Kim Phillips wrote:
On 3
On 3/27/20 1:18 AM, Kim Phillips wrote:
On 3/26/20 5:19 AM, maddy wrote:
On 3/18/20 11:05 PM, Kim Phillips wrote:
Hi Maddy,
On 3/17/20 1:50 AM, maddy wrote:
On 3/13/20 4:08 AM, Kim Phillips wrote:
On 3/11/20 11:00 AM, Ravi Bangoria wrote:
On 3/6/20 3:36 AM, Kim Phillips wrote:
On
in a CONFIG_PSERIES.
Patch adds two things here. 1) An inline ppc_get_pmu_inuse() to get
the pmu_inuse value and 2)check in perf_event_print_debug() before
dumping the PMU SPRs.
ppc_get_pmu_inuse() is based on ppc_set_pmu_inuse() and includes same
CONFIG_ checks.
Signed-off-by: Madhavan Srinivasan
---
Changelog
the pmu_inuse flag to avoid any overflow scenarios.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/core-book3s.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index a934e8c8a9b8..6e35bf9ff80a 100644
--- a/arch/powerpc/perf/core
This patch disables trace_imc pmu unit, but will
be re-enabled at a later stage with a fix patchset.
Fixes: 012ae244845f1 ('powerpc/perf: Trace imc PMU functions')
Signed-off-by: Madhavan Srinivasan
---
Changelog v1:
- Added fixes and signed-off by.
arch/powerpc/platforms/powernv/opal-imc.c | 7 +
When a root user or a user with CAP_SYS_ADMIN
privilege use trace_imc performance monitoring
unit events, to monitor application or KVM threads,
may result in a checkstop (System crash). Reason
being frequent switch of the "trace/accumulation"
mode of In-Memory Collection hardware.
This patch
pmu_inuse flag is part of lppaca struct which notifies the hypervisor
whether guest/partition is using PMUs. This provides a hint for
save/restore of PMU registers. Currently perf_event_print_debug()
does not check for pmu_inuse flag and it is not safe to use it to
dump PMU SPRs in a
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