On Fri, Aug 15, 2025 at 11:07:42AM GMT, Niklas Cassel wrote:
> Hello Mani,
>
> Sorry for the delayed reply.
> I just came back from vacation.
>
> On Thu, Jul 24, 2025 at 11:00:05AM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Jul 18, 2025 at 12:39:50PM GMT, Niklas Ca
On Thu, Aug 28, 2025 at 01:01:51PM GMT, Brian Norris wrote:
> On Tue, Jul 15, 2025 at 07:51:03PM +0530, Manivannan Sadhasivam via B4 Relay
> wrote:
> > Hi,
> >
> > Currently, in the event of AER/DPC, PCI core will try to reset the slot
> > (Root
> > Port) and
On Fri, Jul 18, 2025 at 12:39:50PM GMT, Niklas Cassel wrote:
> On Fri, Jul 18, 2025 at 12:28:44PM +0200, Niklas Cassel wrote:
> > On Tue, Jul 15, 2025 at 07:51:03PM +0530, Manivannan Sadhasivam via B4
> > Relay wrote:
> > 2) Testing link down reset:
> >
> >
From: Manivannan Sadhasivam
The PCIe link can go down under circumstances such as the device firmware
crash, link instability, etc... When that happens, the PCIe Root Port needs
to be reset to make it operational again. Currently, the driver is not
handling the link down event, due to which the
alling reset_slot() callback from pcie_do_recovery() to
pcibios_reset_secondary_bus()
- Link to v1:
https://lore.kernel.org/r/20250404-pcie-reset-slot-v1-0-98952918b...@linaro.org
Signed-off-by: Manivannan Sadhasivam
---
Manivannan Sadhasivam (3):
PCI/ERR: Add support for resetting the R
From: Manivannan Sadhasivam
The PCI link, when down, needs to be recovered to bring it back. But on
some platforms, that cannot be done in a generic way as link recovery
procedure is platform specific. So add a new API
pci_host_handle_link_down() that could be called by the host bridge drivers
Mallawa
[mani: rebased on top of the new version of reset_root_port series]
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/Kconfig| 1 +
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 91 ++-
2 files changed, 90 insertions(+), 2 deletions
From: Manivannan Sadhasivam
Some host bridge devices require resetting the Root Ports in a platform
specific way to recover them from error conditions such as Fatal AER
errors, Link Down etc... So introduce pci_host_bridge::reset_root_port()
callback and call it from pcibios_reset_secondary_bus
On Tue, Jul 15, 2025 at 10:16:27AM GMT, Lukas Wunner wrote:
> On Tue, Jul 15, 2025 at 01:29:18PM +0530, Manivannan Sadhasivam wrote:
> > --- a/drivers/pci/pci.c
> > +++ b/drivers/pci/pci.c
> > @@ -4964,7 +4964,19 @@ void pci_reset_secondary_bus(struct pci_dev *dev)
&
From: Manivannan Sadhasivam
The PCI link, when down, needs to be recovered to bring it back. But on
some platforms, that cannot be done in a generic way as link recovery
procedure is platform specific. So add a new API
pci_host_handle_link_down() that could be called by the host bridge drivers
Mallawa
[mani: rebased on top of the new version of reset_root_port series]
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/Kconfig| 1 +
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 91 ++-
2 files changed, 90 insertions(+), 2 deletions
From: Manivannan Sadhasivam
Some host bridge devices require resetting the Root Ports in a platform
specific way to recover them from error conditions such as Fatal AER
errors, Link Down etc... So introduce pci_host_bridge::reset_root_port
callback and call it from pcibios_reset_secondary_bus
-pcie-reset-slot-v2-0-efe76b278...@linaro.org
Changes in v2:
- Moved calling reset_slot() callback from pcie_do_recovery() to
pcibios_reset_secondary_bus()
- Link to v1:
https://lore.kernel.org/r/20250404-pcie-reset-slot-v1-0-98952918b...@linaro.org
Signed-off-by: Manivannan Sadhasivam
---
Maniva
On Mon, Jul 07, 2025 at 01:29:22PM GMT, Niklas Cassel wrote:
> + Mani's kernel.org email.
>
> On Mon, Jul 07, 2025 at 01:05:39PM +0200, Niklas Cassel wrote:
> > Hello Mani,
> >
> > On Fri, May 30, 2025 at 09:39:28PM +0530, Manivannan Sadhasivam wrote:
> >
ure atomicity. It just provides
a helper to avoid code duplication for RMW kind of operations. Nothing
guarantees the function to be atomic.
> Signed-off-by: Hans Zhang <18255117...@163.com>
But the change LGTM. With the above wording corrected,
Acked-by: Manivannan Sadhasivam
- Ma
On Sat, May 17, 2025 at 12:52:23AM +0800, Hans Zhang wrote:
> From: Hans Zhang
>
> Change pcie_aer_disable variable to bool and update pci_no_aer()
> to set it to true. Improves code readability and aligns with modern
> kernel practices.
>
> Signed-off-by: Hans Zhang
Applied to pci/misc!
- Ma
On Sun, Mar 02, 2025 at 07:43:41PM -0800, Sathyanarayanan Kuppuswamy wrote:
>
> On 2/16/25 6:42 PM, Shuai Xue wrote:
> > The AER driver has historically avoided reading the configuration space of
> > an endpoint or RCiEP that reported a fatal error, considering the link to
> > that device unreliab
On Mon, Feb 17, 2025 at 10:42:17AM +0800, Shuai Xue wrote:
> The current implementation of pcie_do_recovery() assumes that the
> recovery process is executed on the device that detected the error.
s/on/for
> However, the DPC driver currently passes the error port that experienced
> the DPC event
On Tue, Mar 04, 2025 at 07:07:05AM +, 孙利斌_Dio wrote:
> [EXTERNAL EMAIL]
>
> From 5fc7b1a9e0f0bcfa14068c6358019ed1e3ffc6c6 Mon Sep 17 00:00:00 2001
> From: "dio.sun"
> Date: Wed, 26 Feb 2025 08:54:49 +
> Subject: [PATCH] AER: PCIE CTO recovery handle fix
>
Looks like you forwarded this p
On Fri, May 30, 2025 at 06:34:04AM -0500, Bjorn Helgaas wrote:
> On Fri, May 30, 2025 at 09:16:59AM +0530, Manivannan Sadhasivam wrote:
> > On Wed, May 28, 2025 at 05:35:00PM -0500, Bjorn Helgaas wrote:
> > > On Thu, May 08, 2025 at 12:40:33PM +0530, Manivannan Sadhasivam wrot
On Wed, May 28, 2025 at 05:35:00PM -0500, Bjorn Helgaas wrote:
> On Thu, May 08, 2025 at 12:40:33PM +0530, Manivannan Sadhasivam wrote:
> > The PCI link, when down, needs to be recovered to bring it back. But that
> > cannot be done in a generic way as link recovery procedure
On Sat, May 17, 2025 at 12:55:14AM +0800, Hans Zhang wrote:
> The following series introduces a new kernel command-line option aer_panic
> to enhance error handling for PCIe Advanced Error Reporting (AER) in
> mission-critical environments. This feature ensures deterministic recover
> from fatal PC
On Wed, May 14, 2025 at 11:52:13AM +0530, Krishna Chaitanya Chundru wrote:
>
>
> On 5/8/2025 12:40 PM, Manivannan Sadhasivam wrote:
> > The PCIe link can go down under circumstances such as the device firmware
> > crash, link instability, etc... When that happens, the PCIe
On Wed, May 14, 2025 at 12:00:11PM +0530, Krishna Chaitanya Chundru wrote:
>
>
> On 5/8/2025 12:40 PM, Manivannan Sadhasivam wrote:
> > The PCI link, when down, needs to be recovered to bring it back. But that
> > cannot be done in a generic way as link recovery procedure is
On Thu, 08 May 2025 12:40:29 +0530, Manivannan Sadhasivam wrote:
> Currently, in the event of AER/DPC, PCI core will try to reset the slot and
> its
> subordinate devices by invoking bridge control reset and FLR. But in some
> cases like AER Fatal error, it might be necessary to res
On Fri, May 09, 2025 at 02:11:00PM +0800, Ethan Zhao wrote:
>
>
> On 5/8/2025 3:10 PM, Manivannan Sadhasivam wrote:
> > A PCI device is just another peripheral in a system. So failure to
> > recover it, must not result in a kernel panic. So remove the TODO which
&g
On Thu, Apr 24, 2025 at 10:31:00AM +0530, Manivannan Sadhasivam wrote:
> On Fri, Apr 18, 2025 at 08:11:47AM +0530, Krishna Chaitanya Chundru wrote:
> >
> >
> > On 4/17/2025 10:46 PM, Manivannan Sadhasivam via B4 Relay wrote:
> > > From: Manivannan Sadhasivam
>
A PCI device is just another peripheral in a system. So failure to
recover it, must not result in a kernel panic. So remove the TODO which
is quite misleading.
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/pcie/err.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/pci/pcie
pci_host_bridge::reset_slot()' callback to
reset the slot in a platform specific way. So implement the callback to
reset the slot by first resetting the PCIe core, followed by reinitializing
the resources and then finally starting the link again.
Signed-off-by: Manivannan Sadhasivam
---
driver
ill be broadcasted to the bridge and the downstream devices
indicating successful link recovery.
In case if the AER support is not enabled in the kernel, only
pci_bus_error_reset() will be called for each slots as there is no way we
could inform the drivers about link recovery.
Signed-off-
register. For the error recovery to
succeed (if AER is enabled), all the drivers in the bridge hierarchy should have
the 'err_handlers' populated. Otherwise, the link recovery will fail.
[1]
https://lore.kernel.org/linux-pci/20250221172309.120009-1-manivannan.sadhasi...@linaro.org
S
x86/ACPI platforms).
Suggested-by: Lukas Wunner
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/Kconfig| 8
drivers/pci/controller/dwc/pcie-hisi.c| 1 +
drivers/pci/controller/pci-host-common.c | 6 --
drivers/pci/controller
; callback is responsible for resetting the given slot
referenced by the 'pci_dev' pointer in a platform specific way and bring it
back to the working state if possible. If any error occurs during the slot
reset operation, relevant errno should be returned.
Signed-off-by: Manivannan Sadh
On Mon, May 05, 2025 at 05:05:10PM +0200, Niklas Cassel wrote:
> Hello Mani,
>
> On Thu, Apr 17, 2025 at 10:46:31PM +0530, Manivannan Sadhasivam via B4 Relay
> wrote:
> > @@ -1571,6 +1652,9 @@ static irqreturn_t qcom_pcie_global_irq_thread(int
&
On Thu, Apr 24, 2025 at 10:41:24AM +0530, Krishna Chaitanya Chundru wrote:
>
>
> On 4/24/2025 10:30 AM, Manivannan Sadhasivam wrote:
> > On Fri, Apr 18, 2025 at 08:11:47AM +0530, Krishna Chaitanya Chundru wrote:
> > >
> > >
> > > On 4/17/2025 10:46 PM
On Fri, Apr 18, 2025 at 08:11:47AM +0530, Krishna Chaitanya Chundru wrote:
>
>
> On 4/17/2025 10:46 PM, Manivannan Sadhasivam via B4 Relay wrote:
> > From: Manivannan Sadhasivam
> >
> > The PCIe link can go down under circumstances such as the device firmware
>
From: Manivannan Sadhasivam
The PCIe link can go down under circumstances such as the device firmware
crash, link instability, etc... When that happens, the PCIe slot needs to
be reset to make it operational again. Currently, the driver is not
handling the link down event, due to which the users
From: Manivannan Sadhasivam
This common library will be used as a placeholder for helper functions
shared by the host controller drivers. This avoids placing the host
controller drivers specific helpers in drivers/pci/*.c, to avoid enlarging
the kernel Image on platforms that do not use host
register. For the error recovery to
succeed (if AER is enabled), all the drivers in the bridge hierarchy should have
the 'err_handlers' populated. Otherwise, the link recovery will fail.
[1]
https://lore.kernel.org/linux-pci/20250221172309.120009-1-manivannan.sadhasi...@linaro.org
Si
From: Manivannan Sadhasivam
Some host bridge devices require resetting the slots in a platform specific
way to recover them from error conditions such as Fatal AER errors, Link
Down etc... So introduce pci_host_bridge::reset_slot callback and call it
from pcibios_reset_secondary_bus() if
From: Manivannan Sadhasivam
A PCI device is just another peripheral in a system. So failure to
recover it, must not result in a kernel panic. So remove the TODO which
is quite misleading.
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/pcie/err.c | 1 -
1 file changed, 1 deletion
From: Manivannan Sadhasivam
The PCI link, when down, needs to be recovered to bring it back. But that
cannot be done in a generic way as link recovery procedure is specific to
host bridges. So add a new API pci_host_handle_link_down() that could be
called by the host bridge drivers when the link
On Thu, Apr 17, 2025 at 02:41:55PM +0530, Krishna Chaitanya Chundru wrote:
>
>
> On 4/17/2025 1:24 PM, Manivannan Sadhasivam wrote:
> > On Wed, Apr 16, 2025 at 11:21:49PM +0530, Krishna Chaitanya Chundru wrote:
> > >
> > >
> > > On 4/16/2025 9:59 PM
On Wed, Apr 16, 2025 at 11:21:49PM +0530, Krishna Chaitanya Chundru wrote:
>
>
> On 4/16/2025 9:59 PM, Manivannan Sadhasivam via B4 Relay wrote:
> > From: Manivannan Sadhasivam
> >
> > The PCI link, when down, needs to be recovered to bring it back. But that
> >
On Wed, Apr 16, 2025 at 06:57:11PM +0200, Lukas Wunner wrote:
> On Wed, Apr 16, 2025 at 09:59:05PM +0530, Manivannan Sadhasivam via B4 Relay
> wrote:
> > --- a/drivers/pci/pcie/err.c
> > +++ b/drivers/pci/pcie/err.c
> > @@ -270,3 +270,30 @@ pci_ers_result_t pcie_do_reco
On Thu, Apr 17, 2025 at 02:23:26AM +0200, Lukas Wunner wrote:
> On Wed, Apr 16, 2025 at 08:34:21PM +0530, Manivannan Sadhasivam wrote:
> > I don't think it is possible to get rid of the powerpc version. It has
> > its own pci_dev::sysdata pointing to 'struct pci_control
From: Manivannan Sadhasivam
The PCIe link can go down under circumstances such as the device firmware
crash, link instability, etc... When that happens, the PCIe slot needs to
be reset to make it operational again. Currently, the driver is not
handling the link down event, due to which the users
From: Manivannan Sadhasivam
The PCI link, when down, needs to be recovered to bring it back. But that
cannot be done in a generic way as link recovery procedure is specific to
host bridges. So add a new API pci_host_handle_link_down() that could be
called by the host bridge drivers when the link
From: Manivannan Sadhasivam
A PCI device is just another peripheral in a system. So failure to
recover it, must not result in a kernel panic. So remove the TODO which
is quite misleading.
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/pcie/err.c | 1 -
1 file changed, 1 deletion
From: Manivannan Sadhasivam
Some host bridge devices require resetting the slots in a platform specific
way to recover them from error conditions such as Fatal AER errors, Link
Down etc... So introduce pci_host_bridge::reset_slot callback and call it
from pcibios_reset_secondary_bus() if
register. For the error recovery to
succeed (if AER is enabled), all the drivers in the bridge hierarchy should have
the 'err_handlers' populated. Otherwise, the link recovery will fail.
[1]
https://lore.kernel.org/linux-pci/20250221172309.120009-1-manivannan.sadhasi...@linaro.org
On Wed, Apr 16, 2025 at 04:38:01PM +0200, Lukas Wunner wrote:
> On Tue, Apr 15, 2025 at 07:03:17PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Apr 04, 2025 at 10:46:27AM +0200, Lukas Wunner wrote:
> > > On Fri, Apr 04, 2025 at 01:52:22PM +0530, Manivannan Sadhasivam via B4
On Fri, Apr 04, 2025 at 10:46:27AM +0200, Lukas Wunner wrote:
> On Fri, Apr 04, 2025 at 01:52:22PM +0530, Manivannan Sadhasivam via B4 Relay
> wrote:
> > When the PCI error handling requires resetting the slot, reset it using the
> > host bridge specific 'reset_slot'
From: Manivannan Sadhasivam
The PCI link, when down, needs to be recovered to bring it back. But that
cannot be done in a generic way as link recovery procedure is specific to
host bridges. So add a new API pci_host_handle_link_down() that could be
called by the host bridge drivers when the link
From: Manivannan Sadhasivam
When the PCI error handling requires resetting the slot, reset it using the
host bridge specific 'reset_slot' callback if available before calling the
'slot_reset' callback of the PCI drivers.
The 'reset_slot' callback is responsibl
From: Manivannan Sadhasivam
The PCIe link can go down under circumstances such as the device firmware
crash, link instability, etc... When that happens, the PCIe slot needs to
be reset to make it operational again. Currently, the driver is not
handling the link down event, due to which the users
From: Manivannan Sadhasivam
A PCI device is just another peripheral in a system. So failure to
recover it, must not result in a kernel panic. So remove the TODO which
is quite misleading.
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/pcie/err.c | 1 -
1 file changed, 1 deletion
register. For the error recovery to
succeed (if AER is enabled), all the drivers in the bridge hierarchy should have
the 'err_handlers' populated. Otherwise, the link recovery will fail.
[1]
https://lore.kernel.org/linux-pci/20250221172309.120009-1-manivannan.sadhasi...@linaro.org
S
On Tue, Jun 11, 2024 at 05:06:40PM -0500, Bjorn Helgaas wrote:
> On Thu, Jun 06, 2024 at 12:56:35PM +0530, Manivannan Sadhasivam wrote:
> > As like the 'epc_init' event, that is used to signal the EPF drivers about
> > the EPC initialization, let's introduce
On Thu, Jun 06, 2024 at 12:56:33PM +0530, Manivannan Sadhasivam wrote:
> Hi,
>
> This series includes patches that were left over from previous series [1] for
> making the host reboot handling robust in endpoint framework.
>
> When the above mentioned series got merged to pci/
On Fri, Jun 07, 2024 at 11:31:28AM +0200, Niklas Cassel wrote:
> On Thu, Jun 06, 2024 at 12:56:33PM +0530, Manivannan Sadhasivam wrote:
> > Hi,
> >
> > This series includes patches that were left over from previous series [1]
> > for
> > making the host r
ff-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index 35bb481564c7..a4a800699f89 100644
--- a/driver
y the drivers supporting PERST# to handle the
scenario (2) mentioned above.
NOTE: For the sake of code organization, move the dw_pcie_ep_linkup()
definition just above dw_pcie_ep_linkdown().
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-desig
Now that the API is available, let's make use of it. It also handles the
reinitialization of DWC non-sticky registers in addition to sending the
notification to EPF drivers.
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 2
nups in unbind() if already done
in epc_deinit().
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 1 -
drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
drivers/p
Currently dw_pcie_ep_init_notify() wrapper just calls pci_epc_init_notify()
directly. So this wrapper provides no benefit to the glue drivers.
So let's remove it and call pci_epc_init_notify() directly from glue
drivers.
Suggested-by: Bjorn Helgaas
Signed-off-by: Manivannan Sadha
://lore.kernel.org/linux-pci/20240430-pci-epf-rework-v4-0-22832d0d4...@linaro.org/
[2] https://lore.kernel.org/linux-pci/202405130815.bwbriepl-...@intel.com/
[3] https://lore.kernel.org/linux-pci/20240529141614.GA3293@thinkpad/
Signed-off-by: Manivannan Sadhasivam
---
Manivannan Sadhasivam (5
On Fri, Apr 12, 2024 at 02:58:36PM -0500, Bjorn Helgaas wrote:
> On Wed, Mar 27, 2024 at 02:43:31PM +0530, Manivannan Sadhasivam wrote:
> > All of the APIs are missing the Kernel-doc comments. Hence, add them.
>
> > + * dw_pcie_ep_reset_bar - Reset endpoint BAR
>
> App
On Fri, Apr 12, 2024 at 03:22:16PM -0500, Bjorn Helgaas wrote:
> On Wed, Mar 27, 2024 at 02:43:37PM +0530, Manivannan Sadhasivam wrote:
> > "core_init_notifier" flag is set by the glue drivers requiring refclk from
> > the host to complete the DWC core initialization.
in 'init_complete' flag and pci-ep-cfs driver sends the
notification to EPF drivers based on that after each EPF driver bind.
Tested-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 ++
drivers/pci/controller/dw
s to remove the
'core_init_notifier' flag completely in the later commits.
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pci-dra7xx.c | 7 +++
drivers/pci/controller/dwc/pci-imx6.c
ar that it
initializes the DWC specific registers.
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 14 +++---
drivers/pci/controller/dwc/pcie-designware.h| 4 ++--
drivers/pci/controller/dwc/pcie
y, it just removes
eDMA.
Reported-by: Niklas Cassel
Closes: https://lore.kernel.org/linux-pci/ZWYmX8Y%2F7Q9WMxES@x1-carbon
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 19 +--
driver
iewed-by: Frank Li
Reviewed-by: Niklas Cassel
Reviewed-by: Yoshihiro Shimoda
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++---
drivers/pci/controller/dwc/pcie-designware.h| 4 ++--
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +-
3
Reviewed-by: Yoshihiro Shimoda
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 9 +
drivers/pci/controller/dwc/pcie-designware.h| 1 -
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 14 --
3 files changed, 9 insertions(+), 15
All of the APIs are missing the Kernel-doc comments. Hence, add them.
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 77 +
1 file changed, 77 insertions(+)
diff --git a
().
Fixes: e966f7390da9 ("PCI: dwc: Refactor core initialization code for EP mode")
Co-developed-by: Vidya Sagar
Signed-off-by: Vidya Sagar
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 120 ++
e
heavily modified.
Changes in v6:
- Rebased on top of pci/next (6e2fca71e187)
- removed ep_init_late() callback as it is no longer necessary
For previous changelog, please refer [1].
Signed-off-by: Manivannan Sadhasivam
---
Manivannan Sadhasivam (8):
PCI: dwc: ep: Fix DBI access fail
On Wed, Mar 27, 2024 at 09:24:05AM +0100, Niklas Cassel wrote:
> Hello Mani,
>
> On Wed, Mar 27, 2024 at 12:05:54PM +0530, Manivannan Sadhasivam wrote:
> > "core_init_notifier" flag is set by the glue drivers requiring refclk from
> > the host to complete the DWC c
in 'init_complete' flag and pci-ep-cfs driver sends the
notification to EPF drivers based on that after each EPF driver bind.
Tested-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 ++
drivers/pci/controller/dw
s to remove the
'core_init_notifier' flag completely in the later commits.
Reviewed-by: Yoshihiro Shimoda
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pci-dra7xx.c | 7 +++
drivers/pci/controller/dwc/pci-imx6.c
ar that it
initializes the DWC specific registers.
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 14 +++---
drivers/pci/controller/dwc/pcie-designware.h| 4 ++--
drivers/pci/controller/dwc/pcie
y, it just removes
eDMA.
Reported-by: Niklas Cassel
Closes: https://lore.kernel.org/linux-pci/ZWYmX8Y%2F7Q9WMxES@x1-carbon
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 19 +--
driver
iewed-by: Frank Li
Reviewed-by: Niklas Cassel
Reviewed-by: Yoshihiro Shimoda
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++---
drivers/pci/controller/dwc/pcie-designware.h| 4 ++--
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +-
3
Reviewed-by: Yoshihiro Shimoda
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 9 +
drivers/pci/controller/dwc/pcie-designware.h| 1 -
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 14 --
3 files changed, 9 insertions(+), 15
All of the APIs are missing the Kernel-doc comments. Hence, add them.
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 77 +
1 file changed, 77 insertions(+)
diff --git a
().
Fixes: e966f7390da9 ("PCI: dwc: Refactor core initialization code for EP mode")
Co-developed-by: Vidya Sagar
Signed-off-by: Vidya Sagar
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 120 ++
ok over the authorship and dropped the previous Ack as the patches are
heavily modified.
Changes in v6:
- Rebased on top of pci/next (6e2fca71e187)
- removed ep_init_late() callback as it is no longer necessary
For previous changelog, please refer [1].
Signed-off-by: Manivannan Sadhasivam
---
Man
On Fri, Mar 22, 2024 at 12:53:50PM +0100, Niklas Cassel wrote:
> On Thu, Mar 14, 2024 at 01:18:06PM +0530, Manivannan Sadhasivam wrote:
> > "core_init_notifier" flag is set by the glue drivers requiring refclk from
> > the host to complete the DWC core initialization.
in 'init_complete' flag and pci-ep-cfs driver sends the
notification to EPF drivers based on that after each EPF driver bind.
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pci-dra7xx.c | 2 ++
drivers/pci/controller/dwc/pci-imx6.c | 2
s to remove the
'core_init_notifier' flag completely in the later commits.
Reviewed-by: Yoshihiro Shimoda
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pci-dra7xx.c | 7 +++
drivers/pci/controller/dwc/pci-imx6.c | 8
drive
ar that it
initializes the DWC specific registers.
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 14 +++---
drivers/pci/controller/dwc/pcie-designware.h| 4 ++--
drivers/pci/controller/dwc/pcie
y, it just removes
eDMA.
Reported-by: Niklas Cassel
Closes: https://lore.kernel.org/linux-pci/ZWYmX8Y%2F7Q9WMxES@x1-carbon
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 19 +--
driver
iewed-by: Frank Li
Reviewed-by: Niklas Cassel
Reviewed-by: Yoshihiro Shimoda
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++---
drivers/pci/controller/dwc/pcie-designware.h| 4 ++--
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 2 +-
3
Reviewed-by: Yoshihiro Shimoda
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 9 +
drivers/pci/controller/dwc/pcie-designware.h| 1 -
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 14 --
3 files changed, 9 insertions(+), 15
All of the APIs are missing the Kernel-doc comments. Hence, add them.
Reviewed-by: Frank Li
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 78 +
1 file changed, 78 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie
().
Fixes: e966f7390da9 ("PCI: dwc: Refactor core initialization code for EP mode")
Co-developed-by: Vidya Sagar
Signed-off-by: Vidya Sagar
Reviewed-by: Frank Li
Reviewed-by: Niklas Cassel
Signed-off-by: Manivannan Sadhasivam
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 120 ++
Changes in v6:
- Rebased on top of pci/next (6e2fca71e187)
- removed ep_init_late() callback as it is no longer necessary
For previous changelog, please refer [1].
Signed-off-by: Manivannan Sadhasivam
---
Manivannan Sadhasivam (8):
PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk
On Fri, Mar 08, 2024 at 11:22:52AM +0100, Niklas Cassel wrote:
> On Fri, Mar 08, 2024 at 03:19:47PM +0530, Manivannan Sadhasivam wrote:
> > > > > > @@ -467,6 +467,13 @@ static int dra7xx_add_pcie_ep(struct
> > > > > > dra7xx_pcie *dra
On Mon, Mar 11, 2024 at 10:54:28PM +0100, Niklas Cassel wrote:
> On Mon, Mar 11, 2024 at 08:15:59PM +0530, Manivannan Sadhasivam wrote:
> > >
> > > I would say that it is the following change that breaks things:
> > >
> > > > - if (!core_in
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