On Thu, Jun 06, 2019 at 04:39:04PM -0300, Murilo Opsfelder Araújo wrote:
> Claudio Carvalho writes:
>
> > From: Ram Pai
> >
> > Ultravisor is responsible for flushing the tlb cache, since it manages
> > the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
> > available.
> >
> >
On Tue, Apr 30, 2019 at 12:39:03PM +, Christophe Leroy wrote:
> This patch implements a fast entry for syscalls.
>
> Syscalls don't have to preserve non volatile registers except LR.
>
> This patch then implement a fast entry for syscalls, where
> volatile registers get clobbered.
>
> As
On Tue, May 21, 2019 at 07:13:26AM +0200, Christoph Hellwig wrote:
> On Tue, May 21, 2019 at 01:49:02AM -0300, Thiago Jung Bauermann wrote:
> > From: Benjamin Herrenschmidt
> >
> > For secure VMs, the signing tool will create a ticket called the "ESM blob"
> > for the Enter Secure Mode
On Sat, May 18, 2019 at 11:25:23AM -0300, Claudio Carvalho wrote:
> From: Paul Mackerras
>
> - Pass SRR1 in r11 for UV_RETURN because SRR0 and SRR1 get set by
> the sc 2 instruction. (Note r3 - r10 potentially have hcall return
> values in them.)
>
> - Fix kvmppc_msr_
On Sat, May 18, 2019 at 11:25:22AM -0300, Claudio Carvalho wrote:
> From: Sukadev Bhattiprolu
>
> All hcalls from a secure VM go to the ultravisor from where they are
> reflected into the HV. When we (HV) complete processing such hcalls,
> we should return to the UV rather than to the guest
On Sat, May 18, 2019 at 11:25:21AM -0300, Claudio Carvalho wrote:
> From: Ram Pai
>
> When the ultravisor firmware is available, it takes control over the
> LDBAR register. In this case, thread-imc updates and save/restore
> operations on the LDBAR register are handled by ultravisor.
>
>
On Sun, Apr 28, 2019 at 09:45:15PM +1000, Nicholas Piggin wrote:
> This is the KVM update to the new idle code. A few improvements:
>
> - Idle sleepers now always return to caller rather than branch out
> to KVM first.
> - This allows optimisations like very fast return to caller when no
>
On Thu, Apr 25, 2019 at 12:53:39PM -0700, Palmer Dabbelt wrote:
> I made the same typo when trying to grep for uses of smp_wmb and figured
> I might as well fix it.
>
> Signed-off-by: Palmer Dabbelt
Thanks, patch applied to my kvm-ppc-next tree.
Paul.
On Wed, Apr 03, 2019 at 03:16:12PM +0100, Steven Price wrote:
> Since pmd_large() is now always available, pmd_is_leaf() is redundant.
> Replace all uses with calls to pmd_large().
NAK. I don't want to do this, because pmd_is_leaf() is purely about
the guest page tables (the "partition-scoped"
On Wed, Mar 20, 2019 at 03:39:50PM -0300, Fabiano Rosas wrote:
> When calling the KVM_SET_GUEST_DEBUG ioctl, userspace might request
> the next instruction to be single stepped via the
> KVM_GUESTDBG_SINGLESTEP control bit of the kvm_guest_debug structure.
>
> We currently don't have support for
On Wed, Apr 10, 2019 at 07:04:48PM +0200, Cédric Le Goater wrote:
> When a P9 sPAPR VM boots, the CAS negotiation process determines which
> interrupt mode to use (XICS legacy or XIVE native) and invokes a
> machine reset to activate the chosen mode.
>
> To be able to switch from one mode to
On Wed, Apr 10, 2019 at 07:04:48PM +0200, Cédric Le Goater wrote:
> When a P9 sPAPR VM boots, the CAS negotiation process determines which
> interrupt mode to use (XICS legacy or XIVE native) and invokes a
> machine reset to activate the chosen mode.
>
> To be able to switch from one mode to
On Wed, Mar 20, 2019 at 09:37:44AM +0100, Cédric Le Goater wrote:
> The state of the thread interrupt management registers needs to be
> collected for migration. These registers are cached under the
> 'xive_saved_state.w01' field of the VCPU when the VPCU context is
> pulled from the HW thread. An
On Fri, Mar 01, 2019 at 05:52:51PM +1100, Michael Ellerman wrote:
> Suraj Jitindar Singh writes:
>
> > Add KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST &
> > KVM_PPC_CPU_BEHAV_FLUSH_COUNT_CACHE to the characteristics returned from
> > the H_GET_CPU_CHARACTERISTICS H-CALL, as queried from either the
> >
On Wed, Feb 27, 2019 at 07:41:21AM +0100, Christophe Leroy wrote:
>
>
> Le 26/02/2019 à 23:24, Paul Mackerras a écrit :
> >On Tue, Feb 26, 2019 at 11:59:08AM +0200, Mike Rapoport wrote:
> >>On Tue, Feb 26, 2019 at 10:39:54AM +0100, Christophe Leroy wrote:
> >>&
On Tue, Feb 26, 2019 at 11:59:08AM +0200, Mike Rapoport wrote:
> On Tue, Feb 26, 2019 at 10:39:54AM +0100, Christophe Leroy wrote:
> >
> >
> > Le 26/02/2019 à 09:12, Mike Rapoport a écrit :
> > >Hi,
> > >
> > >I've encountered the following error when building skyroot_defconfig with
> > >current
S: Allow XICS emulation to work in nested
hosts using XIVE")
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/kvm_ppc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/kvm_ppc.h
b/arch/powerpc/include/asm/kvm_ppc.h
index d283d31..ac22b28
On Fri, Feb 22, 2019 at 12:28:30PM +0100, Cédric Le Goater wrote:
> These controls will be used by the H_INT_SET_QUEUE_CONFIG and
> H_INT_GET_QUEUE_CONFIG hcalls from QEMU. They will also be used to
> restore the configuration of the XIVE EQs in the KVM device and to
> capture the internal runtime
On Mon, Feb 25, 2019 at 01:10:12PM +1100, David Gibson wrote:
> On Fri, Feb 22, 2019 at 12:28:28PM +0100, Cédric Le Goater wrote:
> > + /*
> > +* If the source doesn't already have an IPI, allocate
> > +* one and get the corresponding data
> > +*/
> > + if (!state->ipi_number) {
>
On Fri, Feb 22, 2019 at 12:28:28PM +0100, Cédric Le Goater wrote:
> The associated HW interrupt source is simply allocated at the OPAL/HW
> level and then MASKED. KVM only needs to know about its type: LSI or
> MSI.
I think it would be helpful to explain to the reader here that with
XIVE, all
On Mon, Feb 25, 2019 at 11:35:27AM +1100, David Gibson wrote:
> On Fri, Feb 22, 2019 at 12:28:27PM +0100, Cédric Le Goater wrote:
> > + xc->xive = xive;
> > + xc->vcpu = vcpu;
> > + xc->server_num = cpu;
> > + xc->vp_id = xive->vp_base + cpu;
>
> Hrm. This ties the internal VP id to the
On Fri, Feb 22, 2019 at 12:28:27PM +0100, Cédric Le Goater wrote:
> The user interface exposes a new capability to let QEMU connect the
> vCPU to the XIVE KVM device if required. The capability is only
> advertised on a PowerNV Hypervisor as support for nested guests
> (pseries KVM Hypervisor) is
On Thu, Feb 21, 2019 at 02:28:48PM +1100, Jordan Niethe wrote:
> Currently trying to build without IOMMU support will fail:
>
> (.text+0x1380): undefined reference to `kvmppc_h_get_tce'
> (.text+0x1384): undefined reference to `kvmppc_rm_h_put_tce'
> (.text+0x149c): undefined reference to
On Thu, Feb 21, 2019 at 02:44:14PM +1100, Alexey Kardashevskiy wrote:
> The anon fd's ops releases the KVM reference in the release hook.
> However we reference the KVM object after we create the fd so there is
> small window when the release function can be called and
> dereferenced the KVM
On Tue, Feb 12, 2019 at 03:37:45PM +1100, Alexey Kardashevskiy wrote:
> The SPAPR TCE KVM device references all hardware IOMMU tables assigned to
> some IOMMU group to ensure that in-kernel KVM acceleration of H_PUT_TCE
> can work. The tables are references when an IOMMU group gets registered
>
On Thu, Feb 07, 2019 at 03:56:50PM +1100, Suraj Jitindar Singh wrote:
> Devices on the KVM_FAST_MMIO_BUS by definition have length zero and are
> thus used for notification purposes rather than data transfer. For
> example eventfd for virtio devices.
>
> This means that when emulating mmio
On Tue, Feb 19, 2019 at 02:53:45PM +1100, Suraj Jitindar Singh wrote:
> This adds an entry to the kvm_stats_debugfs directory which provides the
> number of large (2M or 1G) pages which have been used to setup the guest
> mappings.
>
> Signed-off-by: Suraj Jitindar Singh
Thanks, applied to my
This adds an "in_guest" parameter to machine_check_print_event_info()
so that we can avoid trying to translate guest NIP values into
symbolic form using the host kernel's symbol table.
Reviewed-by: Aravinda Prasad
Reviewed-by: Mahesh Salgaonkar
Signed-off-by: Paul Mackerras
---
v2:
that are not
FWNMI-capable.
Reviewed-by: Aravinda Prasad
Reviewed-by: Mahesh Salgaonkar
Signed-off-by: Paul Mackerras
---
v2: fix comment as requested by Aravinda
arch/powerpc/include/asm/kvm_ppc.h | 3 +-
arch/powerpc/kvm/book3s.c | 7
arch/powerpc/kvm/book3s_hv.c
On Wed, Feb 20, 2019 at 03:59:58PM +1100, Russell Currey wrote:
> Using the hash MMU on P7+, the AMR is used for pkeys. It's important
This needs a bit of rewording. The "Using" ... "used" construct is a
bit confusing on the first read. Also, there was a processor called
P7+, but I think
that are not
FWNMI-capable.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/kvm_ppc.h | 3 +-
arch/powerpc/kvm/book3s.c | 7 +
arch/powerpc/kvm/book3s_hv.c| 18 +--
arch/powerpc/kvm/book3s_hv_ras.c| 56 +
arch
This adds an "in_guest" parameter to machine_check_print_event_info()
so that we can avoid trying to translate guest NIP values into
symbolic form using the host kernel's symbol table.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/mce.h| 2 +-
arch/powerpc/ke
On Tue, Feb 19, 2019 at 02:13:51PM +1000, Nicholas Piggin wrote:
> Paul Mackerras's on February 18, 2019 9:06 am:
> > On Sat, Oct 13, 2018 at 10:04:09PM +1000, Nicholas Piggin wrote:
> >> Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
> >> speific HV idle code to the powernv
On Wed, Jan 30, 2019 at 11:37:25AM +0530, Bharata B Rao wrote:
> H_SVM_INIT_START: Initiate securing a VM
> H_SVM_INIT_DONE: Conclude securing a VM
>
> During early guest init, these hcalls will be issued by UV.
> As part of these hcalls, [un]register memslots with UV.
That last sentence is a
On Sat, Oct 13, 2018 at 10:04:09PM +1000, Nicholas Piggin wrote:
> Reimplement Book3S idle code in C, moving POWER7/8/9 implementation
> speific HV idle code to the powernv platform code.
>
[...]
> @@ -2760,21 +2744,47 @@ BEGIN_FTR_SECTION
> li r4, LPCR_PECE_HVEE@higher
> sldi
nly on
Hotplug")
Cc: sta...@vger.kernel.org # v4.14+
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/powernv.h| 2 ++
arch/powerpc/platforms/powernv/idle.c | 27 ++-
arch/powerpc/platforms/powernv/smp.c | 25 +
3 files changed,
On Fri, Feb 08, 2019 at 08:58:14AM +0100, Cédric Le Goater wrote:
> On 2/8/19 6:15 AM, David Gibson wrote:
> > On Thu, Feb 07, 2019 at 10:03:15AM +0100, Cédric Le Goater wrote:
> >> That's the plan I have in mind as suggested by Paul if I understood it
> >> well.
> >> The mechanics are more
On Tue, Feb 05, 2019 at 12:31:28PM +0100, Cédric Le Goater wrote:
> >>> As for nesting, I suggest for the foreseeable future we stick to XICS
> >>> emulation in nested guests.
> >>
> >> ok. so no kernel_irqchip at all. hmm.
>
> I was confused with what Paul calls 'XICS emulation'. It's not the
On Wed, Jan 30, 2019 at 08:01:22AM +0100, Cédric Le Goater wrote:
> On 1/30/19 5:29 AM, Paul Mackerras wrote:
> > On Mon, Jan 28, 2019 at 06:35:34PM +0100, Cédric Le Goater wrote:
> >> On 1/22/19 6:05 AM, Paul Mackerras wrote:
> >>> On Mon, Jan 07, 2019 at 07:43:17PM
On Wed, Jan 30, 2019 at 04:54:23PM +0100, Cédric Le Goater wrote:
> On 1/30/19 7:20 AM, Paul Mackerras wrote:
> > On Tue, Jan 29, 2019 at 02:47:55PM +0100, Cédric Le Goater wrote:
> >> On 1/29/19 3:45 AM, Paul Mackerras wrote:
> >>> On Mon, Jan 28, 2019 at 07:26:00PM
On Mon, Jan 28, 2019 at 06:35:34PM +0100, Cédric Le Goater wrote:
> On 1/22/19 6:05 AM, Paul Mackerras wrote:
> > On Mon, Jan 07, 2019 at 07:43:17PM +0100, Cédric Le Goater wrote:
> >> This is the basic framework for the new KVM device supporting the XIVE
> >> native
On Tue, Jan 29, 2019 at 02:51:05PM +0100, Cédric Le Goater wrote:
> >>> Another general comment is that you seem to have written all this
> >>> code assuming we are using HV KVM in a host running bare-metal.
> >>
> >> Yes. I didn't look at the other configurations. I thought that we could
> >> use
On Tue, Jan 29, 2019 at 02:47:55PM +0100, Cédric Le Goater wrote:
> On 1/29/19 3:45 AM, Paul Mackerras wrote:
> > On Mon, Jan 28, 2019 at 07:26:00PM +0100, Cédric Le Goater wrote:
> >> On 1/28/19 7:13 AM, Paul Mackerras wrote:
> >>> Would we end up with too
On Tue, Jan 29, 2019 at 06:44:50PM +0100, Cédric Le Goater wrote:
> On 1/29/19 5:12 AM, Paul Mackerras wrote:
> > On Mon, Jan 28, 2019 at 07:26:00PM +0100, Cédric Le Goater wrote:
> >>
> >> Is clearing the PTEs and repopulating the VMA unsafe ?
> >
>
On Mon, Jan 28, 2019 at 07:26:00PM +0100, Cédric Le Goater wrote:
>
> Is clearing the PTEs and repopulating the VMA unsafe ?
Actually, now that I come to think of it, there could be any number of
VMAs (well, up to almost 64k of them), since once you have a file
descriptor you can call mmap on
On Mon, Jan 28, 2019 at 07:26:00PM +0100, Cédric Le Goater wrote:
> On 1/28/19 7:13 AM, Paul Mackerras wrote:
> > Would we end up with too many VMAs if we just used mmap() to
> > change the mappings from the software-generated pages to the
> > hardware-generated interrupt pag
On Wed, Jan 23, 2019 at 12:07:19PM +0100, Cédric Le Goater wrote:
> On 1/23/19 11:30 AM, Paul Mackerras wrote:
> > On Wed, Jan 23, 2019 at 05:45:24PM +1100, Benjamin Herrenschmidt wrote:
> >> On Tue, 2019-01-22 at 16:26 +1100, Paul Mackerras wrote:
> >>> On Mon, Ja
On Wed, Jan 23, 2019 at 08:07:33PM +0100, Cédric Le Goater wrote:
> On 1/22/19 5:46 AM, Paul Mackerras wrote:
> > On Mon, Jan 07, 2019 at 07:43:12PM +0100, Cédric Le Goater wrote:
> >> Hello,
> >>
> >> On the POWER9 processor, the XIVE interrupt controller can
On Thu, Jan 24, 2019 at 08:25:15AM +1100, Benjamin Herrenschmidt wrote:
> On Wed, 2019-01-23 at 21:30 +1100, Paul Mackerras wrote:
> > > Afaik bcs we change the mapping to point to the real HW irq ESB page
> > > instead of the "IPI" that was there at VM init time.
On Wed, Jan 23, 2019 at 09:48:31AM +0100, Cédric Le Goater wrote:
> On 1/23/19 7:44 AM, Benjamin Herrenschmidt wrote:
> > On Tue, 2019-01-22 at 16:23 +1100, Paul Mackerras wrote:
> >> Why do we need to provide real-mode versions of these hypercall
> >> handlers? I tho
On Wed, Jan 23, 2019 at 05:45:24PM +1100, Benjamin Herrenschmidt wrote:
> On Tue, 2019-01-22 at 16:26 +1100, Paul Mackerras wrote:
> > On Mon, Jan 07, 2019 at 08:10:05PM +0100, Cédric Le Goater wrote:
> > > Clear the ESB pages from the VMA of the IRQ being pass through to the
&
On Mon, Jan 07, 2019 at 07:43:20PM +0100, Cédric Le Goater wrote:
> The ESB MMIO region controls the interrupt sources of the guest. QEMU
> will query an fd (GET_ESB_FD ioctl) and map this region at a specific
> address for the guest to use. The guest will obtain this information
> using the
On Mon, Jan 07, 2019 at 07:43:23PM +0100, Cédric Le Goater wrote:
> The XIVE native exploitation mode specs define a set of Hypervisor
> calls to configure the sources and the event queues :
>
> - H_INT_GET_SOURCE_INFO
>
>used to obtain the address of the MMIO page of the Event State
>
On Mon, Jan 07, 2019 at 08:10:06PM +0100, Cédric Le Goater wrote:
> This will be used to destroy the KVM XICS or XIVE device when the
> sPAPR machine is reseted. When the VM boots, the CAS negotiation
> process will determine which interrupt mode to use and the appropriate
> KVM device will then
On Mon, Jan 07, 2019 at 07:43:18PM +0100, Cédric Le Goater wrote:
> This will let the guest create a memory mapping to expose the ESB MMIO
> regions used to control the interrupt sources, to trigger events, to
> EOI or to turn off the sources.
>
> Signed-off-by: Cédric Le Goater
> ---
>
On Mon, Jan 07, 2019 at 07:43:15PM +0100, Cédric Le Goater wrote:
> We will have different KVM devices for interrupts, one for the
> XICS-over-XIVE mode and one for the XIVE native exploitation
> mode. Let's add some checks to make sure we are not mixing the
> interfaces in KVM.
>
>
On Mon, Jan 07, 2019 at 08:10:05PM +0100, Cédric Le Goater wrote:
> Clear the ESB pages from the VMA of the IRQ being pass through to the
> guest and let the fault handler repopulate the VMA when the ESB pages
> are accessed for an EOI or for a trigger.
Why do we want to do this?
I don't see any
On Mon, Jan 07, 2019 at 07:43:17PM +0100, Cédric Le Goater wrote:
> This is the basic framework for the new KVM device supporting the XIVE
> native exploitation mode. The user interface exposes a new capability
> and a new KVM device to be used by QEMU.
[snip]
> @@ -1039,7 +1039,10 @@ static int
On Mon, Jan 07, 2019 at 07:43:12PM +0100, Cédric Le Goater wrote:
> Hello,
>
> On the POWER9 processor, the XIVE interrupt controller can control
> interrupt sources using MMIO to trigger events, to EOI or to turn off
> the sources. Priority management and interrupt acknowledgment is also
>
On Tue, Jan 15, 2019 at 11:49:45PM +0100, Tobias Ulmer wrote:
> Hi,
>
> both the latest stable 4.20.2 and 5.0 rc2+ hang early on the G5 Quad.
Interesting, I just built v4.20 with g5_defconfig for my quad and it
booted just fine. I'll try Linus' latest.
It could be config-related; could you
On Fri, Dec 07, 2018 at 02:43:18PM +1100, Suraj Jitindar Singh wrote:
> When booting a kvm-pr guest on a POWER9 machine the following message is
> observed:
> "qemu-system-ppc64: KVM does not support 1TiB segments which guest expects"
>
> This is because the guest is expecting to be able to use
On Mon, Nov 05, 2018 at 09:47:17AM -0500, Yangtao Li wrote:
> Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
>
> Signed-off-by: Yangtao Li
Thanks, patch applied to my kvm-ppc-next branch.
Paul.
On Fri, Dec 14, 2018 at 04:29:02PM +1100, Suraj Jitindar Singh wrote:
> This patch series allows for emulated devices to be passed through to nested
> guests, irrespective of at which level the device is being emulated.
>
> Note that the emulated device must be using dma, not virtio.
>
> For
o_page().
>
> This adds a check for device memory in mm_iommu_ua_mark_dirty_rm() which
> does delayed pages dirtying.
>
> Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Paul Mackerras
On Mon, Dec 10, 2018 at 02:58:24PM +1100, Suraj Jitindar Singh wrote:
> A guest cannot access quadrants 1 or 2 as this would result in an
> exception. Thus introduce the hcall H_COPY_TOFROM_GUEST to be used by a
> guest when it wants to perform an access to quadrants 1 or 2, for
> example when it
On Fri, Nov 23, 2018 at 04:52:48PM +1100, Alexey Kardashevskiy wrote:
> This new memory does not have page structs as it is not plugged to
> the host so gup() will fail anyway.
>
> This adds 2 helpers:
> - mm_iommu_newdev() to preregister the "memory device" memory so
> the rest of API can still
turn value(s) mean that the caller should flush the tlb. I would
guess that non-zero means to do the flush, but you should make that
explicit.
> Signed-off-by: Lan Tianyu
For the powerpc bits:
Acked-by: Paul Mackerras
On Fri, Dec 07, 2018 at 10:08:20PM +1100, Michael Ellerman wrote:
> Suraj Jitindar Singh writes:
>
> > When booting a kvm-pr guest on a POWER9 machine the following message is
> > observed:
> > "qemu-system-ppc64: KVM does not support 1TiB segments which guest expects"
> >
> > This is because
"powerpc/boot: Allow building the zImage wrapper as a
relocatable ET_DYN")
Signed-off-by: Paul Mackerras
---
arch/powerpc/boot/crt0.S | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/crt0.S b/arch/powerpc/boot/crt0.S
index 32dfe6d..9b9d174 100644
On Mon, Oct 29, 2018 at 11:31:55PM -0700, Ram Pai wrote:
> On Tue, Oct 30, 2018 at 04:03:00PM +1100, Paul Mackerras wrote:
> > On Mon, Oct 22, 2018 at 10:48:34AM +0530, Bharata B Rao wrote:
> > > HMM driver for KVM PPC to manage page transitions of
> > > sec
On Mon, Oct 22, 2018 at 10:48:34AM +0530, Bharata B Rao wrote:
> HMM driver for KVM PPC to manage page transitions of
> secure guest via H_SVM_PAGE_IN and H_SVM_PAGE_OUT hcalls.
>
> H_SVM_PAGE_IN: Move the content of a normal page to secure page
> H_SVM_PAGE_OUT: Move the content of a secure page
On Mon, Oct 22, 2018 at 10:48:35AM +0530, Bharata B Rao wrote:
> A secure guest will share some of its pages with hypervisor (Eg. virtio
> bounce buffers etc). Support shared pages in HMM driver.
>
> Signed-off-by: Bharata B Rao
Comments below...
> ---
> arch/powerpc/kvm/book3s_hv_hmm.c | 69
On Mon, Oct 22, 2018 at 10:48:36AM +0530, Bharata B Rao wrote:
> H_SVM_INIT_START: Initiate securing a VM
> H_SVM_INIT_DONE: Conclude securing a VM
>
> During early guest init, these hcalls will be issued by UV.
> As part of these hcalls, [un]register memslots with UV.
>
> Signed-off-by: Bharata
On Fri, Oct 26, 2018 at 01:55:44AM +0530, Naveen N. Rao wrote:
> When the dtl debugfs interface is used, we usually set the
> dtl_enable_mask to 0x7 (DTL_LOG_ALL). When this happens, we start seeing
> DTL entries for all preempt reasons, including CEDE. In
> scan_dispatch_log(), we add up the
On Mon, Oct 15, 2018 at 09:08:41PM +1100, Alexey Kardashevskiy wrote:
> The powernv platform maintains 2 TCE tables for VFIO - a hardware TCE
> table and a table with userspace addresses. These tables are radix trees,
> we allocate indirect levels when they are written to. Since
> the memory
struct. Similarly, the HV-KVM code that did
the same conversion using arithmetic on tb_ticks_per_sec also now
uses tb_to_ns().
Signed-off-by: Paul Mackerras
---
v2: don't delete the second do_div in kvmppc_emulate_dec(), we need it.
arch/powerpc/kvm/book3s_hv.c | 3 +--
arch/powerpc/kvm/emulate.c
struct. Similarly, the HV-KVM code that did
the same conversion using arithmetic on tb_ticks_per_sec also now
uses tb_to_ns().
Signed-off-by: Paul Mackerras
---
arch/powerpc/kvm/book3s_hv.c | 3 +--
arch/powerpc/kvm/emulate.c | 6 ++
2 files changed, 3 insertions(+), 6 deletions(-)
diff
On Tue, Oct 16, 2018 at 07:05:16PM +0200, Greg Kroah-Hartman wrote:
> 4.18-stable review patch. If anyone has any objections, please let me know.
>
> --
>
> From: Nicholas Piggin
>
> [ Upstream commit 71d29f43b6332badc5598c656616a62575e83342 ]
If you take 71d29f43b633 then
be taken as
indicating only that the new HPT features in ISA V3.0 are not
supported, leaving it ambiguous whether pre-V3.0 HPT features
are supported.
Signed-off-by: Paul Mackerras
---
Documentation/virtual/kvm/api.txt | 4
arch/powerpc/kvm/book3s_hv.c | 4
include/uapi/linux/kvm.h
capability on a guest will fail). Guests which are already nested
hypervisors will continue to be so.
Signed-off-by: Paul Mackerras
---
Documentation/virtual/kvm/api.txt | 14 ++
arch/powerpc/include/asm/kvm_ppc.h | 1 +
arch/powerpc/kvm/book3s_hv.c
hypervisors (by returning false for the
KVM_CAP_PPC_MMU_HASH_V3 capability), and to prevent userspace from
configuring a guest to use HPT mode.
Signed-off-by: Paul Mackerras
---
arch/powerpc/kvm/book3s_hv.c | 16
arch/powerpc/kvm/powerpc.c | 3 ++-
2 files changed, 14 insertions
This adds a list of valid shadow PTEs for each nested guest to
the 'radix' file for the guest in debugfs. This can be useful for
debugging.
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/kvm_book3s_64.h | 1 +
arch/powerpc/kvm/book3s_64_mmu_radix.c
-by: Paul Mackerras
---
arch/powerpc/kvm/book3s_hv_nested.c | 51 -
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c
b/arch/powerpc/kvm/book3s_hv_nested.c
index e2305962..3f21f78 100644
--- a/arch/powerpc/kvm
hv_regs. We don't need
to sanitise when copying back the L1 hv_regs since these shouldn't be
able to contain invalid values as they're just what was copied out.
Reviewed-by: David Gibson
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/reg.h | 1
is the only extra requirement for migrating a
guest which has nested guests (assuming of course that the destination
host supports nested virtualization in the kvm-hv module).
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
---
Documentation/virtual/kvm/api.txt | 1 +
arch/powerpc/include/uapi
in kvmppc_mmu_hv_init()
since its only caller already checks this.
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 7 +++
arch/powerpc/kvm/book3s_hv.c| 33 +
2 files changed, 24 insertions(+), 16
.
This introduces a limit on the the vcpu_token values used in the
H_ENTER_NESTED hcall -- they must now be less than NR_CPUS.
[pau...@ozlabs.org - made prev_cpu array be short[] to reduce
memory consumption.]
Reviewed-by: David Gibson
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: Paul Mackerras
to partition-scoped page tables or the
partition table without needing to do hypervisor-privileged tlbie
instructions.
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/kvm_book3s_64.h | 5 +
arch/powerpc/kvm/book3s_64_mmu_radix.c | 30
ed-off-by: Suraj Jitindar Singh
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/kvm_book3s.h| 3 +
arch/powerpc/include/asm/kvm_book3s_64.h | 69 +++-
arch/powerpc/kvm/book3s_64_mmu_radix.c | 44 +++---
arch/powerpc/kvm/book3s_hv.c | 1 +
arch/power
lues).
[pau...@ozlabs.org - adapted to having the partition table in guest
memory, added the H_TLB_INVALIDATE implementation, removed tlbie
instruction emulation, reworded the commit message.]
Reviewed-by: David Gibson
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: Paul Mackerras
---
arch/powerpc
large number of functions in book3s_64_mmu_radix.c for
this we also needed to refactor a number of these functions to take
an lpid parameter so that the correct lpid is used for tlb invalidations.
The functionality however has remained the same.
Reviewed-by: David Gibson
Signed-off-by: Suraj Jitindar Si
, then the
virtual-mode handlers assume that they are being called only to finish
up the operation. Therefore we turn off the real-mode flag in the XICS
code when running as a nested hypervisor.
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/asm-prototypes.h
This adds code to call the H_IPI and H_EOI hypercalls when we are
running as a nested hypervisor (i.e. without the CPU_FTR_HVMODE cpu
feature) and we would otherwise access the XICS interrupt controller
directly or via an OPAL call.
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
-by: Paul Mackerras
---
arch/powerpc/include/asm/hvcall.h | 36 +
arch/powerpc/include/asm/kvm_book3s.h | 7 +
arch/powerpc/include/asm/kvm_host.h | 5 +
arch/powerpc/kernel/asm-offsets.c | 1 +
arch/powerpc/kvm/book3s_hv.c| 214
(or later) processor.
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/hvcall.h | 5 +
arch/powerpc/include/asm/kvm_book3s.h | 10 +-
arch/powerpc/include/asm/kvm_book3s_64.h | 33
arch/powerpc/include/asm/kvm_book3s_asm.h | 3 +
arch/powerpc/include/asm/kvm_host.h
for any pgtable, not specific to the one for this guest.
[pau...@ozlabs.org - reduced diffs from previous code]
Reviewed-by: David Gibson
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: Paul Mackerras
---
arch/powerpc/kvm/book3s_64_mmu_radix.c | 210 +++--
1 file
kvmppc_unmap_pte() does a sequence of operations that are open-coded in
kvm_unmap_radix(). This extends kvmppc_unmap_pte() a little so that it
can be used by kvm_unmap_radix(), and makes kvm_unmap_radix() call it.
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
---
arch/powerpc/kvm
through the
process tables or a guest real address through the partition tables.
[pau...@ozlabs.org - reduced diffs from previous code]
Reviewed-by: David Gibson
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/kvm_book3s.h | 3 +
arch/powerpc/kvm
as a nested hypervisor the
real hypervisor could use this to determine when it can free resources.
Reviewed-by: David Gibson
Signed-off-by: Suraj Jitindar Singh
Signed-off-by: Paul Mackerras
---
arch/powerpc/kvm/book3s_hv.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git
. This changes the code to use the regs.ccr field
instead of cr, and changes the assembly code on 64-bit platforms to
use 64-bit loads and stores instead of 32-bit ones.
Reviewed-by: David Gibson
Signed-off-by: Paul Mackerras
---
arch/powerpc/include/asm/kvm_book3s.h| 4 ++--
arch/powerpc/include/asm
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